Revision 6d5c34fa
| b/target-ppc/translate.c | ||
|---|---|---|
| 7751 | 7751 |
return; |
| 7752 | 7752 |
} |
| 7753 | 7753 |
#if defined(TARGET_PPC64) |
| 7754 |
tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
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|
| 7754 |
tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
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|
| 7755 | 7755 |
#else |
| 7756 |
tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
|
|
| 7757 |
tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
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|
| 7756 |
tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
|
|
| 7757 |
tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
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|
| 7758 | 7758 |
#endif |
| 7759 | 7759 |
} |
| 7760 | 7760 |
static inline void gen_evfsnabs(DisasContext *ctx) |
| ... | ... | |
| 7764 | 7764 |
return; |
| 7765 | 7765 |
} |
| 7766 | 7766 |
#if defined(TARGET_PPC64) |
| 7767 |
tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
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|
| 7767 |
tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
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|
| 7768 | 7768 |
#else |
| 7769 |
tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
|
|
| 7770 |
tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
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|
| 7769 |
tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
|
|
| 7770 |
tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
|
|
| 7771 | 7771 |
#endif |
| 7772 | 7772 |
} |
| 7773 | 7773 |
static inline void gen_evfsneg(DisasContext *ctx) |
| ... | ... | |
| 7777 | 7777 |
return; |
| 7778 | 7778 |
} |
| 7779 | 7779 |
#if defined(TARGET_PPC64) |
| 7780 |
tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
|
|
| 7780 |
tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
|
|
| 7781 | 7781 |
#else |
| 7782 |
tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
|
|
| 7783 |
tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
|
|
| 7782 |
tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
|
|
| 7783 |
tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
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|
| 7784 | 7784 |
#endif |
| 7785 | 7785 |
} |
| 7786 | 7786 |
|
| ... | ... | |
| 7832 | 7832 |
gen_exception(ctx, POWERPC_EXCP_APU); |
| 7833 | 7833 |
return; |
| 7834 | 7834 |
} |
| 7835 |
tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
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|
| 7835 |
tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
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|
| 7836 | 7836 |
} |
| 7837 | 7837 |
static inline void gen_efsnabs(DisasContext *ctx) |
| 7838 | 7838 |
{
|
| ... | ... | |
| 7840 | 7840 |
gen_exception(ctx, POWERPC_EXCP_APU); |
| 7841 | 7841 |
return; |
| 7842 | 7842 |
} |
| 7843 |
tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
|
|
| 7843 |
tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
|
|
| 7844 | 7844 |
} |
| 7845 | 7845 |
static inline void gen_efsneg(DisasContext *ctx) |
| 7846 | 7846 |
{
|
| ... | ... | |
| 7848 | 7848 |
gen_exception(ctx, POWERPC_EXCP_APU); |
| 7849 | 7849 |
return; |
| 7850 | 7850 |
} |
| 7851 |
tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
|
|
| 7851 |
tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
|
|
| 7852 | 7852 |
} |
| 7853 | 7853 |
|
| 7854 | 7854 |
/* Conversion */ |
| ... | ... | |
| 7901 | 7901 |
return; |
| 7902 | 7902 |
} |
| 7903 | 7903 |
#if defined(TARGET_PPC64) |
| 7904 |
tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
|
|
| 7904 |
tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
|
|
| 7905 | 7905 |
#else |
| 7906 |
tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000); |
|
| 7906 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
|
| 7907 |
tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000); |
|
| 7907 | 7908 |
#endif |
| 7908 | 7909 |
} |
| 7909 | 7910 |
static inline void gen_efdnabs(DisasContext *ctx) |
| ... | ... | |
| 7913 | 7914 |
return; |
| 7914 | 7915 |
} |
| 7915 | 7916 |
#if defined(TARGET_PPC64) |
| 7916 |
tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
|
|
| 7917 |
tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
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|
| 7917 | 7918 |
#else |
| 7918 |
tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000); |
|
| 7919 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
|
| 7920 |
tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000); |
|
| 7919 | 7921 |
#endif |
| 7920 | 7922 |
} |
| 7921 | 7923 |
static inline void gen_efdneg(DisasContext *ctx) |
| ... | ... | |
| 7925 | 7927 |
return; |
| 7926 | 7928 |
} |
| 7927 | 7929 |
#if defined(TARGET_PPC64) |
| 7928 |
tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
|
|
| 7930 |
tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
|
|
| 7929 | 7931 |
#else |
| 7930 |
tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000); |
|
| 7932 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
|
| 7933 |
tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000); |
|
| 7931 | 7934 |
#endif |
| 7932 | 7935 |
} |
| 7933 | 7936 |
|
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