Archipelago » qemu

/*

   SPARC translation

   Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>

   Copyright (C) 2003-2005 Fabrice Bellard

   This library is free software; you can redistribute it and/or

   modify it under the terms of the GNU Lesser General Public

   License as published by the Free Software Foundation; either

   version 2 of the License, or (at your option) any later version.

   This library is distributed in the hope that it will be useful,

   but WITHOUT ANY WARRANTY; without even the implied warranty of

   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

   Lesser General Public License for more details.

   You should have received a copy of the GNU Lesser General Public

   License along with this library; if not, write to the Free Software

   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

 */

/*

   TODO-list:

   Rest of V9 instructions, VIS instructions

   NPC/PC static optimisations (use JUMP_TB when possible)

   Optimize synthetic instructions

   128-bit float

*/

#include <stdarg.h>

#include <stdlib.h>

#include <stdio.h>

#include <string.h>

#include <inttypes.h>

#include "cpu.h"

#include "exec-all.h"

#include "disas.h"

#define DEBUG_DISAS

#define DYNAMIC_PC  1 /* dynamic pc value */

#define JUMP_PC     2 /* dynamic pc value which takes only two values

                         according to jump_pc[T2] */

typedef struct DisasContext {

    target_ulong pc;    /* current Program Counter: integer or DYNAMIC_PC */

    target_ulong npc;   /* next PC: integer or DYNAMIC_PC or JUMP_PC */

    target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */

    int is_br;

    int mem_idx;

    int fpu_enabled;

    struct TranslationBlock *tb;

} DisasContext;

struct sparc_def_t {

    const unsigned char *name;

    target_ulong iu_version;

    uint32_t fpu_version;

    uint32_t mmu_version;

    uint32_t mmu_bm;

};

static uint16_t *gen_opc_ptr;

static uint32_t *gen_opparam_ptr;

extern FILE *logfile;

extern int loglevel;

enum {

#define DEF(s,n,copy_size) INDEX_op_ ## s,

#include "opc.h"

#undef DEF

    NB_OPS

};

#include "gen-op.h"

// This function uses non-native bit order

#define GET_FIELD(X, FROM, TO) \

  ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))

// This function uses the order in the manuals, i.e. bit 0 is 2^0

#define GET_FIELD_SP(X, FROM, TO) \

    GET_FIELD(X, 31 - (TO), 31 - (FROM))

#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)

#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))

#ifdef TARGET_SPARC64

#define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))

#else

#define DFPREG(r) (r & 0x1e)

#endif

#ifdef USE_DIRECT_JUMP

#define TBPARAM(x)

#else

#define TBPARAM(x) (long)(x)

#endif

static int sign_extend(int x, int len)

{

    len = 32 - len;

    return (x << len) >> len;

}

#define IS_IMM (insn & (1<<13))

static void disas_sparc_insn(DisasContext * dc);

static GenOpFunc * const gen_op_movl_TN_reg[2][32] = {

    {

     gen_op_movl_g0_T0,

     gen_op_movl_g1_T0,

     gen_op_movl_g2_T0,

     gen_op_movl_g3_T0,

     gen_op_movl_g4_T0,

     gen_op_movl_g5_T0,

     gen_op_movl_g6_T0,

     gen_op_movl_g7_T0,

     gen_op_movl_o0_T0,

     gen_op_movl_o1_T0,

     gen_op_movl_o2_T0,

     gen_op_movl_o3_T0,

     gen_op_movl_o4_T0,

     gen_op_movl_o5_T0,

     gen_op_movl_o6_T0,

     gen_op_movl_o7_T0,

     gen_op_movl_l0_T0,

     gen_op_movl_l1_T0,

     gen_op_movl_l2_T0,

     gen_op_movl_l3_T0,

     gen_op_movl_l4_T0,

     gen_op_movl_l5_T0,

     gen_op_movl_l6_T0,

     gen_op_movl_l7_T0,

     gen_op_movl_i0_T0,

     gen_op_movl_i1_T0,

     gen_op_movl_i2_T0,

     gen_op_movl_i3_T0,

     gen_op_movl_i4_T0,

     gen_op_movl_i5_T0,

     gen_op_movl_i6_T0,

     gen_op_movl_i7_T0,

     },

    {

     gen_op_movl_g0_T1,

     gen_op_movl_g1_T1,

     gen_op_movl_g2_T1,

     gen_op_movl_g3_T1,

     gen_op_movl_g4_T1,

     gen_op_movl_g5_T1,

     gen_op_movl_g6_T1,

     gen_op_movl_g7_T1,

     gen_op_movl_o0_T1,

     gen_op_movl_o1_T1,

     gen_op_movl_o2_T1,

     gen_op_movl_o3_T1,

     gen_op_movl_o4_T1,

     gen_op_movl_o5_T1,

     gen_op_movl_o6_T1,

     gen_op_movl_o7_T1,

     gen_op_movl_l0_T1,

     gen_op_movl_l1_T1,

     gen_op_movl_l2_T1,

     gen_op_movl_l3_T1,

     gen_op_movl_l4_T1,

     gen_op_movl_l5_T1,

     gen_op_movl_l6_T1,

     gen_op_movl_l7_T1,

     gen_op_movl_i0_T1,

     gen_op_movl_i1_T1,

     gen_op_movl_i2_T1,

     gen_op_movl_i3_T1,

     gen_op_movl_i4_T1,

     gen_op_movl_i5_T1,

     gen_op_movl_i6_T1,

     gen_op_movl_i7_T1,

     }

};

static GenOpFunc * const gen_op_movl_reg_TN[3][32] = {

    {

     gen_op_movl_T0_g0,

     gen_op_movl_T0_g1,

     gen_op_movl_T0_g2,

     gen_op_movl_T0_g3,

     gen_op_movl_T0_g4,

     gen_op_movl_T0_g5,

     gen_op_movl_T0_g6,

     gen_op_movl_T0_g7,

     gen_op_movl_T0_o0,

     gen_op_movl_T0_o1,

     gen_op_movl_T0_o2,

     gen_op_movl_T0_o3,

     gen_op_movl_T0_o4,

     gen_op_movl_T0_o5,

     gen_op_movl_T0_o6,

     gen_op_movl_T0_o7,

     gen_op_movl_T0_l0,

     gen_op_movl_T0_l1,

     gen_op_movl_T0_l2,

     gen_op_movl_T0_l3,

     gen_op_movl_T0_l4,

     gen_op_movl_T0_l5,

     gen_op_movl_T0_l6,

     gen_op_movl_T0_l7,

     gen_op_movl_T0_i0,

     gen_op_movl_T0_i1,

     gen_op_movl_T0_i2,

     gen_op_movl_T0_i3,

     gen_op_movl_T0_i4,

     gen_op_movl_T0_i5,

     gen_op_movl_T0_i6,

     gen_op_movl_T0_i7,

     },

    {

     gen_op_movl_T1_g0,

     gen_op_movl_T1_g1,

     gen_op_movl_T1_g2,

     gen_op_movl_T1_g3,

     gen_op_movl_T1_g4,

     gen_op_movl_T1_g5,

     gen_op_movl_T1_g6,

     gen_op_movl_T1_g7,

     gen_op_movl_T1_o0,

     gen_op_movl_T1_o1,

     gen_op_movl_T1_o2,

     gen_op_movl_T1_o3,

     gen_op_movl_T1_o4,

     gen_op_movl_T1_o5,

     gen_op_movl_T1_o6,

     gen_op_movl_T1_o7,

     gen_op_movl_T1_l0,

     gen_op_movl_T1_l1,

     gen_op_movl_T1_l2,

     gen_op_movl_T1_l3,

     gen_op_movl_T1_l4,

     gen_op_movl_T1_l5,

     gen_op_movl_T1_l6,

     gen_op_movl_T1_l7,

     gen_op_movl_T1_i0,

     gen_op_movl_T1_i1,

     gen_op_movl_T1_i2,

     gen_op_movl_T1_i3,

     gen_op_movl_T1_i4,

     gen_op_movl_T1_i5,

     gen_op_movl_T1_i6,

     gen_op_movl_T1_i7,

     },

    {

     gen_op_movl_T2_g0,

     gen_op_movl_T2_g1,

     gen_op_movl_T2_g2,

     gen_op_movl_T2_g3,

     gen_op_movl_T2_g4,

     gen_op_movl_T2_g5,

     gen_op_movl_T2_g6,

     gen_op_movl_T2_g7,

     gen_op_movl_T2_o0,

     gen_op_movl_T2_o1,

     gen_op_movl_T2_o2,

     gen_op_movl_T2_o3,

     gen_op_movl_T2_o4,

     gen_op_movl_T2_o5,

     gen_op_movl_T2_o6,

     gen_op_movl_T2_o7,

     gen_op_movl_T2_l0,

     gen_op_movl_T2_l1,

     gen_op_movl_T2_l2,

     gen_op_movl_T2_l3,

     gen_op_movl_T2_l4,

     gen_op_movl_T2_l5,

     gen_op_movl_T2_l6,

     gen_op_movl_T2_l7,

     gen_op_movl_T2_i0,

     gen_op_movl_T2_i1,

     gen_op_movl_T2_i2,

     gen_op_movl_T2_i3,

     gen_op_movl_T2_i4,

     gen_op_movl_T2_i5,

     gen_op_movl_T2_i6,

     gen_op_movl_T2_i7,

     }

};

static GenOpFunc1 * const gen_op_movl_TN_im[3] = {

    gen_op_movl_T0_im,

    gen_op_movl_T1_im,

    gen_op_movl_T2_im

};

// Sign extending version

static GenOpFunc1 * const gen_op_movl_TN_sim[3] = {

    gen_op_movl_T0_sim,

    gen_op_movl_T1_sim,

    gen_op_movl_T2_sim

};

#ifdef TARGET_SPARC64

#define GEN32(func, NAME) \

static GenOpFunc * const NAME ## _table [64] = {                              \

NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \

NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \

NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11,                                 \

NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15,                               \

NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19,                               \

NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23,                               \

NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27,                               \

NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31,                               \

NAME ## 32, 0, NAME ## 34, 0, NAME ## 36, 0, NAME ## 38, 0,                   \

NAME ## 40, 0, NAME ## 42, 0, NAME ## 44, 0, NAME ## 46, 0,                   \

NAME ## 48, 0, NAME ## 50, 0, NAME ## 52, 0, NAME ## 54, 0,                   \

NAME ## 56, 0, NAME ## 58, 0, NAME ## 60, 0, NAME ## 62, 0,                   \

};                                                                            \

static inline void func(int n)                                                \

{                                                                             \

    NAME ## _table[n]();                                                      \

}

#else

#define GEN32(func, NAME) \

static GenOpFunc *const NAME ## _table [32] = {                               \

NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \

NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \

NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11,                                 \

NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15,                               \

NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19,                               \

NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23,                               \

NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27,                               \

NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31,                               \

};                                                                            \

static inline void func(int n)                                                \

{                                                                             \

    NAME ## _table[n]();                                                      \

}

#endif

/* floating point registers moves */

GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fprf);

GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fprf);

GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fprf);

GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fprf);

GEN32(gen_op_load_fpr_DT0, gen_op_load_fpr_DT0_fprf);

GEN32(gen_op_load_fpr_DT1, gen_op_load_fpr_DT1_fprf);

GEN32(gen_op_store_DT0_fpr, gen_op_store_DT0_fpr_fprf);

GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf);

/* moves */

#ifdef CONFIG_USER_ONLY

#define supervisor(dc) 0

#ifdef TARGET_SPARC64

#define hypervisor(dc) 0

#endif

#define gen_op_ldst(name)        gen_op_##name##_raw()

#else

#define supervisor(dc) (dc->mem_idx >= 1)

#ifdef TARGET_SPARC64

#define hypervisor(dc) (dc->mem_idx == 2)

#define OP_LD_TABLE(width)                                              \

    static GenOpFunc * const gen_op_##width[] = {                       \

        &gen_op_##width##_user,                                         \

        &gen_op_##width##_kernel,                                       \

        &gen_op_##width##_hypv,                                         \

    };

#else

#define OP_LD_TABLE(width)                                              \

    static GenOpFunc * const gen_op_##width[] = {                       \

        &gen_op_##width##_user,                                         \

        &gen_op_##width##_kernel,                                       \

    };

#endif

#define gen_op_ldst(name)        (*gen_op_##name[dc->mem_idx])()

#endif

#ifndef CONFIG_USER_ONLY

OP_LD_TABLE(ld);

OP_LD_TABLE(st);

OP_LD_TABLE(ldub);

OP_LD_TABLE(lduh);

OP_LD_TABLE(ldsb);

OP_LD_TABLE(ldsh);

OP_LD_TABLE(stb);

OP_LD_TABLE(sth);

OP_LD_TABLE(std);

OP_LD_TABLE(ldstub);

OP_LD_TABLE(swap);

OP_LD_TABLE(ldd);

OP_LD_TABLE(stf);

OP_LD_TABLE(stdf);

OP_LD_TABLE(ldf);

OP_LD_TABLE(lddf);

#ifdef TARGET_SPARC64

OP_LD_TABLE(lduw);

OP_LD_TABLE(ldsw);

OP_LD_TABLE(ldx);

OP_LD_TABLE(stx);

#endif

#endif

/* asi moves */

#ifdef TARGET_SPARC64

static inline void gen_ld_asi(int insn, int size, int sign)

{

    int asi, offset;

    if (IS_IMM) {

        offset = GET_FIELD(insn, 25, 31);

        gen_op_ld_asi_reg(offset, size, sign);

    } else {

        asi = GET_FIELD(insn, 19, 26);

        gen_op_ld_asi(asi, size, sign);

    }

}

static inline void gen_st_asi(int insn, int size)

{

    int asi, offset;

    if (IS_IMM) {

        offset = GET_FIELD(insn, 25, 31);

        gen_op_st_asi_reg(offset, size);

    } else {

        asi = GET_FIELD(insn, 19, 26);

        gen_op_st_asi(asi, size);

    }

}

static inline void gen_ldf_asi(int insn, int size)

{

    int asi, offset, rd;

    rd = DFPREG(GET_FIELD(insn, 2, 6));

    if (IS_IMM) {

        offset = GET_FIELD(insn, 25, 31);

        gen_op_ldf_asi_reg(offset, size, rd);

    } else {

        asi = GET_FIELD(insn, 19, 26);

        gen_op_ldf_asi(asi, size, rd);

    }

}

static inline void gen_stf_asi(int insn, int size)

{

    int asi, offset, rd;

    rd = DFPREG(GET_FIELD(insn, 2, 6));

    if (IS_IMM) {

        offset = GET_FIELD(insn, 25, 31);

        gen_op_stf_asi_reg(offset, size, rd);

    } else {

        asi = GET_FIELD(insn, 19, 26);

        gen_op_stf_asi(asi, size, rd);

    }

}

static inline void gen_swap_asi(int insn)

{

    int asi, offset;

    if (IS_IMM) {

        offset = GET_FIELD(insn, 25, 31);

        gen_op_swap_asi_reg(offset);

    } else {

        asi = GET_FIELD(insn, 19, 26);

        gen_op_swap_asi(asi);

    }

}

static inline void gen_ldstub_asi(int insn)

{

    int asi, offset;

    if (IS_IMM) {

        offset = GET_FIELD(insn, 25, 31);

        gen_op_ldstub_asi_reg(offset);

    } else {

        asi = GET_FIELD(insn, 19, 26);

        gen_op_ldstub_asi(asi);

    }

}

static inline void gen_ldda_asi(int insn)

{

    int asi, offset;

    if (IS_IMM) {

        offset = GET_FIELD(insn, 25, 31);

        gen_op_ldda_asi_reg(offset);

    } else {

        asi = GET_FIELD(insn, 19, 26);

        gen_op_ldda_asi(asi);

    }

}

static inline void gen_stda_asi(int insn)

{

    int asi, offset;

    if (IS_IMM) {

        offset = GET_FIELD(insn, 25, 31);

        gen_op_stda_asi_reg(offset);

    } else {

        asi = GET_FIELD(insn, 19, 26);

        gen_op_stda_asi(asi);

    }

}

static inline void gen_cas_asi(int insn)

{

    int asi, offset;

    if (IS_IMM) {

        offset = GET_FIELD(insn, 25, 31);

        gen_op_cas_asi_reg(offset);

    } else {

        asi = GET_FIELD(insn, 19, 26);

        gen_op_cas_asi(asi);

    }

}

static inline void gen_casx_asi(int insn)

{

    int asi, offset;

    if (IS_IMM) {

        offset = GET_FIELD(insn, 25, 31);

        gen_op_casx_asi_reg(offset);

    } else {

        asi = GET_FIELD(insn, 19, 26);

        gen_op_casx_asi(asi);

    }

}

#elif !defined(CONFIG_USER_ONLY)

static inline void gen_ld_asi(int insn, int size, int sign)

{

    int asi;

    asi = GET_FIELD(insn, 19, 26);

    gen_op_ld_asi(asi, size, sign);

}

static inline void gen_st_asi(int insn, int size)

{

    int asi;

    asi = GET_FIELD(insn, 19, 26);

    gen_op_st_asi(asi, size);

}

static inline void gen_ldstub_asi(int insn)

{

    int asi;

    asi = GET_FIELD(insn, 19, 26);

    gen_op_ldstub_asi(asi);

}

static inline void gen_swap_asi(int insn)

{

    int asi;

    asi = GET_FIELD(insn, 19, 26);

    gen_op_swap_asi(asi);

}

static inline void gen_ldda_asi(int insn)

{

    int asi;

    asi = GET_FIELD(insn, 19, 26);

    gen_op_ld_asi(asi, 8, 0);

}

static inline void gen_stda_asi(int insn)

{

    int asi;

    asi = GET_FIELD(insn, 19, 26);

    gen_op_st_asi(asi, 8);

}

#endif

static inline void gen_movl_imm_TN(int reg, uint32_t imm)

{

    gen_op_movl_TN_im[reg](imm);

}

static inline void gen_movl_imm_T1(uint32_t val)

{

    gen_movl_imm_TN(1, val);

}

static inline void gen_movl_imm_T0(uint32_t val)

{

    gen_movl_imm_TN(0, val);

}

static inline void gen_movl_simm_TN(int reg, int32_t imm)

{

    gen_op_movl_TN_sim[reg](imm);

}

static inline void gen_movl_simm_T1(int32_t val)

{

    gen_movl_simm_TN(1, val);

}

static inline void gen_movl_simm_T0(int32_t val)

{

    gen_movl_simm_TN(0, val);

}

static inline void gen_movl_reg_TN(int reg, int t)

{

    if (reg)

        gen_op_movl_reg_TN[t][reg] ();

    else

        gen_movl_imm_TN(t, 0);

}

static inline void gen_movl_reg_T0(int reg)

{

    gen_movl_reg_TN(reg, 0);

}

static inline void gen_movl_reg_T1(int reg)

{

    gen_movl_reg_TN(reg, 1);

}

static inline void gen_movl_reg_T2(int reg)

{

    gen_movl_reg_TN(reg, 2);

}

static inline void gen_movl_TN_reg(int reg, int t)

{

    if (reg)

        gen_op_movl_TN_reg[t][reg] ();

}

static inline void gen_movl_T0_reg(int reg)

{

    gen_movl_TN_reg(reg, 0);

}

static inline void gen_movl_T1_reg(int reg)

{

    gen_movl_TN_reg(reg, 1);

}

static inline void gen_jmp_im(target_ulong pc)

{

#ifdef TARGET_SPARC64

    if (pc == (uint32_t)pc) {

        gen_op_jmp_im(pc);

    } else {

        gen_op_jmp_im64(pc >> 32, pc);

    }

#else

    gen_op_jmp_im(pc);

#endif

}

static inline void gen_movl_npc_im(target_ulong npc)

{

#ifdef TARGET_SPARC64

    if (npc == (uint32_t)npc) {

        gen_op_movl_npc_im(npc);

    } else {

        gen_op_movq_npc_im64(npc >> 32, npc);

    }

#else

    gen_op_movl_npc_im(npc);

#endif

}

static inline void gen_goto_tb(DisasContext *s, int tb_num,

                               target_ulong pc, target_ulong npc)

{

    TranslationBlock *tb;

    tb = s->tb;

    if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&

        (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK))  {

        /* jump to same page: we can use a direct jump */

        if (tb_num == 0)

            gen_op_goto_tb0(TBPARAM(tb));

        else

            gen_op_goto_tb1(TBPARAM(tb));

        gen_jmp_im(pc);

        gen_movl_npc_im(npc);

        gen_op_movl_T0_im((long)tb + tb_num);

        gen_op_exit_tb();

    } else {

        /* jump to another page: currently not optimized */

        gen_jmp_im(pc);

        gen_movl_npc_im(npc);

        gen_op_movl_T0_0();

        gen_op_exit_tb();

    }

}

static inline void gen_branch2(DisasContext *dc, target_ulong pc1,

                               target_ulong pc2)

{

    int l1;

    l1 = gen_new_label();

    gen_op_jz_T2_label(l1);

    gen_goto_tb(dc, 0, pc1, pc1 + 4);

    gen_set_label(l1);

    gen_goto_tb(dc, 1, pc2, pc2 + 4);

}

static inline void gen_branch_a(DisasContext *dc, target_ulong pc1,

                                target_ulong pc2)

{

    int l1;

    l1 = gen_new_label();

    gen_op_jz_T2_label(l1);

    gen_goto_tb(dc, 0, pc2, pc1);

    gen_set_label(l1);

    gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);

}

static inline void gen_branch(DisasContext *dc, target_ulong pc,

                              target_ulong npc)

{

    gen_goto_tb(dc, 0, pc, npc);

}

static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2)

{

    int l1, l2;

    l1 = gen_new_label();

    l2 = gen_new_label();

    gen_op_jz_T2_label(l1);

    gen_movl_npc_im(npc1);

    gen_op_jmp_label(l2);

    gen_set_label(l1);

    gen_movl_npc_im(npc2);

    gen_set_label(l2);

}

/* call this function before using T2 as it may have been set for a jump */

static inline void flush_T2(DisasContext * dc)

{

    if (dc->npc == JUMP_PC) {

        gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);

        dc->npc = DYNAMIC_PC;

    }

}

static inline void save_npc(DisasContext * dc)

{

    if (dc->npc == JUMP_PC) {

        gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);

        dc->npc = DYNAMIC_PC;

    } else if (dc->npc != DYNAMIC_PC) {

        gen_movl_npc_im(dc->npc);

    }

}

static inline void save_state(DisasContext * dc)

{

    gen_jmp_im(dc->pc);

    save_npc(dc);

}

static inline void gen_mov_pc_npc(DisasContext * dc)

{

    if (dc->npc == JUMP_PC) {

        gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);

        gen_op_mov_pc_npc();

        dc->pc = DYNAMIC_PC;

    } else if (dc->npc == DYNAMIC_PC) {

        gen_op_mov_pc_npc();

        dc->pc = DYNAMIC_PC;

    } else {

        dc->pc = dc->npc;

    }

}

static GenOpFunc * const gen_cond[2][16] = {

    {

        gen_op_eval_bn,

        gen_op_eval_be,

        gen_op_eval_ble,

        gen_op_eval_bl,

        gen_op_eval_bleu,

        gen_op_eval_bcs,

        gen_op_eval_bneg,

        gen_op_eval_bvs,

        gen_op_eval_ba,

        gen_op_eval_bne,

        gen_op_eval_bg,

        gen_op_eval_bge,

        gen_op_eval_bgu,

        gen_op_eval_bcc,

        gen_op_eval_bpos,

        gen_op_eval_bvc,

    },

    {

#ifdef TARGET_SPARC64

        gen_op_eval_bn,

        gen_op_eval_xbe,

        gen_op_eval_xble,

        gen_op_eval_xbl,

        gen_op_eval_xbleu,

        gen_op_eval_xbcs,

        gen_op_eval_xbneg,

        gen_op_eval_xbvs,

        gen_op_eval_ba,

        gen_op_eval_xbne,

        gen_op_eval_xbg,

        gen_op_eval_xbge,

        gen_op_eval_xbgu,

        gen_op_eval_xbcc,

        gen_op_eval_xbpos,

        gen_op_eval_xbvc,

#endif

    },

};

static GenOpFunc * const gen_fcond[4][16] = {

    {

        gen_op_eval_bn,

        gen_op_eval_fbne,

        gen_op_eval_fblg,

        gen_op_eval_fbul,

        gen_op_eval_fbl,

        gen_op_eval_fbug,

        gen_op_eval_fbg,

        gen_op_eval_fbu,

        gen_op_eval_ba,

        gen_op_eval_fbe,

        gen_op_eval_fbue,

        gen_op_eval_fbge,

        gen_op_eval_fbuge,

        gen_op_eval_fble,

        gen_op_eval_fbule,

        gen_op_eval_fbo,

    },

#ifdef TARGET_SPARC64

    {

        gen_op_eval_bn,

        gen_op_eval_fbne_fcc1,

        gen_op_eval_fblg_fcc1,

        gen_op_eval_fbul_fcc1,

        gen_op_eval_fbl_fcc1,

        gen_op_eval_fbug_fcc1,

        gen_op_eval_fbg_fcc1,

        gen_op_eval_fbu_fcc1,

        gen_op_eval_ba,

        gen_op_eval_fbe_fcc1,

        gen_op_eval_fbue_fcc1,

        gen_op_eval_fbge_fcc1,

        gen_op_eval_fbuge_fcc1,

        gen_op_eval_fble_fcc1,

        gen_op_eval_fbule_fcc1,

        gen_op_eval_fbo_fcc1,

    },

    {

        gen_op_eval_bn,

        gen_op_eval_fbne_fcc2,

        gen_op_eval_fblg_fcc2,

        gen_op_eval_fbul_fcc2,

        gen_op_eval_fbl_fcc2,

        gen_op_eval_fbug_fcc2,

        gen_op_eval_fbg_fcc2,

        gen_op_eval_fbu_fcc2,

        gen_op_eval_ba,

        gen_op_eval_fbe_fcc2,

        gen_op_eval_fbue_fcc2,

        gen_op_eval_fbge_fcc2,

        gen_op_eval_fbuge_fcc2,

        gen_op_eval_fble_fcc2,

        gen_op_eval_fbule_fcc2,

        gen_op_eval_fbo_fcc2,

    },

    {

        gen_op_eval_bn,

        gen_op_eval_fbne_fcc3,

        gen_op_eval_fblg_fcc3,