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1
/*
2
   SPARC translation
3

4
   Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
5
   Copyright (C) 2003-2005 Fabrice Bellard
6

7
   This library is free software; you can redistribute it and/or
8
   modify it under the terms of the GNU Lesser General Public
9
   License as published by the Free Software Foundation; either
10
   version 2 of the License, or (at your option) any later version.
11

12
   This library is distributed in the hope that it will be useful,
13
   but WITHOUT ANY WARRANTY; without even the implied warranty of
14
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15
   Lesser General Public License for more details.
16

17
   You should have received a copy of the GNU Lesser General Public
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   License along with this library; if not, write to the Free Software
19
   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
20
 */
21

    
22
/*
23
   TODO-list:
24

25
   Rest of V9 instructions, VIS instructions
26
   NPC/PC static optimisations (use JUMP_TB when possible)
27
   Optimize synthetic instructions
28
   128-bit float
29
*/
30

    
31
#include <stdarg.h>
32
#include <stdlib.h>
33
#include <stdio.h>
34
#include <string.h>
35
#include <inttypes.h>
36

    
37
#include "cpu.h"
38
#include "exec-all.h"
39
#include "disas.h"
40

    
41
#define DEBUG_DISAS
42

    
43
#define DYNAMIC_PC  1 /* dynamic pc value */
44
#define JUMP_PC     2 /* dynamic pc value which takes only two values
45
                         according to jump_pc[T2] */
46

    
47
typedef struct DisasContext {
48
    target_ulong pc;    /* current Program Counter: integer or DYNAMIC_PC */
49
    target_ulong npc;   /* next PC: integer or DYNAMIC_PC or JUMP_PC */
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    target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
51
    int is_br;
52
    int mem_idx;
53
    int fpu_enabled;
54
    struct TranslationBlock *tb;
55
} DisasContext;
56

    
57
struct sparc_def_t {
58
    const unsigned char *name;
59
    target_ulong iu_version;
60
    uint32_t fpu_version;
61
    uint32_t mmu_version;
62
    uint32_t mmu_bm;
63
};
64

    
65
static uint16_t *gen_opc_ptr;
66
static uint32_t *gen_opparam_ptr;
67
extern FILE *logfile;
68
extern int loglevel;
69

    
70
enum {
71
#define DEF(s,n,copy_size) INDEX_op_ ## s,
72
#include "opc.h"
73
#undef DEF
74
    NB_OPS
75
};
76

    
77
#include "gen-op.h"
78

    
79
// This function uses non-native bit order
80
#define GET_FIELD(X, FROM, TO) \
81
  ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
82

    
83
// This function uses the order in the manuals, i.e. bit 0 is 2^0
84
#define GET_FIELD_SP(X, FROM, TO) \
85
    GET_FIELD(X, 31 - (TO), 31 - (FROM))
86

    
87
#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
88
#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
89

    
90
#ifdef TARGET_SPARC64
91
#define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
92
#else
93
#define DFPREG(r) (r & 0x1e)
94
#endif
95

    
96
#ifdef USE_DIRECT_JUMP
97
#define TBPARAM(x)
98
#else
99
#define TBPARAM(x) (long)(x)
100
#endif
101

    
102
static int sign_extend(int x, int len)
103
{
104
    len = 32 - len;
105
    return (x << len) >> len;
106
}
107

    
108
#define IS_IMM (insn & (1<<13))
109

    
110
static void disas_sparc_insn(DisasContext * dc);
111

    
112
static GenOpFunc * const gen_op_movl_TN_reg[2][32] = {
113
    {
114
     gen_op_movl_g0_T0,
115
     gen_op_movl_g1_T0,
116
     gen_op_movl_g2_T0,
117
     gen_op_movl_g3_T0,
118
     gen_op_movl_g4_T0,
119
     gen_op_movl_g5_T0,
120
     gen_op_movl_g6_T0,
121
     gen_op_movl_g7_T0,
122
     gen_op_movl_o0_T0,
123
     gen_op_movl_o1_T0,
124
     gen_op_movl_o2_T0,
125
     gen_op_movl_o3_T0,
126
     gen_op_movl_o4_T0,
127
     gen_op_movl_o5_T0,
128
     gen_op_movl_o6_T0,
129
     gen_op_movl_o7_T0,
130
     gen_op_movl_l0_T0,
131
     gen_op_movl_l1_T0,
132
     gen_op_movl_l2_T0,
133
     gen_op_movl_l3_T0,
134
     gen_op_movl_l4_T0,
135
     gen_op_movl_l5_T0,
136
     gen_op_movl_l6_T0,
137
     gen_op_movl_l7_T0,
138
     gen_op_movl_i0_T0,
139
     gen_op_movl_i1_T0,
140
     gen_op_movl_i2_T0,
141
     gen_op_movl_i3_T0,
142
     gen_op_movl_i4_T0,
143
     gen_op_movl_i5_T0,
144
     gen_op_movl_i6_T0,
145
     gen_op_movl_i7_T0,
146
     },
147
    {
148
     gen_op_movl_g0_T1,
149
     gen_op_movl_g1_T1,
150
     gen_op_movl_g2_T1,
151
     gen_op_movl_g3_T1,
152
     gen_op_movl_g4_T1,
153
     gen_op_movl_g5_T1,
154
     gen_op_movl_g6_T1,
155
     gen_op_movl_g7_T1,
156
     gen_op_movl_o0_T1,
157
     gen_op_movl_o1_T1,
158
     gen_op_movl_o2_T1,
159
     gen_op_movl_o3_T1,
160
     gen_op_movl_o4_T1,
161
     gen_op_movl_o5_T1,
162
     gen_op_movl_o6_T1,
163
     gen_op_movl_o7_T1,
164
     gen_op_movl_l0_T1,
165
     gen_op_movl_l1_T1,
166
     gen_op_movl_l2_T1,
167
     gen_op_movl_l3_T1,
168
     gen_op_movl_l4_T1,
169
     gen_op_movl_l5_T1,
170
     gen_op_movl_l6_T1,
171
     gen_op_movl_l7_T1,
172
     gen_op_movl_i0_T1,
173
     gen_op_movl_i1_T1,
174
     gen_op_movl_i2_T1,
175
     gen_op_movl_i3_T1,
176
     gen_op_movl_i4_T1,
177
     gen_op_movl_i5_T1,
178
     gen_op_movl_i6_T1,
179
     gen_op_movl_i7_T1,
180
     }
181
};
182

    
183
static GenOpFunc * const gen_op_movl_reg_TN[3][32] = {
184
    {
185
     gen_op_movl_T0_g0,
186
     gen_op_movl_T0_g1,
187
     gen_op_movl_T0_g2,
188
     gen_op_movl_T0_g3,
189
     gen_op_movl_T0_g4,
190
     gen_op_movl_T0_g5,
191
     gen_op_movl_T0_g6,
192
     gen_op_movl_T0_g7,
193
     gen_op_movl_T0_o0,
194
     gen_op_movl_T0_o1,
195
     gen_op_movl_T0_o2,
196
     gen_op_movl_T0_o3,
197
     gen_op_movl_T0_o4,
198
     gen_op_movl_T0_o5,
199
     gen_op_movl_T0_o6,
200
     gen_op_movl_T0_o7,
201
     gen_op_movl_T0_l0,
202
     gen_op_movl_T0_l1,
203
     gen_op_movl_T0_l2,
204
     gen_op_movl_T0_l3,
205
     gen_op_movl_T0_l4,
206
     gen_op_movl_T0_l5,
207
     gen_op_movl_T0_l6,
208
     gen_op_movl_T0_l7,
209
     gen_op_movl_T0_i0,
210
     gen_op_movl_T0_i1,
211
     gen_op_movl_T0_i2,
212
     gen_op_movl_T0_i3,
213
     gen_op_movl_T0_i4,
214
     gen_op_movl_T0_i5,
215
     gen_op_movl_T0_i6,
216
     gen_op_movl_T0_i7,
217
     },
218
    {
219
     gen_op_movl_T1_g0,
220
     gen_op_movl_T1_g1,
221
     gen_op_movl_T1_g2,
222
     gen_op_movl_T1_g3,
223
     gen_op_movl_T1_g4,
224
     gen_op_movl_T1_g5,
225
     gen_op_movl_T1_g6,
226
     gen_op_movl_T1_g7,
227
     gen_op_movl_T1_o0,
228
     gen_op_movl_T1_o1,
229
     gen_op_movl_T1_o2,
230
     gen_op_movl_T1_o3,
231
     gen_op_movl_T1_o4,
232
     gen_op_movl_T1_o5,
233
     gen_op_movl_T1_o6,
234
     gen_op_movl_T1_o7,
235
     gen_op_movl_T1_l0,
236
     gen_op_movl_T1_l1,
237
     gen_op_movl_T1_l2,
238
     gen_op_movl_T1_l3,
239
     gen_op_movl_T1_l4,
240
     gen_op_movl_T1_l5,
241
     gen_op_movl_T1_l6,
242
     gen_op_movl_T1_l7,
243
     gen_op_movl_T1_i0,
244
     gen_op_movl_T1_i1,
245
     gen_op_movl_T1_i2,
246
     gen_op_movl_T1_i3,
247
     gen_op_movl_T1_i4,
248
     gen_op_movl_T1_i5,
249
     gen_op_movl_T1_i6,
250
     gen_op_movl_T1_i7,
251
     },
252
    {
253
     gen_op_movl_T2_g0,
254
     gen_op_movl_T2_g1,
255
     gen_op_movl_T2_g2,
256
     gen_op_movl_T2_g3,
257
     gen_op_movl_T2_g4,
258
     gen_op_movl_T2_g5,
259
     gen_op_movl_T2_g6,
260
     gen_op_movl_T2_g7,
261
     gen_op_movl_T2_o0,
262
     gen_op_movl_T2_o1,
263
     gen_op_movl_T2_o2,
264
     gen_op_movl_T2_o3,
265
     gen_op_movl_T2_o4,
266
     gen_op_movl_T2_o5,
267
     gen_op_movl_T2_o6,
268
     gen_op_movl_T2_o7,
269
     gen_op_movl_T2_l0,
270
     gen_op_movl_T2_l1,
271
     gen_op_movl_T2_l2,
272
     gen_op_movl_T2_l3,
273
     gen_op_movl_T2_l4,
274
     gen_op_movl_T2_l5,
275
     gen_op_movl_T2_l6,
276
     gen_op_movl_T2_l7,
277
     gen_op_movl_T2_i0,
278
     gen_op_movl_T2_i1,
279
     gen_op_movl_T2_i2,
280
     gen_op_movl_T2_i3,
281
     gen_op_movl_T2_i4,
282
     gen_op_movl_T2_i5,
283
     gen_op_movl_T2_i6,
284
     gen_op_movl_T2_i7,
285
     }
286
};
287

    
288
static GenOpFunc1 * const gen_op_movl_TN_im[3] = {
289
    gen_op_movl_T0_im,
290
    gen_op_movl_T1_im,
291
    gen_op_movl_T2_im
292
};
293

    
294
// Sign extending version
295
static GenOpFunc1 * const gen_op_movl_TN_sim[3] = {
296
    gen_op_movl_T0_sim,
297
    gen_op_movl_T1_sim,
298
    gen_op_movl_T2_sim
299
};
300

    
301
#ifdef TARGET_SPARC64
302
#define GEN32(func, NAME) \
303
static GenOpFunc * const NAME ## _table [64] = {                              \
304
NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \
305
NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \
306
NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11,                                 \
307
NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15,                               \
308
NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19,                               \
309
NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23,                               \
310
NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27,                               \
311
NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31,                               \
312
NAME ## 32, 0, NAME ## 34, 0, NAME ## 36, 0, NAME ## 38, 0,                   \
313
NAME ## 40, 0, NAME ## 42, 0, NAME ## 44, 0, NAME ## 46, 0,                   \
314
NAME ## 48, 0, NAME ## 50, 0, NAME ## 52, 0, NAME ## 54, 0,                   \
315
NAME ## 56, 0, NAME ## 58, 0, NAME ## 60, 0, NAME ## 62, 0,                   \
316
};                                                                            \
317
static inline void func(int n)                                                \
318
{                                                                             \
319
    NAME ## _table[n]();                                                      \
320
}
321
#else
322
#define GEN32(func, NAME) \
323
static GenOpFunc *const NAME ## _table [32] = {                               \
324
NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \
325
NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \
326
NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11,                                 \
327
NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15,                               \
328
NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19,                               \
329
NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23,                               \
330
NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27,                               \
331
NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31,                               \
332
};                                                                            \
333
static inline void func(int n)                                                \
334
{                                                                             \
335
    NAME ## _table[n]();                                                      \
336
}
337
#endif
338

    
339
/* floating point registers moves */
340
GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fprf);
341
GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fprf);
342
GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fprf);
343
GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fprf);
344

    
345
GEN32(gen_op_load_fpr_DT0, gen_op_load_fpr_DT0_fprf);
346
GEN32(gen_op_load_fpr_DT1, gen_op_load_fpr_DT1_fprf);
347
GEN32(gen_op_store_DT0_fpr, gen_op_store_DT0_fpr_fprf);
348
GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf);
349

    
350
/* moves */
351
#ifdef CONFIG_USER_ONLY
352
#define supervisor(dc) 0
353
#ifdef TARGET_SPARC64
354
#define hypervisor(dc) 0
355
#endif
356
#define gen_op_ldst(name)        gen_op_##name##_raw()
357
#else
358
#define supervisor(dc) (dc->mem_idx >= 1)
359
#ifdef TARGET_SPARC64
360
#define hypervisor(dc) (dc->mem_idx == 2)
361
#define OP_LD_TABLE(width)                                              \
362
    static GenOpFunc * const gen_op_##width[] = {                       \
363
        &gen_op_##width##_user,                                         \
364
        &gen_op_##width##_kernel,                                       \
365
        &gen_op_##width##_hypv,                                         \
366
    };
367
#else
368
#define OP_LD_TABLE(width)                                              \
369
    static GenOpFunc * const gen_op_##width[] = {                       \
370
        &gen_op_##width##_user,                                         \
371
        &gen_op_##width##_kernel,                                       \
372
    };
373
#endif
374
#define gen_op_ldst(name)        (*gen_op_##name[dc->mem_idx])()
375
#endif
376

    
377
#ifndef CONFIG_USER_ONLY
378
OP_LD_TABLE(ld);
379
OP_LD_TABLE(st);
380
OP_LD_TABLE(ldub);
381
OP_LD_TABLE(lduh);
382
OP_LD_TABLE(ldsb);
383
OP_LD_TABLE(ldsh);
384
OP_LD_TABLE(stb);
385
OP_LD_TABLE(sth);
386
OP_LD_TABLE(std);
387
OP_LD_TABLE(ldstub);
388
OP_LD_TABLE(swap);
389
OP_LD_TABLE(ldd);
390
OP_LD_TABLE(stf);
391
OP_LD_TABLE(stdf);
392
OP_LD_TABLE(ldf);
393
OP_LD_TABLE(lddf);
394

    
395
#ifdef TARGET_SPARC64
396
OP_LD_TABLE(lduw);
397
OP_LD_TABLE(ldsw);
398
OP_LD_TABLE(ldx);
399
OP_LD_TABLE(stx);
400
#endif
401
#endif
402

    
403
/* asi moves */
404
#ifdef TARGET_SPARC64
405
static inline void gen_ld_asi(int insn, int size, int sign)
406
{
407
    int asi, offset;
408

    
409
    if (IS_IMM) {
410
        offset = GET_FIELD(insn, 25, 31);
411
        gen_op_ld_asi_reg(offset, size, sign);
412
    } else {
413
        asi = GET_FIELD(insn, 19, 26);
414
        gen_op_ld_asi(asi, size, sign);
415
    }
416
}
417

    
418
static inline void gen_st_asi(int insn, int size)
419
{
420
    int asi, offset;
421

    
422
    if (IS_IMM) {
423
        offset = GET_FIELD(insn, 25, 31);
424
        gen_op_st_asi_reg(offset, size);
425
    } else {
426
        asi = GET_FIELD(insn, 19, 26);
427
        gen_op_st_asi(asi, size);
428
    }
429
}
430

    
431
static inline void gen_ldf_asi(int insn, int size)
432
{
433
    int asi, offset, rd;
434

    
435
    rd = DFPREG(GET_FIELD(insn, 2, 6));
436
    if (IS_IMM) {
437
        offset = GET_FIELD(insn, 25, 31);
438
        gen_op_ldf_asi_reg(offset, size, rd);
439
    } else {
440
        asi = GET_FIELD(insn, 19, 26);
441
        gen_op_ldf_asi(asi, size, rd);
442
    }
443
}
444

    
445
static inline void gen_stf_asi(int insn, int size)
446
{
447
    int asi, offset, rd;
448

    
449
    rd = DFPREG(GET_FIELD(insn, 2, 6));
450
    if (IS_IMM) {
451
        offset = GET_FIELD(insn, 25, 31);
452
        gen_op_stf_asi_reg(offset, size, rd);
453
    } else {
454
        asi = GET_FIELD(insn, 19, 26);
455
        gen_op_stf_asi(asi, size, rd);
456
    }
457
}
458

    
459
static inline void gen_swap_asi(int insn)
460
{
461
    int asi, offset;
462

    
463
    if (IS_IMM) {
464
        offset = GET_FIELD(insn, 25, 31);
465
        gen_op_swap_asi_reg(offset);
466
    } else {
467
        asi = GET_FIELD(insn, 19, 26);
468
        gen_op_swap_asi(asi);
469
    }
470
}
471

    
472
static inline void gen_ldstub_asi(int insn)
473
{
474
    int asi, offset;
475

    
476
    if (IS_IMM) {
477
        offset = GET_FIELD(insn, 25, 31);
478
        gen_op_ldstub_asi_reg(offset);
479
    } else {
480
        asi = GET_FIELD(insn, 19, 26);
481
        gen_op_ldstub_asi(asi);
482
    }
483
}
484

    
485
static inline void gen_ldda_asi(int insn)
486
{
487
    int asi, offset;
488

    
489
    if (IS_IMM) {
490
        offset = GET_FIELD(insn, 25, 31);
491
        gen_op_ldda_asi_reg(offset);
492
    } else {
493
        asi = GET_FIELD(insn, 19, 26);
494
        gen_op_ldda_asi(asi);
495
    }
496
}
497

    
498
static inline void gen_stda_asi(int insn)
499
{
500
    int asi, offset;
501

    
502
    if (IS_IMM) {
503
        offset = GET_FIELD(insn, 25, 31);
504
        gen_op_stda_asi_reg(offset);
505
    } else {
506
        asi = GET_FIELD(insn, 19, 26);
507
        gen_op_stda_asi(asi);
508
    }
509
}
510

    
511
static inline void gen_cas_asi(int insn)
512
{
513
    int asi, offset;
514

    
515
    if (IS_IMM) {
516
        offset = GET_FIELD(insn, 25, 31);
517
        gen_op_cas_asi_reg(offset);
518
    } else {
519
        asi = GET_FIELD(insn, 19, 26);
520
        gen_op_cas_asi(asi);
521
    }
522
}
523

    
524
static inline void gen_casx_asi(int insn)
525
{
526
    int asi, offset;
527

    
528
    if (IS_IMM) {
529
        offset = GET_FIELD(insn, 25, 31);
530
        gen_op_casx_asi_reg(offset);
531
    } else {
532
        asi = GET_FIELD(insn, 19, 26);
533
        gen_op_casx_asi(asi);
534
    }
535
}
536

    
537
#elif !defined(CONFIG_USER_ONLY)
538

    
539
static inline void gen_ld_asi(int insn, int size, int sign)
540
{
541
    int asi;
542

    
543
    asi = GET_FIELD(insn, 19, 26);
544
    gen_op_ld_asi(asi, size, sign);
545
}
546

    
547
static inline void gen_st_asi(int insn, int size)
548
{
549
    int asi;
550

    
551
    asi = GET_FIELD(insn, 19, 26);
552
    gen_op_st_asi(asi, size);
553
}
554

    
555
static inline void gen_ldstub_asi(int insn)
556
{
557
    int asi;
558

    
559
    asi = GET_FIELD(insn, 19, 26);
560
    gen_op_ldstub_asi(asi);
561
}
562

    
563
static inline void gen_swap_asi(int insn)
564
{
565
    int asi;
566

    
567
    asi = GET_FIELD(insn, 19, 26);
568
    gen_op_swap_asi(asi);
569
}
570

    
571
static inline void gen_ldda_asi(int insn)
572
{
573
    int asi;
574

    
575
    asi = GET_FIELD(insn, 19, 26);
576
    gen_op_ld_asi(asi, 8, 0);
577
}
578

    
579
static inline void gen_stda_asi(int insn)
580
{
581
    int asi;
582

    
583
    asi = GET_FIELD(insn, 19, 26);
584
    gen_op_st_asi(asi, 8);
585
}
586
#endif
587

    
588
static inline void gen_movl_imm_TN(int reg, uint32_t imm)
589
{
590
    gen_op_movl_TN_im[reg](imm);
591
}
592

    
593
static inline void gen_movl_imm_T1(uint32_t val)
594
{
595
    gen_movl_imm_TN(1, val);
596
}
597

    
598
static inline void gen_movl_imm_T0(uint32_t val)
599
{
600
    gen_movl_imm_TN(0, val);
601
}
602

    
603
static inline void gen_movl_simm_TN(int reg, int32_t imm)
604
{
605
    gen_op_movl_TN_sim[reg](imm);
606
}
607

    
608
static inline void gen_movl_simm_T1(int32_t val)
609
{
610
    gen_movl_simm_TN(1, val);
611
}
612

    
613
static inline void gen_movl_simm_T0(int32_t val)
614
{
615
    gen_movl_simm_TN(0, val);
616
}
617

    
618
static inline void gen_movl_reg_TN(int reg, int t)
619
{
620
    if (reg)
621
        gen_op_movl_reg_TN[t][reg] ();
622
    else
623
        gen_movl_imm_TN(t, 0);
624
}
625

    
626
static inline void gen_movl_reg_T0(int reg)
627
{
628
    gen_movl_reg_TN(reg, 0);
629
}
630

    
631
static inline void gen_movl_reg_T1(int reg)
632
{
633
    gen_movl_reg_TN(reg, 1);
634
}
635

    
636
static inline void gen_movl_reg_T2(int reg)
637
{
638
    gen_movl_reg_TN(reg, 2);
639
}
640

    
641
static inline void gen_movl_TN_reg(int reg, int t)
642
{
643
    if (reg)
644
        gen_op_movl_TN_reg[t][reg] ();
645
}
646

    
647
static inline void gen_movl_T0_reg(int reg)
648
{
649
    gen_movl_TN_reg(reg, 0);
650
}
651

    
652
static inline void gen_movl_T1_reg(int reg)
653
{
654
    gen_movl_TN_reg(reg, 1);
655
}
656

    
657
static inline void gen_jmp_im(target_ulong pc)
658
{
659
#ifdef TARGET_SPARC64
660
    if (pc == (uint32_t)pc) {
661
        gen_op_jmp_im(pc);
662
    } else {
663
        gen_op_jmp_im64(pc >> 32, pc);
664
    }
665
#else
666
    gen_op_jmp_im(pc);
667
#endif
668
}
669

    
670
static inline void gen_movl_npc_im(target_ulong npc)
671
{
672
#ifdef TARGET_SPARC64
673
    if (npc == (uint32_t)npc) {
674
        gen_op_movl_npc_im(npc);
675
    } else {
676
        gen_op_movq_npc_im64(npc >> 32, npc);
677
    }
678
#else
679
    gen_op_movl_npc_im(npc);
680
#endif
681
}
682

    
683
static inline void gen_goto_tb(DisasContext *s, int tb_num,
684
                               target_ulong pc, target_ulong npc)
685
{
686
    TranslationBlock *tb;
687

    
688
    tb = s->tb;
689
    if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
690
        (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK))  {
691
        /* jump to same page: we can use a direct jump */
692
        if (tb_num == 0)
693
            gen_op_goto_tb0(TBPARAM(tb));
694
        else
695
            gen_op_goto_tb1(TBPARAM(tb));
696
        gen_jmp_im(pc);
697
        gen_movl_npc_im(npc);
698
        gen_op_movl_T0_im((long)tb + tb_num);
699
        gen_op_exit_tb();
700
    } else {
701
        /* jump to another page: currently not optimized */
702
        gen_jmp_im(pc);
703
        gen_movl_npc_im(npc);
704
        gen_op_movl_T0_0();
705
        gen_op_exit_tb();
706
    }
707
}
708

    
709
static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
710
                               target_ulong pc2)
711
{
712
    int l1;
713

    
714
    l1 = gen_new_label();
715

    
716
    gen_op_jz_T2_label(l1);
717

    
718
    gen_goto_tb(dc, 0, pc1, pc1 + 4);
719

    
720
    gen_set_label(l1);
721
    gen_goto_tb(dc, 1, pc2, pc2 + 4);
722
}
723

    
724
static inline void gen_branch_a(DisasContext *dc, target_ulong pc1,
725
                                target_ulong pc2)
726
{
727
    int l1;
728

    
729
    l1 = gen_new_label();
730

    
731
    gen_op_jz_T2_label(l1);
732

    
733
    gen_goto_tb(dc, 0, pc2, pc1);
734

    
735
    gen_set_label(l1);
736
    gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
737
}
738

    
739
static inline void gen_branch(DisasContext *dc, target_ulong pc,
740
                              target_ulong npc)
741
{
742
    gen_goto_tb(dc, 0, pc, npc);
743
}
744

    
745
static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2)
746
{
747
    int l1, l2;
748

    
749
    l1 = gen_new_label();
750
    l2 = gen_new_label();
751
    gen_op_jz_T2_label(l1);
752

    
753
    gen_movl_npc_im(npc1);
754
    gen_op_jmp_label(l2);
755

    
756
    gen_set_label(l1);
757
    gen_movl_npc_im(npc2);
758
    gen_set_label(l2);
759
}
760

    
761
/* call this function before using T2 as it may have been set for a jump */
762
static inline void flush_T2(DisasContext * dc)
763
{
764
    if (dc->npc == JUMP_PC) {
765
        gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);
766
        dc->npc = DYNAMIC_PC;
767
    }
768
}
769

    
770
static inline void save_npc(DisasContext * dc)
771
{
772
    if (dc->npc == JUMP_PC) {
773
        gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);
774
        dc->npc = DYNAMIC_PC;
775
    } else if (dc->npc != DYNAMIC_PC) {
776
        gen_movl_npc_im(dc->npc);
777
    }
778
}
779

    
780
static inline void save_state(DisasContext * dc)
781
{
782
    gen_jmp_im(dc->pc);
783
    save_npc(dc);
784
}
785

    
786
static inline void gen_mov_pc_npc(DisasContext * dc)
787
{
788
    if (dc->npc == JUMP_PC) {
789
        gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);
790
        gen_op_mov_pc_npc();
791
        dc->pc = DYNAMIC_PC;
792
    } else if (dc->npc == DYNAMIC_PC) {
793
        gen_op_mov_pc_npc();
794
        dc->pc = DYNAMIC_PC;
795
    } else {
796
        dc->pc = dc->npc;
797
    }
798
}
799

    
800
static GenOpFunc * const gen_cond[2][16] = {
801
    {
802
        gen_op_eval_bn,
803
        gen_op_eval_be,
804
        gen_op_eval_ble,
805
        gen_op_eval_bl,
806
        gen_op_eval_bleu,
807
        gen_op_eval_bcs,
808
        gen_op_eval_bneg,
809
        gen_op_eval_bvs,
810
        gen_op_eval_ba,
811
        gen_op_eval_bne,
812
        gen_op_eval_bg,
813
        gen_op_eval_bge,
814
        gen_op_eval_bgu,
815
        gen_op_eval_bcc,
816
        gen_op_eval_bpos,
817
        gen_op_eval_bvc,
818
    },
819
    {
820
#ifdef TARGET_SPARC64
821
        gen_op_eval_bn,
822
        gen_op_eval_xbe,
823
        gen_op_eval_xble,
824
        gen_op_eval_xbl,
825
        gen_op_eval_xbleu,
826
        gen_op_eval_xbcs,
827
        gen_op_eval_xbneg,
828
        gen_op_eval_xbvs,
829
        gen_op_eval_ba,
830
        gen_op_eval_xbne,
831
        gen_op_eval_xbg,
832
        gen_op_eval_xbge,
833
        gen_op_eval_xbgu,
834
        gen_op_eval_xbcc,
835
        gen_op_eval_xbpos,
836
        gen_op_eval_xbvc,
837
#endif
838
    },
839
};
840

    
841
static GenOpFunc * const gen_fcond[4][16] = {
842
    {
843
        gen_op_eval_bn,
844
        gen_op_eval_fbne,
845
        gen_op_eval_fblg,
846
        gen_op_eval_fbul,
847
        gen_op_eval_fbl,
848
        gen_op_eval_fbug,
849
        gen_op_eval_fbg,
850
        gen_op_eval_fbu,
851
        gen_op_eval_ba,
852
        gen_op_eval_fbe,
853
        gen_op_eval_fbue,
854
        gen_op_eval_fbge,
855
        gen_op_eval_fbuge,
856
        gen_op_eval_fble,
857
        gen_op_eval_fbule,
858
        gen_op_eval_fbo,
859
    },
860
#ifdef TARGET_SPARC64
861
    {
862
        gen_op_eval_bn,
863
        gen_op_eval_fbne_fcc1,
864
        gen_op_eval_fblg_fcc1,
865
        gen_op_eval_fbul_fcc1,
866
        gen_op_eval_fbl_fcc1,
867
        gen_op_eval_fbug_fcc1,
868
        gen_op_eval_fbg_fcc1,
869
        gen_op_eval_fbu_fcc1,
870
        gen_op_eval_ba,
871
        gen_op_eval_fbe_fcc1,
872
        gen_op_eval_fbue_fcc1,
873
        gen_op_eval_fbge_fcc1,
874
        gen_op_eval_fbuge_fcc1,
875
        gen_op_eval_fble_fcc1,
876
        gen_op_eval_fbule_fcc1,
877
        gen_op_eval_fbo_fcc1,
878
    },
879
    {
880
        gen_op_eval_bn,
881
        gen_op_eval_fbne_fcc2,
882
        gen_op_eval_fblg_fcc2,
883
        gen_op_eval_fbul_fcc2,
884
        gen_op_eval_fbl_fcc2,
885
        gen_op_eval_fbug_fcc2,
886
        gen_op_eval_fbg_fcc2,
887
        gen_op_eval_fbu_fcc2,
888
        gen_op_eval_ba,
889
        gen_op_eval_fbe_fcc2,
890
        gen_op_eval_fbue_fcc2,
891
        gen_op_eval_fbge_fcc2,
892
        gen_op_eval_fbuge_fcc2,
893
        gen_op_eval_fble_fcc2,
894
        gen_op_eval_fbule_fcc2,
895
        gen_op_eval_fbo_fcc2,
896
    },
897
    {
898
        gen_op_eval_bn,
899
        gen_op_eval_fbne_fcc3,
900
        gen_op_eval_fblg_fcc3,
901
        gen_op_eval_fbul_fcc3,
902
        gen_op_eval_fbl_fcc3,
903
        gen_op_eval_fbug_fcc3,
904
        gen_op_eval_fbg_fcc3,
905
        gen_op_eval_fbu_fcc3,
906
        gen_op_eval_ba,
907
        gen_op_eval_fbe_fcc3,
908
        gen_op_eval_fbue_fcc3,
909
        gen_op_eval_fbge_fcc3,
910
        gen_op_eval_fbuge_fcc3,
911
        gen_op_eval_fble_fcc3,
912
        gen_op_eval_fbule_fcc3,
913
        gen_op_eval_fbo_fcc3,
914
    },
915
#else
916
    {}, {}, {},
917
#endif
918
};
919

    
920
#ifdef TARGET_SPARC64
921
static void gen_cond_reg(int cond)
922
{
923
        switch (cond) {
924
        case 0x1:
925
            gen_op_eval_brz();
926
            break;
927
        case 0x2:
928
            gen_op_eval_brlez();
929
            break;
930
        case 0x3:
931
            gen_op_eval_brlz();
932
            break;
933
        case 0x5:
934
            gen_op_eval_brnz();
935
            break;
936
        case 0x6:
937
            gen_op_eval_brgz();
938
            break;
939
        default:
940
        case 0x7:
941
            gen_op_eval_brgez();
942
            break;
943
        }
944
}
945
#endif
946

    
947
/* XXX: potentially incorrect if dynamic npc */
948
static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
949
{
950
    unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
951
    target_ulong target = dc->pc + offset;
952

    
953
    if (cond == 0x0) {
954
        /* unconditional not taken */
955
        if (a) {
956
            dc->pc = dc->npc + 4;
957
            dc->npc = dc->pc + 4;
958
        } else {
959
            dc->pc = dc->npc;
960
            dc->npc = dc->pc + 4;
961
        }
962
    } else if (cond == 0x8) {
963
        /* unconditional taken */
964
        if (a) {
965
            dc->pc = target;
966
            dc->npc = dc->pc + 4;
967
        } else {
968
            dc->pc = dc->npc;
969
            dc->npc = target;
970
        }
971
    } else {
972
        flush_T2(dc);
973
        gen_cond[cc][cond]();
974
        if (a) {
975
            gen_branch_a(dc, target, dc->npc);
976
            dc->is_br = 1;
977
        } else {
978
            dc->pc = dc->npc;
979
            dc->jump_pc[0] = target;
980
            dc->jump_pc[1] = dc->npc + 4;
981
            dc->npc = JUMP_PC;
982
        }
983
    }
984
}
985

    
986
/* XXX: potentially incorrect if dynamic npc */
987
static void do_fbranch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
988
{
989
    unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
990
    target_ulong target = dc->pc + offset;
991

    
992
    if (cond == 0x0) {
993
        /* unconditional not taken */
994
        if (a) {
995
            dc->pc = dc->npc + 4;
996
            dc->npc = dc->pc + 4;
997
        } else {
998
            dc->pc = dc->npc;
999
            dc->npc = dc->pc + 4;
1000
        }
1001
    } else if (cond == 0x8) {
1002
        /* unconditional taken */
1003
        if (a) {
1004
            dc->pc = target;
1005
            dc->npc = dc->pc + 4;
1006
        } else {
1007
            dc->pc = dc->npc;
1008
            dc->npc = target;
1009
        }
1010
    } else {
1011
        flush_T2(dc);
1012
        gen_fcond[cc][cond]();
1013
        if (a) {
1014
            gen_branch_a(dc, target, dc->npc);
1015
            dc->is_br = 1;
1016
        } else {
1017
            dc->pc = dc->npc;
1018
            dc->jump_pc[0] = target;
1019
            dc->jump_pc[1] = dc->npc + 4;
1020
            dc->npc = JUMP_PC;
1021
        }
1022
    }
1023
}
1024

    
1025
#ifdef TARGET_SPARC64
1026
/* XXX: potentially incorrect if dynamic npc */
1027
static void do_branch_reg(DisasContext * dc, int32_t offset, uint32_t insn)
1028
{
1029
    unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
1030
    target_ulong target = dc->pc + offset;
1031

    
1032
    flush_T2(dc);
1033
    gen_cond_reg(cond);
1034
    if (a) {
1035
        gen_branch_a(dc, target, dc->npc);
1036
        dc->is_br = 1;
1037
    } else {
1038
        dc->pc = dc->npc;
1039
        dc->jump_pc[0] = target;
1040
        dc->jump_pc[1] = dc->npc + 4;
1041
        dc->npc = JUMP_PC;
1042
    }
1043
}
1044

    
1045
static GenOpFunc * const gen_fcmps[4] = {
1046
    gen_op_fcmps,
1047
    gen_op_fcmps_fcc1,
1048
    gen_op_fcmps_fcc2,
1049
    gen_op_fcmps_fcc3,
1050
};
1051

    
1052
static GenOpFunc * const gen_fcmpd[4] = {
1053
    gen_op_fcmpd,
1054
    gen_op_fcmpd_fcc1,
1055
    gen_op_fcmpd_fcc2,
1056
    gen_op_fcmpd_fcc3,
1057
};
1058

    
1059
static GenOpFunc * const gen_fcmpes[4] = {
1060
    gen_op_fcmpes,
1061
    gen_op_fcmpes_fcc1,
1062
    gen_op_fcmpes_fcc2,
1063
    gen_op_fcmpes_fcc3,
1064
};
1065

    
1066
static GenOpFunc * const gen_fcmped[4] = {
1067
    gen_op_fcmped,
1068
    gen_op_fcmped_fcc1,
1069
    gen_op_fcmped_fcc2,
1070
    gen_op_fcmped_fcc3,
1071
};
1072

    
1073
#endif
1074

    
1075
static int gen_trap_ifnofpu(DisasContext * dc)
1076
{
1077
#if !defined(CONFIG_USER_ONLY)
1078
    if (!dc->fpu_enabled) {
1079
        save_state(dc);
1080
        gen_op_exception(TT_NFPU_INSN);
1081
        dc->is_br = 1;
1082
        return 1;
1083
    }
1084
#endif
1085
    return 0;
1086
}
1087

    
1088
/* before an instruction, dc->pc must be static */
1089
static void disas_sparc_insn(DisasContext * dc)
1090
{
1091
    unsigned int insn, opc, rs1, rs2, rd;
1092

    
1093
    insn = ldl_code(dc->pc);
1094
    opc = GET_FIELD(insn, 0, 1);
1095

    
1096
    rd = GET_FIELD(insn, 2, 6);
1097
    switch (opc) {
1098
    case 0:                     /* branches/sethi */
1099
        {
1100
            unsigned int xop = GET_FIELD(insn, 7, 9);
1101
            int32_t target;
1102
            switch (xop) {
1103
#ifdef TARGET_SPARC64
1104
            case 0x1:           /* V9 BPcc */
1105
                {
1106
                    int cc;
1107

    
1108
                    target = GET_FIELD_SP(insn, 0, 18);
1109
                    target = sign_extend(target, 18);
1110
                    target <<= 2;
1111
                    cc = GET_FIELD_SP(insn, 20, 21);
1112
                    if (cc == 0)
1113
                        do_branch(dc, target, insn, 0);
1114
                    else if (cc == 2)
1115
                        do_branch(dc, target, insn, 1);
1116
                    else
1117
                        goto illegal_insn;
1118
                    goto jmp_insn;
1119
                }
1120
            case 0x3:           /* V9 BPr */
1121
                {
1122
                    target = GET_FIELD_SP(insn, 0, 13) |
1123
                        (GET_FIELD_SP(insn, 20, 21) << 14);
1124
                    target = sign_extend(target, 16);
1125
                    target <<= 2;
1126
                    rs1 = GET_FIELD(insn, 13, 17);
1127
                    gen_movl_reg_T0(rs1);
1128
                    do_branch_reg(dc, target, insn);
1129
                    goto jmp_insn;
1130
                }
1131
            case 0x5:           /* V9 FBPcc */
1132
                {
1133
                    int cc = GET_FIELD_SP(insn, 20, 21);
1134
                    if (gen_trap_ifnofpu(dc))
1135
                        goto jmp_insn;
1136
                    target = GET_FIELD_SP(insn, 0, 18);
1137
                    target = sign_extend(target, 19);
1138
                    target <<= 2;
1139
                    do_fbranch(dc, target, insn, cc);
1140
                    goto jmp_insn;
1141
                }
1142
#else
1143
            case 0x7:           /* CBN+x */
1144
                {
1145
                    goto ncp_insn;
1146
                }
1147
#endif
1148
            case 0x2:           /* BN+x */
1149
                {
1150
                    target = GET_FIELD(insn, 10, 31);
1151
                    target = sign_extend(target, 22);
1152
                    target <<= 2;
1153
                    do_branch(dc, target, insn, 0);
1154
                    goto jmp_insn;
1155
                }
1156
            case 0x6:           /* FBN+x */
1157
                {
1158
                    if (gen_trap_ifnofpu(dc))
1159
                        goto jmp_insn;
1160
                    target = GET_FIELD(insn, 10, 31);
1161
                    target = sign_extend(target, 22);
1162
                    target <<= 2;
1163
                    do_fbranch(dc, target, insn, 0);
1164
                    goto jmp_insn;
1165
                }
1166
            case 0x4:           /* SETHI */
1167
#define OPTIM
1168
#if defined(OPTIM)
1169
                if (rd) { // nop
1170
#endif
1171
                    uint32_t value = GET_FIELD(insn, 10, 31);
1172
                    gen_movl_imm_T0(value << 10);
1173
                    gen_movl_T0_reg(rd);
1174
#if defined(OPTIM)
1175
                }
1176
#endif
1177
                break;
1178
            case 0x0:           /* UNIMPL */
1179
            default:
1180
                goto illegal_insn;
1181
            }
1182
            break;
1183
        }
1184
        break;
1185
    case 1:
1186
        /*CALL*/ {
1187
            target_long target = GET_FIELDs(insn, 2, 31) << 2;
1188

    
1189
#ifdef TARGET_SPARC64
1190
            if (dc->pc == (uint32_t)dc->pc) {
1191
                gen_op_movl_T0_im(dc->pc);
1192
            } else {
1193
                gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
1194
            }
1195
#else
1196
            gen_op_movl_T0_im(dc->pc);
1197
#endif
1198
            gen_movl_T0_reg(15);
1199
            target += dc->pc;
1200
            gen_mov_pc_npc(dc);
1201
            dc->npc = target;
1202
        }
1203
        goto jmp_insn;
1204
    case 2:                     /* FPU & Logical Operations */
1205
        {
1206
            unsigned int xop = GET_FIELD(insn, 7, 12);
1207
            if (xop == 0x3a) {  /* generate trap */
1208
                int cond;
1209

    
1210
                rs1 = GET_FIELD(insn, 13, 17);
1211
                gen_movl_reg_T0(rs1);
1212
                if (IS_IMM) {
1213
                    rs2 = GET_FIELD(insn, 25, 31);
1214
#if defined(OPTIM)
1215
                    if (rs2 != 0) {
1216
#endif
1217
                        gen_movl_simm_T1(rs2);
1218
                        gen_op_add_T1_T0();
1219
#if defined(OPTIM)
1220
                    }
1221
#endif
1222
                } else {
1223
                    rs2 = GET_FIELD(insn, 27, 31);
1224
#if defined(OPTIM)
1225
                    if (rs2 != 0) {
1226
#endif
1227
                        gen_movl_reg_T1(rs2);
1228
                        gen_op_add_T1_T0();
1229
#if defined(OPTIM)
1230
                    }
1231
#endif
1232
                }
1233
                cond = GET_FIELD(insn, 3, 6);
1234
                if (cond == 0x8) {
1235
                    save_state(dc);
1236
                    gen_op_trap_T0();
1237
                } else if (cond != 0) {
1238
#ifdef TARGET_SPARC64
1239
                    /* V9 icc/xcc */
1240
                    int cc = GET_FIELD_SP(insn, 11, 12);
1241
                    flush_T2(dc);
1242
                    save_state(dc);
1243
                    if (cc == 0)
1244
                        gen_cond[0][cond]();
1245
                    else if (cc == 2)
1246
                        gen_cond[1][cond]();
1247
                    else
1248
                        goto illegal_insn;
1249
#else
1250
                    flush_T2(dc);
1251
                    save_state(dc);
1252
                    gen_cond[0][cond]();
1253
#endif
1254
                    gen_op_trapcc_T0();
1255
                }
1256
                gen_op_next_insn();
1257
                gen_op_movl_T0_0();
1258
                gen_op_exit_tb();
1259
                dc->is_br = 1;
1260
                goto jmp_insn;
1261
            } else if (xop == 0x28) {
1262
                rs1 = GET_FIELD(insn, 13, 17);
1263
                switch(rs1) {
1264
                case 0: /* rdy */
1265
#ifndef TARGET_SPARC64
1266
                case 0x01 ... 0x0e: /* undefined in the SPARCv8
1267
                                       manual, rdy on the microSPARC
1268
                                       II */
1269
                case 0x0f:          /* stbar in the SPARCv8 manual,
1270
                                       rdy on the microSPARC II */
1271
                case 0x10 ... 0x1f: /* implementation-dependent in the
1272
                                       SPARCv8 manual, rdy on the
1273
                                       microSPARC II */
1274
#endif
1275
                    gen_op_movtl_T0_env(offsetof(CPUSPARCState, y));
1276
                    gen_movl_T0_reg(rd);
1277
                    break;
1278
#ifdef TARGET_SPARC64
1279
                case 0x2: /* V9 rdccr */
1280
                    gen_op_rdccr();
1281
                    gen_movl_T0_reg(rd);
1282
                    break;
1283
                case 0x3: /* V9 rdasi */
1284
                    gen_op_movl_T0_env(offsetof(CPUSPARCState, asi));
1285
                    gen_movl_T0_reg(rd);
1286
                    break;
1287
                case 0x4: /* V9 rdtick */
1288
                    gen_op_rdtick();
1289
                    gen_movl_T0_reg(rd);
1290
                    break;
1291
                case 0x5: /* V9 rdpc */
1292
                    if (dc->pc == (uint32_t)dc->pc) {
1293
                        gen_op_movl_T0_im(dc->pc);
1294
                    } else {
1295
                        gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
1296
                    }
1297
                    gen_movl_T0_reg(rd);
1298
                    break;
1299
                case 0x6: /* V9 rdfprs */
1300
                    gen_op_movl_T0_env(offsetof(CPUSPARCState, fprs));
1301
                    gen_movl_T0_reg(rd);
1302
                    break;
1303
                case 0xf: /* V9 membar */
1304
                    break; /* no effect */
1305
                case 0x13: /* Graphics Status */
1306
                    if (gen_trap_ifnofpu(dc))
1307
                        goto jmp_insn;
1308
                    gen_op_movtl_T0_env(offsetof(CPUSPARCState, gsr));
1309
                    gen_movl_T0_reg(rd);
1310
                    break;
1311
                case 0x17: /* Tick compare */
1312
                    gen_op_movtl_T0_env(offsetof(CPUSPARCState, tick_cmpr));
1313
                    gen_movl_T0_reg(rd);
1314
                    break;
1315
                case 0x18: /* System tick */
1316
                    gen_op_rdstick();
1317
                    gen_movl_T0_reg(rd);
1318
                    break;
1319
                case 0x19: /* System tick compare */
1320
                    gen_op_movtl_T0_env(offsetof(CPUSPARCState, stick_cmpr));
1321
                    gen_movl_T0_reg(rd);
1322
                    break;
1323
                case 0x10: /* Performance Control */
1324
                case 0x11: /* Performance Instrumentation Counter */
1325
                case 0x12: /* Dispatch Control */
1326
                case 0x14: /* Softint set, WO */
1327
                case 0x15: /* Softint clear, WO */
1328
                case 0x16: /* Softint write */
1329
#endif
1330
                default:
1331
                    goto illegal_insn;
1332
                }
1333
#if !defined(CONFIG_USER_ONLY)
1334
            } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
1335
#ifndef TARGET_SPARC64
1336
                if (!supervisor(dc))
1337
                    goto priv_insn;
1338
                gen_op_rdpsr();
1339
#else
1340
                if (!hypervisor(dc))
1341
                    goto priv_insn;
1342
                rs1 = GET_FIELD(insn, 13, 17);
1343
                switch (rs1) {
1344
                case 0: // hpstate
1345
                    // gen_op_rdhpstate();
1346
                    break;
1347
                case 1: // htstate
1348
                    // gen_op_rdhtstate();
1349
                    break;
1350
                case 3: // hintp
1351
                    gen_op_movl_T0_env(offsetof(CPUSPARCState, hintp));
1352
                    break;
1353
                case 5: // htba
1354
                    gen_op_movl_T0_env(offsetof(CPUSPARCState, htba));
1355
                    break;
1356
                case 6: // hver
1357
                    gen_op_movl_T0_env(offsetof(CPUSPARCState, hver));
1358
                    break;
1359
                case 31: // hstick_cmpr
1360
                    gen_op_movl_env_T0(offsetof(CPUSPARCState, hstick_cmpr));
1361
                    break;
1362
                default:
1363
                    goto illegal_insn;
1364
                }
1365
#endif
1366
                gen_movl_T0_reg(rd);
1367
                break;
1368
            } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
1369
                if (!supervisor(dc))
1370
                    goto priv_insn;
1371
#ifdef TARGET_SPARC64
1372
                rs1 = GET_FIELD(insn, 13, 17);
1373
                switch (rs1) {
1374
                case 0: // tpc
1375
                    gen_op_rdtpc();
1376
                    break;
1377
                case 1: // tnpc
1378
                    gen_op_rdtnpc();
1379
                    break;
1380
                case 2: // tstate
1381
                    gen_op_rdtstate();
1382
                    break;
1383
                case 3: // tt
1384
                    gen_op_rdtt();
1385
                    break;
1386
                case 4: // tick
1387
                    gen_op_rdtick();
1388
                    break;
1389
                case 5: // tba
1390
                    gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
1391
                    break;
1392
                case 6: // pstate
1393
                    gen_op_rdpstate();
1394
                    break;
1395
                case 7: // tl
1396
                    gen_op_movl_T0_env(offsetof(CPUSPARCState, tl));
1397
                    break;
1398
                case 8: // pil
1399
                    gen_op_movl_T0_env(offsetof(CPUSPARCState, psrpil));
1400
                    break;
1401
                case 9: // cwp
1402
                    gen_op_rdcwp();
1403
                    break;
1404
                case 10: // cansave
1405
                    gen_op_movl_T0_env(offsetof(CPUSPARCState, cansave));
1406
                    break;
1407
                case 11: // canrestore
1408
                    gen_op_movl_T0_env(offsetof(CPUSPARCState, canrestore));
1409
                    break;
1410
                case 12: // cleanwin
1411
                    gen_op_movl_T0_env(offsetof(CPUSPARCState, cleanwin));
1412
                    break;
1413
                case 13: // otherwin
1414
                    gen_op_movl_T0_env(offsetof(CPUSPARCState, otherwin));
1415
                    break;
1416
                case 14: // wstate
1417
                    gen_op_movl_T0_env(offsetof(CPUSPARCState, wstate));
1418
                    break;
1419
                case 16: // UA2005 gl
1420
                    gen_op_movl_T0_env(offsetof(CPUSPARCState, gl));
1421
                    break;
1422
                case 26: // UA2005 strand status
1423
                    if (!hypervisor(dc))
1424
                        goto priv_insn;
1425
                    gen_op_movl_T0_env(offsetof(CPUSPARCState, ssr));
1426
                    break;
1427
                case 31: // ver
1428
                    gen_op_movtl_T0_env(offsetof(CPUSPARCState, version));
1429
                    break;
1430
                case 15: // fq
1431
                default:
1432
                    goto illegal_insn;
1433
                }
1434
#else
1435
                gen_op_movl_T0_env(offsetof(CPUSPARCState, wim));
1436
#endif
1437
                gen_movl_T0_reg(rd);
1438
                break;
1439
            } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
1440
#ifdef TARGET_SPARC64
1441
                gen_op_flushw();
1442
#else
1443
                if (!supervisor(dc))
1444
                    goto priv_insn;
1445
                gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
1446
                gen_movl_T0_reg(rd);
1447
#endif
1448
                break;
1449
#endif
1450
            } else if (xop == 0x34) {   /* FPU Operations */
1451
                if (gen_trap_ifnofpu(dc))
1452
                    goto jmp_insn;
1453
                gen_op_clear_ieee_excp_and_FTT();
1454
                rs1 = GET_FIELD(insn, 13, 17);
1455
                rs2 = GET_FIELD(insn, 27, 31);
1456
                xop = GET_FIELD(insn, 18, 26);
1457
                switch (xop) {
1458
                    case 0x1: /* fmovs */
1459
                        gen_op_load_fpr_FT0(rs2);
1460
                        gen_op_store_FT0_fpr(rd);
1461
                        break;
1462
                    case 0x5: /* fnegs */
1463
                        gen_op_load_fpr_FT1(rs2);
1464
                        gen_op_fnegs();
1465
                        gen_op_store_FT0_fpr(rd);
1466
                        break;
1467
                    case 0x9: /* fabss */
1468
                        gen_op_load_fpr_FT1(rs2);
1469
                        gen_op_fabss();
1470
                        gen_op_store_FT0_fpr(rd);
1471
                        break;
1472
                    case 0x29: /* fsqrts */
1473
                        gen_op_load_fpr_FT1(rs2);
1474
                        gen_op_fsqrts();
1475
                        gen_op_store_FT0_fpr(rd);
1476
                        break;
1477
                    case 0x2a: /* fsqrtd */
1478
                        gen_op_load_fpr_DT1(DFPREG(rs2));
1479
                        gen_op_fsqrtd();
1480
                        gen_op_store_DT0_fpr(DFPREG(rd));
1481
                        break;
1482
                    case 0x2b: /* fsqrtq */
1483
                        goto nfpu_insn;
1484
                    case 0x41:
1485
                        gen_op_load_fpr_FT0(rs1);
1486
                        gen_op_load_fpr_FT1(rs2);
1487
                        gen_op_fadds();
1488
                        gen_op_store_FT0_fpr(rd);
1489
                        break;
1490
                    case 0x42:
1491
                        gen_op_load_fpr_DT0(DFPREG(rs1));
1492
                        gen_op_load_fpr_DT1(DFPREG(rs2));
1493
                        gen_op_faddd();
1494
                        gen_op_store_DT0_fpr(DFPREG(rd));
1495
                        break;
1496
                    case 0x43: /* faddq */
1497
                        goto nfpu_insn;
1498
                    case 0x45:
1499
                        gen_op_load_fpr_FT0(rs1);
1500
                        gen_op_load_fpr_FT1(rs2);
1501
                        gen_op_fsubs();
1502
                        gen_op_store_FT0_fpr(rd);
1503
                        break;
1504
                    case 0x46:
1505
                        gen_op_load_fpr_DT0(DFPREG(rs1));
1506
                        gen_op_load_fpr_DT1(DFPREG(rs2));
1507
                        gen_op_fsubd();
1508
                        gen_op_store_DT0_fpr(DFPREG(rd));
1509
                        break;
1510
                    case 0x47: /* fsubq */
1511
                        goto nfpu_insn;
1512
                    case 0x49:
1513
                        gen_op_load_fpr_FT0(rs1);
1514
                        gen_op_load_fpr_FT1(rs2);
1515
                        gen_op_fmuls();
1516
                        gen_op_store_FT0_fpr(rd);
1517
                        break;
1518
                    case 0x4a:
1519
                        gen_op_load_fpr_DT0(DFPREG(rs1));
1520
                        gen_op_load_fpr_DT1(DFPREG(rs2));
1521
                        gen_op_fmuld();
1522
                        gen_op_store_DT0_fpr(rd);
1523
                        break;
1524
                    case 0x4b: /* fmulq */
1525
                        goto nfpu_insn;
1526
                    case 0x4d:
1527
                        gen_op_load_fpr_FT0(rs1);
1528
                        gen_op_load_fpr_FT1(rs2);
1529
                        gen_op_fdivs();
1530
                        gen_op_store_FT0_fpr(rd);
1531
                        break;
1532
                    case 0x4e:
1533
                        gen_op_load_fpr_DT0(DFPREG(rs1));
1534
                        gen_op_load_fpr_DT1(DFPREG(rs2));
1535
                        gen_op_fdivd();
1536
                        gen_op_store_DT0_fpr(DFPREG(rd));
1537
                        break;
1538
                    case 0x4f: /* fdivq */
1539
                        goto nfpu_insn;
1540
                    case 0x69:
1541
                        gen_op_load_fpr_FT0(rs1);
1542
                        gen_op_load_fpr_FT1(rs2);
1543
                        gen_op_fsmuld();
1544
                        gen_op_store_DT0_fpr(DFPREG(rd));
1545
                        break;
1546
                    case 0x6e: /* fdmulq */
1547
                        goto nfpu_insn;
1548
                    case 0xc4:
1549
                        gen_op_load_fpr_FT1(rs2);
1550
                        gen_op_fitos();
1551
                        gen_op_store_FT0_fpr(rd);
1552
                        break;
1553
                    case 0xc6:
1554
                        gen_op_load_fpr_DT1(DFPREG(rs2));
1555
                        gen_op_fdtos();
1556
                        gen_op_store_FT0_fpr(rd);
1557
                        break;
1558
                    case 0xc7: /* fqtos */
1559
                        goto nfpu_insn;
1560
                    case 0xc8:
1561
                        gen_op_load_fpr_FT1(rs2);
1562
                        gen_op_fitod();
1563
                        gen_op_store_DT0_fpr(DFPREG(rd));
1564
                        break;
1565
                    case 0xc9:
1566
                        gen_op_load_fpr_FT1(rs2);
1567
                        gen_op_fstod();
1568
                        gen_op_store_DT0_fpr(DFPREG(rd));
1569
                        break;
1570
                    case 0xcb: /* fqtod */
1571
                        goto nfpu_insn;
1572
                    case 0xcc: /* fitoq */
1573
                        goto nfpu_insn;
1574
                    case 0xcd: /* fstoq */
1575
                        goto nfpu_insn;
1576
                    case 0xce: /* fdtoq */
1577
                        goto nfpu_insn;
1578
                    case 0xd1:
1579
                        gen_op_load_fpr_FT1(rs2);
1580
                        gen_op_fstoi();
1581
                        gen_op_store_FT0_fpr(rd);
1582
                        break;
1583
                    case 0xd2:
1584
                        gen_op_load_fpr_DT1(rs2);
1585
                        gen_op_fdtoi();
1586
                        gen_op_store_FT0_fpr(rd);
1587
                        break;
1588
                    case 0xd3: /* fqtoi */
1589
                        goto nfpu_insn;
1590
#ifdef TARGET_SPARC64
1591
                    case 0x2: /* V9 fmovd */
1592
                        gen_op_load_fpr_DT0(DFPREG(rs2));
1593
                        gen_op_store_DT0_fpr(DFPREG(rd));
1594
                        break;
1595
                    case 0x6: /* V9 fnegd */
1596
                        gen_op_load_fpr_DT1(DFPREG(rs2));
1597
                        gen_op_fnegd();
1598
                        gen_op_store_DT0_fpr(DFPREG(rd));
1599
                        break;
1600
                    case 0xa: /* V9 fabsd */
1601
                        gen_op_load_fpr_DT1(DFPREG(rs2));
1602
                        gen_op_fabsd();
1603
                        gen_op_store_DT0_fpr(DFPREG(rd));
1604
                        break;
1605
                    case 0x81: /* V9 fstox */
1606
                        gen_op_load_fpr_FT1(rs2);
1607
                        gen_op_fstox();
1608
                        gen_op_store_DT0_fpr(DFPREG(rd));
1609
                        break;
1610
                    case 0x82: /* V9 fdtox */
1611
                        gen_op_load_fpr_DT1(DFPREG(rs2));
1612
                        gen_op_fdtox();
1613
                        gen_op_store_DT0_fpr(DFPREG(rd));
1614
                        break;
1615
                    case 0x84: /* V9 fxtos */
1616
                        gen_op_load_fpr_DT1(DFPREG(rs2));
1617
                        gen_op_fxtos();
1618
                        gen_op_store_FT0_fpr(rd);
1619
                        break;
1620
                    case 0x88: /* V9 fxtod */
1621
                        gen_op_load_fpr_DT1(DFPREG(rs2));
1622
                        gen_op_fxtod();
1623
                        gen_op_store_DT0_fpr(DFPREG(rd));
1624
                        break;
1625
                    case 0x3: /* V9 fmovq */
1626
                    case 0x7: /* V9 fnegq */
1627
                    case 0xb: /* V9 fabsq */
1628
                    case 0x83: /* V9 fqtox */
1629
                    case 0x8c: /* V9 fxtoq */
1630
                        goto nfpu_insn;
1631
#endif
1632
                    default:
1633
                        goto illegal_insn;
1634
                }
1635
            } else if (xop == 0x35) {   /* FPU Operations */
1636
#ifdef TARGET_SPARC64
1637
                int cond;
1638
#endif
1639
                if (gen_trap_ifnofpu(dc))
1640
                    goto jmp_insn;
1641
                gen_op_clear_ieee_excp_and_FTT();
1642
                rs1 = GET_FIELD(insn, 13, 17);
1643
                rs2 = GET_FIELD(insn, 27, 31);
1644
                xop = GET_FIELD(insn, 18, 26);
1645
#ifdef TARGET_SPARC64
1646
                if ((xop & 0x11f) == 0x005) { // V9 fmovsr
1647
                    cond = GET_FIELD_SP(insn, 14, 17);
1648
                    gen_op_load_fpr_FT0(rd);
1649
                    gen_op_load_fpr_FT1(rs2);
1650
                    rs1 = GET_FIELD(insn, 13, 17);
1651
                    gen_movl_reg_T0(rs1);
1652
                    flush_T2(dc);
1653
                    gen_cond_reg(cond);
1654
                    gen_op_fmovs_cc();
1655
                    gen_op_store_FT0_fpr(rd);
1656
                    break;
1657
                } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
1658
                    cond = GET_FIELD_SP(insn, 14, 17);
1659
                    gen_op_load_fpr_DT0(rd);
1660
                    gen_op_load_fpr_DT1(rs2);
1661
                    flush_T2(dc);
1662
                    rs1 = GET_FIELD(insn, 13, 17);
1663
                    gen_movl_reg_T0(rs1);
1664
                    gen_cond_reg(cond);
1665
                    gen_op_fmovs_cc();
1666
                    gen_op_store_DT0_fpr(rd);
1667
                    break;
1668
                } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
1669
                    goto nfpu_insn;
1670
                }
1671
#endif
1672
                switch (xop) {
1673
#ifdef TARGET_SPARC64
1674
                    case 0x001: /* V9 fmovscc %fcc0 */
1675
                        cond = GET_FIELD_SP(insn, 14, 17);
1676
                        gen_op_load_fpr_FT0(rd);
1677
                        gen_op_load_fpr_FT1(rs2);
1678
                        flush_T2(dc);
1679
                        gen_fcond[0][cond]();
1680
                        gen_op_fmovs_cc();
1681
                        gen_op_store_FT0_fpr(rd);
1682
                        break;
1683
                    case 0x002: /* V9 fmovdcc %fcc0 */
1684
                        cond = GET_FIELD_SP(insn, 14, 17);
1685
                        gen_op_load_fpr_DT0(rd);
1686
                        gen_op_load_fpr_DT1(rs2);
1687
                        flush_T2(dc);
1688
                        gen_fcond[0][cond]();
1689
                        gen_op_fmovd_cc();
1690
                        gen_op_store_DT0_fpr(rd);
1691
                        break;
1692
                    case 0x003: /* V9 fmovqcc %fcc0 */
1693
                        goto nfpu_insn;
1694
                    case 0x041: /* V9 fmovscc %fcc1 */
1695
                        cond = GET_FIELD_SP(insn, 14, 17);
1696
                        gen_op_load_fpr_FT0(rd);
1697
                        gen_op_load_fpr_FT1(rs2);
1698
                        flush_T2(dc);
1699
                        gen_fcond[1][cond]();
1700
                        gen_op_fmovs_cc();
1701
                        gen_op_store_FT0_fpr(rd);
1702
                        break;
1703
                    case 0x042: /* V9 fmovdcc %fcc1 */
1704
                        cond = GET_FIELD_SP(insn, 14, 17);
1705
                        gen_op_load_fpr_DT0(rd);
1706
                        gen_op_load_fpr_DT1(rs2);
1707
                        flush_T2(dc);
1708
                        gen_fcond[1][cond]();
1709
                        gen_op_fmovd_cc();
1710
                        gen_op_store_DT0_fpr(rd);
1711
                        break;
1712
                    case 0x043: /* V9 fmovqcc %fcc1 */
1713
                        goto nfpu_insn;
1714
                    case 0x081: /* V9 fmovscc %fcc2 */
1715
                        cond = GET_FIELD_SP(insn, 14, 17);
1716
                        gen_op_load_fpr_FT0(rd);
1717
                        gen_op_load_fpr_FT1(rs2);
1718
                        flush_T2(dc);
1719
                        gen_fcond[2][cond]();
1720
                        gen_op_fmovs_cc();
1721
                        gen_op_store_FT0_fpr(rd);
1722
                        break;
1723
                    case 0x082: /* V9 fmovdcc %fcc2 */
1724
                        cond = GET_FIELD_SP(insn, 14, 17);
1725
                        gen_op_load_fpr_DT0(rd);
1726
                        gen_op_load_fpr_DT1(rs2);
1727
                        flush_T2(dc);
1728
                        gen_fcond[2][cond]();
1729
                        gen_op_fmovd_cc();
1730
                        gen_op_store_DT0_fpr(rd);
1731
                        break;
1732
                    case 0x083: /* V9 fmovqcc %fcc2 */
1733
                        goto nfpu_insn;
1734
                    case 0x0c1: /* V9 fmovscc %fcc3 */
1735
                        cond = GET_FIELD_SP(insn, 14, 17);
1736
                        gen_op_load_fpr_FT0(rd);
1737
                        gen_op_load_fpr_FT1(rs2);
1738
                        flush_T2(dc);
1739
                        gen_fcond[3][cond]();
1740
                        gen_op_fmovs_cc();
1741
                        gen_op_store_FT0_fpr(rd);
1742
                        break;
1743
                    case 0x0c2: /* V9 fmovdcc %fcc3 */
1744
                        cond = GET_FIELD_SP(insn, 14, 17);
1745
                        gen_op_load_fpr_DT0(rd);
1746
                        gen_op_load_fpr_DT1(rs2);
1747
                        flush_T2(dc);
1748
                        gen_fcond[3][cond]();
1749
                        gen_op_fmovd_cc();
1750
                        gen_op_store_DT0_fpr(rd);
1751
                        break;
1752
                    case 0x0c3: /* V9 fmovqcc %fcc3 */
1753
                        goto nfpu_insn;
1754
                    case 0x101: /* V9 fmovscc %icc */
1755
                        cond = GET_FIELD_SP(insn, 14, 17);
1756
                        gen_op_load_fpr_FT0(rd);
1757
                        gen_op_load_fpr_FT1(rs2);
1758
                        flush_T2(dc);
1759
                        gen_cond[0][cond]();
1760
                        gen_op_fmovs_cc();
1761
                        gen_op_store_FT0_fpr(rd);
1762
                        break;
1763
                    case 0x102: /* V9 fmovdcc %icc */
1764
                        cond = GET_FIELD_SP(insn, 14, 17);
1765
                        gen_op_load_fpr_DT0(rd);
1766
                        gen_op_load_fpr_DT1(rs2);
1767
                        flush_T2(dc);
1768
                        gen_cond[0][cond]();
1769
                        gen_op_fmovd_cc();
1770
                        gen_op_store_DT0_fpr(rd);
1771
                        break;
1772
                    case 0x103: /* V9 fmovqcc %icc */
1773
                        goto nfpu_insn;
1774
                    case 0x181: /* V9 fmovscc %xcc */
1775
                        cond = GET_FIELD_SP(insn, 14, 17);
1776
                        gen_op_load_fpr_FT0(rd);
1777
                        gen_op_load_fpr_FT1(rs2);
1778
                        flush_T2(dc);
1779
                        gen_cond[1][cond]();
1780
                        gen_op_fmovs_cc();
1781
                        gen_op_store_FT0_fpr(rd);
1782
                        break;
1783
                    case 0x182: /* V9 fmovdcc %xcc */
1784
                        cond = GET_FIELD_SP(insn, 14, 17);
1785
                        gen_op_load_fpr_DT0(rd);
1786
                        gen_op_load_fpr_DT1(rs2);
1787
                        flush_T2(dc);
1788
                        gen_cond[1][cond]();
1789
                        gen_op_fmovd_cc();
1790
                        gen_op_store_DT0_fpr(rd);
1791
                        break;
1792
                    case 0x183: /* V9 fmovqcc %xcc */
1793
                        goto nfpu_insn;
1794
#endif
1795
                    case 0x51: /* V9 %fcc */
1796
                        gen_op_load_fpr_FT0(rs1);
1797
                        gen_op_load_fpr_FT1(rs2);
1798
#ifdef TARGET_SPARC64
1799
                        gen_fcmps[rd & 3]();
1800
#else
1801
                        gen_op_fcmps();
1802
#endif
1803
                        break;
1804
                    case 0x52: /* V9 %fcc */
1805
                        gen_op_load_fpr_DT0(DFPREG(rs1));
1806
                        gen_op_load_fpr_DT1(DFPREG(rs2));
1807
#ifdef TARGET_SPARC64
1808
                        gen_fcmpd[rd & 3]();
1809
#else
1810
                        gen_op_fcmpd();
1811
#endif
1812
                        break;
1813
                    case 0x53: /* fcmpq */
1814
                        goto nfpu_insn;
1815
                    case 0x55: /* fcmpes, V9 %fcc */
1816
                        gen_op_load_fpr_FT0(rs1);
1817
                        gen_op_load_fpr_FT1(rs2);
1818
#ifdef TARGET_SPARC64
1819
                        gen_fcmpes[rd & 3]();
1820
#else
1821
                        gen_op_fcmpes();
1822
#endif
1823
                        break;
1824
                    case 0x56: /* fcmped, V9 %fcc */
1825
                        gen_op_load_fpr_DT0(DFPREG(rs1));
1826
                        gen_op_load_fpr_DT1(DFPREG(rs2));
1827
#ifdef TARGET_SPARC64
1828
                        gen_fcmped[rd & 3]();
1829
#else
1830
                        gen_op_fcmped();
1831
#endif
1832
                        break;
1833
                    case 0x57: /* fcmpeq */
1834
                        goto nfpu_insn;
1835
                    default:
1836
                        goto illegal_insn;
1837
                }
1838
#if defined(OPTIM)
1839
            } else if (xop == 0x2) {
1840
                // clr/mov shortcut
1841

    
1842
                rs1 = GET_FIELD(insn, 13, 17);
1843
                if (rs1 == 0) {
1844
                    // or %g0, x, y -> mov T1, x; mov y, T1
1845
                    if (IS_IMM) {       /* immediate */
1846
                        rs2 = GET_FIELDs(insn, 19, 31);
1847
                        gen_movl_simm_T1(rs2);
1848
                    } else {            /* register */
1849
                        rs2 = GET_FIELD(insn, 27, 31);
1850
                        gen_movl_reg_T1(rs2);
1851
                    }
1852
                    gen_movl_T1_reg(rd);
1853
                } else {
1854
                    gen_movl_reg_T0(rs1);
1855
                    if (IS_IMM) {       /* immediate */
1856
                        // or x, #0, y -> mov T1, x; mov y, T1
1857
                        rs2 = GET_FIELDs(insn, 19, 31);
1858
                        if (rs2 != 0) {
1859
                            gen_movl_simm_T1(rs2);
1860
                            gen_op_or_T1_T0();
1861
                        }
1862
                    } else {            /* register */
1863
                        // or x, %g0, y -> mov T1, x; mov y, T1
1864
                        rs2 = GET_FIELD(insn, 27, 31);
1865
                        if (rs2 != 0) {
1866
                            gen_movl_reg_T1(rs2);
1867
                            gen_op_or_T1_T0();
1868
                        }
1869
                    }
1870
                    gen_movl_T0_reg(rd);
1871
                }
1872
#endif
1873
#ifdef TARGET_SPARC64
1874
            } else if (xop == 0x25) { /* sll, V9 sllx */
1875
                rs1 = GET_FIELD(insn, 13, 17);
1876
                gen_movl_reg_T0(rs1);
1877
                if (IS_IMM) {   /* immediate */
1878
                    rs2 = GET_FIELDs(insn, 20, 31);
1879
                    gen_movl_simm_T1(rs2);
1880
                } else {                /* register */
1881
                    rs2 = GET_FIELD(insn, 27, 31);
1882
                    gen_movl_reg_T1(rs2);
1883
                }
1884
                if (insn & (1 << 12))
1885
                    gen_op_sllx();
1886
                else
1887
                    gen_op_sll();
1888
                gen_movl_T0_reg(rd);
1889
            } else if (xop == 0x26) { /* srl, V9 srlx */
1890
                rs1 = GET_FIELD(insn, 13, 17);
1891
                gen_movl_reg_T0(rs1);
1892
                if (IS_IMM) {   /* immediate */
1893
                    rs2 = GET_FIELDs(insn, 20, 31);
1894
                    gen_movl_simm_T1(rs2);
1895
                } else {                /* register */
1896
                    rs2 = GET_FIELD(insn, 27, 31);
1897
                    gen_movl_reg_T1(rs2);
1898
                }
1899
                if (insn & (1 << 12))
1900
                    gen_op_srlx();
1901
                else
1902
                    gen_op_srl();
1903
                gen_movl_T0_reg(rd);
1904
            } else if (xop == 0x27) { /* sra, V9 srax */
1905
                rs1 = GET_FIELD(insn, 13, 17);
1906
                gen_movl_reg_T0(rs1);
1907
                if (IS_IMM) {   /* immediate */
1908
                    rs2 = GET_FIELDs(insn, 20, 31);
1909
                    gen_movl_simm_T1(rs2);
1910
                } else {                /* register */
1911
                    rs2 = GET_FIELD(insn, 27, 31);
1912
                    gen_movl_reg_T1(rs2);
1913
                }
1914
                if (insn & (1 << 12))
1915
                    gen_op_srax();
1916
                else
1917
                    gen_op_sra();
1918
                gen_movl_T0_reg(rd);
1919
#endif
1920
            } else if (xop < 0x36) {
1921
                rs1 = GET_FIELD(insn, 13, 17);
1922
                gen_movl_reg_T0(rs1);
1923
                if (IS_IMM) {   /* immediate */
1924
                    rs2 = GET_FIELDs(insn, 19, 31);
1925
                    gen_movl_simm_T1(rs2);
1926
                } else {                /* register */
1927
                    rs2 = GET_FIELD(insn, 27, 31);
1928
                    gen_movl_reg_T1(rs2);
1929
                }
1930
                if (xop < 0x20) {
1931
                    switch (xop & ~0x10) {
1932
                    case 0x0:
1933
                        if (xop & 0x10)
1934
                            gen_op_add_T1_T0_cc();
1935
                        else
1936
                            gen_op_add_T1_T0();
1937
                        break;
1938
                    case 0x1:
1939
                        gen_op_and_T1_T0();
1940
                        if (xop & 0x10)
1941
                            gen_op_logic_T0_cc();
1942
                        break;
1943
                    case 0x2:
1944
                        gen_op_or_T1_T0();
1945
                        if (xop & 0x10)
1946
                            gen_op_logic_T0_cc();
1947
                        break;
1948
                    case 0x3:
1949
                        gen_op_xor_T1_T0();
1950
                        if (xop & 0x10)
1951
                            gen_op_logic_T0_cc();
1952
                        break;
1953
                    case 0x4:
1954
                        if (xop & 0x10)
1955
                            gen_op_sub_T1_T0_cc();
1956
                        else
1957
                            gen_op_sub_T1_T0();
1958
                        break;
1959
                    case 0x5:
1960
                        gen_op_andn_T1_T0();
1961
                        if (xop & 0x10)
1962
                            gen_op_logic_T0_cc();
1963
                        break;
1964
                    case 0x6:
1965
                        gen_op_orn_T1_T0();
1966
                        if (xop & 0x10)
1967
                            gen_op_logic_T0_cc();
1968
                        break;
1969
                    case 0x7:
1970
                        gen_op_xnor_T1_T0();
1971
                        if (xop & 0x10)
1972
                            gen_op_logic_T0_cc();
1973
                        break;
1974
                    case 0x8:
1975
                        if (xop & 0x10)
1976
                            gen_op_addx_T1_T0_cc();
1977
                        else
1978
                            gen_op_addx_T1_T0();
1979
                        break;
1980
#ifdef TARGET_SPARC64
1981
                    case 0x9: /* V9 mulx */
1982
                        gen_op_mulx_T1_T0();
1983
                        break;
1984
#endif
1985
                    case 0xa:
1986
                        gen_op_umul_T1_T0();
1987
                        if (xop & 0x10)
1988
                            gen_op_logic_T0_cc();
1989
                        break;
1990
                    case 0xb:
1991
                        gen_op_smul_T1_T0();
1992
                        if (xop & 0x10)
1993
                            gen_op_logic_T0_cc();
1994
                        break;
1995
                    case 0xc:
1996
                        if (xop & 0x10)
1997
                            gen_op_subx_T1_T0_cc();
1998
                        else
1999
                            gen_op_subx_T1_T0();
2000
                        break;
2001
#ifdef TARGET_SPARC64
2002
                    case 0xd: /* V9 udivx */
2003
                        gen_op_udivx_T1_T0();
2004
                        break;
2005
#endif
2006
                    case 0xe:
2007
                        gen_op_udiv_T1_T0();
2008
                        if (xop & 0x10)
2009
                            gen_op_div_cc();
2010
                        break;
2011
                    case 0xf:
2012
                        gen_op_sdiv_T1_T0();
2013
                        if (xop & 0x10)
2014
                            gen_op_div_cc();
2015
                        break;
2016
                    default:
2017
                        goto illegal_insn;
2018
                    }
2019
                    gen_movl_T0_reg(rd);
2020
                } else {
2021
                    switch (xop) {
2022
                    case 0x20: /* taddcc */
2023
                        gen_op_tadd_T1_T0_cc();
2024
                        gen_movl_T0_reg(rd);
2025
                        break;
2026
                    case 0x21: /* tsubcc */
2027
                        gen_op_tsub_T1_T0_cc();
2028
                        gen_movl_T0_reg(rd);
2029
                        break;
2030
                    case 0x22: /* taddcctv */
2031
                        save_state(dc);
2032
                        gen_op_tadd_T1_T0_ccTV();
2033
                        gen_movl_T0_reg(rd);
2034
                        break;
2035
                    case 0x23: /* tsubcctv */
2036
                        save_state(dc);
2037
                        gen_op_tsub_T1_T0_ccTV();
2038
                        gen_movl_T0_reg(rd);
2039
                        break;
2040
                    case 0x24: /* mulscc */
2041
                        gen_op_mulscc_T1_T0();
2042
                        gen_movl_T0_reg(rd);
2043
                        break;
2044
#ifndef TARGET_SPARC64
2045
                    case 0x25:  /* sll */
2046
                        gen_op_sll();
2047
                        gen_movl_T0_reg(rd);
2048
                        break;
2049
                    case 0x26:  /* srl */
2050
                        gen_op_srl();
2051
                        gen_movl_T0_reg(rd);
2052
                        break;
2053
                    case 0x27:  /* sra */
2054
                        gen_op_sra();
2055
                        gen_movl_T0_reg(rd);
2056
                        break;
2057
#endif
2058
                    case 0x30:
2059
                        {
2060
                            switch(rd) {
2061
                            case 0: /* wry */
2062
                                gen_op_xor_T1_T0();
2063
                                gen_op_movtl_env_T0(offsetof(CPUSPARCState, y));
2064
                                break;
2065
#ifndef TARGET_SPARC64
2066
                            case 0x01 ... 0x0f: /* undefined in the
2067
                                                   SPARCv8 manual, nop
2068
                                                   on the microSPARC
2069
                                                   II */
2070
                            case 0x10 ... 0x1f: /* implementation-dependent
2071
                                                   in the SPARCv8
2072
                                                   manual, nop on the
2073
                                                   microSPARC II */
2074
                                break;
2075
#else
2076
                            case 0x2: /* V9 wrccr */
2077
                                gen_op_xor_T1_T0();
2078
                                gen_op_wrccr();
2079
                                break;
2080
                            case 0x3: /* V9 wrasi */
2081
                                gen_op_xor_T1_T0();
2082
                                gen_op_movl_env_T0(offsetof(CPUSPARCState, asi));
2083
                                break;
2084
                            case 0x6: /* V9 wrfprs */
2085
                                gen_op_xor_T1_T0();
2086
                                gen_op_movl_env_T0(offsetof(CPUSPARCState, fprs));
2087
                                save_state(dc);
2088
                                gen_op_next_insn();
2089
                                gen_op_movl_T0_0();
2090
                                gen_op_exit_tb();
2091
                                dc->is_br = 1;
2092
                                break;
2093
                            case 0xf: /* V9 sir, nop if user */
2094
#if !defined(CONFIG_USER_ONLY)
2095
                                if (supervisor(dc))
2096
                                    gen_op_sir();
2097
#endif
2098
                                break;
2099
                            case 0x13: /* Graphics Status */
2100
                                if (gen_trap_ifnofpu(dc))
2101
                                    goto jmp_insn;
2102
                                gen_op_xor_T1_T0();
2103
                                gen_op_movtl_env_T0(offsetof(CPUSPARCState, gsr));
2104
                                break;
2105
                            case 0x17: /* Tick compare */
2106
#if !defined(CONFIG_USER_ONLY)
2107
                                if (!supervisor(dc))
2108
                                    goto illegal_insn;
2109
#endif
2110
                                gen_op_xor_T1_T0();
2111
                                gen_op_movtl_env_T0(offsetof(CPUSPARCState, tick_cmpr));
2112
                                gen_op_wrtick_cmpr();
2113
                                break;
2114
                            case 0x18: /* System tick */
2115
#if !defined(CONFIG_USER_ONLY)
2116
                                if (!supervisor(dc))
2117
                                    goto illegal_insn;
2118
#endif
2119
                                gen_op_xor_T1_T0();
2120
                                gen_op_wrstick();
2121
                                break;
2122
                            case 0x19: /* System tick compare */
2123
#if !defined(CONFIG_USER_ONLY)
2124
                                if (!supervisor(dc))
2125
                                    goto illegal_insn;
2126
#endif
2127
                                gen_op_xor_T1_T0();
2128
                                gen_op_movtl_env_T0(offsetof(CPUSPARCState, stick_cmpr));
2129
                                gen_op_wrstick_cmpr();
2130
                                break;
2131

    
2132
                            case 0x10: /* Performance Control */
2133
                            case 0x11: /* Performance Instrumentation Counter */
2134
                            case 0x12: /* Dispatch Control */
2135
                            case 0x14: /* Softint set */
2136
                            case 0x15: /* Softint clear */
2137
                            case 0x16: /* Softint write */
2138
#endif
2139
                            default:
2140
                                goto illegal_insn;
2141
                            }
2142
                        }
2143
                        break;
2144
#if !defined(CONFIG_USER_ONLY)
2145
                    case 0x31: /* wrpsr, V9 saved, restored */
2146
                        {
2147
                            if (!supervisor(dc))
2148
                                goto priv_insn;
2149
#ifdef TARGET_SPARC64
2150
                            switch (rd) {
2151
                            case 0:
2152
                                gen_op_saved();
2153
                                break;
2154
                            case 1:
2155
                                gen_op_restored();
2156
                                break;
2157
                            case 2: /* UA2005 allclean */
2158
                            case 3: /* UA2005 otherw */
2159
                            case 4: /* UA2005 normalw */
2160
                            case 5: /* UA2005 invalw */
2161
                                // XXX
2162
                            default:
2163
                                goto illegal_insn;
2164
                            }
2165
#else
2166
                            gen_op_xor_T1_T0();
2167
                            gen_op_wrpsr();
2168
                            save_state(dc);
2169
                            gen_op_next_insn();
2170
                            gen_op_movl_T0_0();
2171
                            gen_op_exit_tb();
2172
                            dc->is_br = 1;
2173
#endif
2174
                        }
2175
                        break;
2176
                    case 0x32: /* wrwim, V9 wrpr */
2177
                        {
2178
                            if (!supervisor(dc))
2179
                                goto priv_insn;
2180
                            gen_op_xor_T1_T0();
2181
#ifdef TARGET_SPARC64
2182
                            switch (rd) {
2183
                            case 0: // tpc
2184
                                gen_op_wrtpc();
2185
                                break;
2186
                            case 1: // tnpc
2187
                                gen_op_wrtnpc();
2188
                                break;
2189
                            case 2: // tstate
2190
                                gen_op_wrtstate();
2191
                                break;
2192
                            case 3: // tt
2193
                                gen_op_wrtt();
2194
                                break;
2195
                            case 4: // tick
2196
                                gen_op_wrtick();
2197
                                break;
2198
                            case 5: // tba
2199
                                gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
2200
                                break;
2201
                            case 6: // pstate
2202
                                gen_op_wrpstate();
2203
                                save_state(dc);
2204
                                gen_op_next_insn();
2205
                                gen_op_movl_T0_0();
2206
                                gen_op_exit_tb();
2207
                                dc->is_br = 1;
2208
                                break;
2209
                            case 7: // tl
2210
                                gen_op_movl_env_T0(offsetof(CPUSPARCState, tl));
2211
                                break;
2212
                            case 8: // pil
2213
                                gen_op_movl_env_T0(offsetof(CPUSPARCState, psrpil));
2214
                                break;
2215
                            case 9: // cwp
2216
                                gen_op_wrcwp();
2217
                                break;
2218
                            case 10: // cansave
2219
                                gen_op_movl_env_T0(offsetof(CPUSPARCState, cansave));
2220
                                break;
2221
                            case 11: // canrestore
2222
                                gen_op_movl_env_T0(offsetof(CPUSPARCState, canrestore));
2223
                                break;
2224
                            case 12: // cleanwin
2225
                                gen_op_movl_env_T0(offsetof(CPUSPARCState, cleanwin));
2226
                                break;
2227
                            case 13: // otherwin
2228
                                gen_op_movl_env_T0(offsetof(CPUSPARCState, otherwin));
2229
                                break;
2230
                            case 14: // wstate
2231
                                gen_op_movl_env_T0(offsetof(CPUSPARCState, wstate));
2232
                                break;
2233
                            case 16: // UA2005 gl
2234
                                gen_op_movl_env_T0(offsetof(CPUSPARCState, gl));
2235
                                break;
2236
                            case 26: // UA2005 strand status
2237
                                if (!hypervisor(dc))
2238
                                    goto priv_insn;
2239
                                gen_op_movl_env_T0(offsetof(CPUSPARCState, ssr));
2240
                                break;
2241
                            default:
2242
                                goto illegal_insn;
2243
                            }
2244
#else
2245
                            gen_op_wrwim();
2246
#endif
2247
                        }
2248
                        break;
2249
                    case 0x33: /* wrtbr, UA2005 wrhpr */
2250
                        {
2251
#ifndef TARGET_SPARC64
2252
                            if (!supervisor(dc))
2253
                                goto priv_insn;
2254
                            gen_op_xor_T1_T0();
2255
                            gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
2256
#else
2257
                            if (!hypervisor(dc))
2258
                                goto priv_insn;
2259
                            gen_op_xor_T1_T0();
2260
                            switch (rd) {
2261
                            case 0: // hpstate
2262
                                // XXX gen_op_wrhpstate();
2263
                                save_state(dc);
2264
                                gen_op_next_insn();
2265
                                gen_op_movl_T0_0();
2266
                                gen_op_exit_tb();
2267
                                dc->is_br = 1;
2268
                                break;
2269
                            case 1: // htstate
2270
                                // XXX gen_op_wrhtstate();
2271
                                break;
2272
                            case 3: // hintp
2273
                                gen_op_movl_env_T0(offsetof(CPUSPARCState, hintp));
2274
                                break;
2275
                            case 5: // htba
2276
                                gen_op_movl_env_T0(offsetof(CPUSPARCState, htba));
2277
                                break;
2278
                            case 31: // hstick_cmpr
2279
                                gen_op_movtl_env_T0(offsetof(CPUSPARCState, hstick_cmpr));
2280
                                gen_op_wrhstick_cmpr();
2281
                                break;
2282
                            case 6: // hver readonly
2283
                            default:
2284
                                goto illegal_insn;
2285
                            }
2286
#endif
2287
                        }
2288
                        break;
2289
#endif
2290
#ifdef TARGET_SPARC64
2291
                    case 0x2c: /* V9 movcc */
2292
                        {
2293
                            int cc = GET_FIELD_SP(insn, 11, 12);
2294
                            int cond = GET_FIELD_SP(insn, 14, 17);
2295
                            if (IS_IMM) {       /* immediate */
2296
                                rs2 = GET_FIELD_SPs(insn, 0, 10);
2297
                                gen_movl_simm_T1(rs2);
2298
                            }
2299
                            else {
2300
                                rs2 = GET_FIELD_SP(insn, 0, 4);
2301
                                gen_movl_reg_T1(rs2);
2302
                            }
2303
                            gen_movl_reg_T0(rd);
2304
                            flush_T2(dc);
2305
                            if (insn & (1 << 18)) {
2306
                                if (cc == 0)
2307
                                    gen_cond[0][cond]();
2308
                                else if (cc == 2)
2309
                                    gen_cond[1][cond]();
2310
                                else
2311
                                    goto illegal_insn;
2312
                            } else {
2313
                                gen_fcond[cc][cond]();
2314
                            }
2315
                            gen_op_mov_cc();
2316
                            gen_movl_T0_reg(rd);
2317
                            break;
2318
                        }
2319
                    case 0x2d: /* V9 sdivx */
2320
                        gen_op_sdivx_T1_T0();
2321
                        gen_movl_T0_reg(rd);
2322
                        break;
2323
                    case 0x2e: /* V9 popc */
2324
                        {
2325
                            if (IS_IMM) {       /* immediate */
2326
                                rs2 = GET_FIELD_SPs(insn, 0, 12);
2327
                                gen_movl_simm_T1(rs2);
2328
                                // XXX optimize: popc(constant)
2329
                            }
2330
                            else {
2331
                                rs2 = GET_FIELD_SP(insn, 0, 4);
2332
                                gen_movl_reg_T1(rs2);
2333
                            }
2334
                            gen_op_popc();
2335
                            gen_movl_T0_reg(rd);
2336
                        }
2337
                    case 0x2f: /* V9 movr */
2338
                        {
2339
                            int cond = GET_FIELD_SP(insn, 10, 12);
2340
                            rs1 = GET_FIELD(insn, 13, 17);
2341
                            flush_T2(dc);
2342
                            gen_movl_reg_T0(rs1);
2343
                            gen_cond_reg(cond);
2344
                            if (IS_IMM) {       /* immediate */
2345
                                rs2 = GET_FIELD_SPs(insn, 0, 9);
2346
                                gen_movl_simm_T1(rs2);
2347
                            }
2348
                            else {
2349
                                rs2 = GET_FIELD_SP(insn, 0, 4);
2350
                                gen_movl_reg_T1(rs2);
2351
                            }
2352
                            gen_movl_reg_T0(rd);
2353
                            gen_op_mov_cc();
2354
                            gen_movl_T0_reg(rd);
2355
                            break;
2356
                        }
2357
#endif
2358
                    default:
2359
                        goto illegal_insn;
2360
                    }
2361
                }
2362
            } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
2363
#ifdef TARGET_SPARC64
2364
                int opf = GET_FIELD_SP(insn, 5, 13);
2365
                rs1 = GET_FIELD(insn, 13, 17);
2366
                rs2 = GET_FIELD(insn, 27, 31);
2367
                if (gen_trap_ifnofpu(dc))
2368
                    goto jmp_insn;
2369

    
2370
                switch (opf) {
2371
                case 0x000: /* VIS I edge8cc */
2372
                case 0x001: /* VIS II edge8n */
2373
                case 0x002: /* VIS I edge8lcc */
2374
                case 0x003: /* VIS II edge8ln */
2375
                case 0x004: /* VIS I edge16cc */
2376
                case 0x005: /* VIS II edge16n */
2377
                case 0x006: /* VIS I edge16lcc */
2378
                case 0x007: /* VIS II edge16ln */
2379
                case 0x008: /* VIS I edge32cc */
2380
                case 0x009: /* VIS II edge32n */
2381
                case 0x00a: /* VIS I edge32lcc */
2382
                case 0x00b: /* VIS II edge32ln */
2383
                    // XXX
2384
                    goto illegal_insn;
2385
                case 0x010: /* VIS I array8 */
2386
                    gen_movl_reg_T0(rs1);
2387
                    gen_movl_reg_T1(rs2);
2388
                    gen_op_array8();
2389
                    gen_movl_T0_reg(rd);
2390
                    break;
2391
                case 0x012: /* VIS I array16 */
2392
                    gen_movl_reg_T0(rs1);
2393
                    gen_movl_reg_T1(rs2);
2394
                    gen_op_array16();
2395
                    gen_movl_T0_reg(rd);
2396
                    break;
2397
                case 0x014: /* VIS I array32 */
2398
                    gen_movl_reg_T0(rs1);
2399
                    gen_movl_reg_T1(rs2);
2400
                    gen_op_array32();
2401
                    gen_movl_T0_reg(rd);
2402
                    break;
2403
                case 0x018: /* VIS I alignaddr */
2404
                    gen_movl_reg_T0(rs1);
2405
                    gen_movl_reg_T1(rs2);
2406
                    gen_op_alignaddr();
2407
                    gen_movl_T0_reg(rd);
2408
                    break;
2409
                case 0x019: /* VIS II bmask */
2410
                case 0x01a: /* VIS I alignaddrl */
2411
                    // XXX
2412
                    goto illegal_insn;
2413
                case 0x020: /* VIS I fcmple16 */
2414
                    gen_op_load_fpr_DT0(rs1);
2415
                    gen_op_load_fpr_DT1(rs2);
2416
                    gen_op_fcmple16();
2417
                    gen_op_store_DT0_fpr(rd);
2418
                    break;
2419
                case 0x022: /* VIS I fcmpne16 */
2420
                    gen_op_load_fpr_DT0(rs1);
2421
                    gen_op_load_fpr_DT1(rs2);
2422
                    gen_op_fcmpne16();
2423
                    gen_op_store_DT0_fpr(rd);
2424
                    break;
2425
                case 0x024: /* VIS I fcmple32 */
2426
                    gen_op_load_fpr_DT0(rs1);
2427
                    gen_op_load_fpr_DT1(rs2);
2428
                    gen_op_fcmple32();
2429
                    gen_op_store_DT0_fpr(rd);
2430
                    break;
2431
                case 0x026: /* VIS I fcmpne32 */
2432
                    gen_op_load_fpr_DT0(rs1);
2433
                    gen_op_load_fpr_DT1(rs2);
2434
                    gen_op_fcmpne32();
2435
                    gen_op_store_DT0_fpr(rd);
2436
                    break;
2437
                case 0x028: /* VIS I fcmpgt16 */
2438
                    gen_op_load_fpr_DT0(rs1);
2439
                    gen_op_load_fpr_DT1(rs2);
2440
                    gen_op_fcmpgt16();
2441
                    gen_op_store_DT0_fpr(rd);
2442
                    break;
2443
                case 0x02a: /* VIS I fcmpeq16 */
2444
                    gen_op_load_fpr_DT0(rs1);
2445
                    gen_op_load_fpr_DT1(rs2);
2446
                    gen_op_fcmpeq16();
2447
                    gen_op_store_DT0_fpr(rd);
2448
                    break;
2449
                case 0x02c: /* VIS I fcmpgt32 */
2450
                    gen_op_load_fpr_DT0(rs1);
2451
                    gen_op_load_fpr_DT1(rs2);
2452
                    gen_op_fcmpgt32();
2453
                    gen_op_store_DT0_fpr(rd);
2454
                    break;
2455
                case 0x02e: /* VIS I fcmpeq32 */
2456
                    gen_op_load_fpr_DT0(rs1);
2457
                    gen_op_load_fpr_DT1(rs2);
2458
                    gen_op_fcmpeq32();
2459
                    gen_op_store_DT0_fpr(rd);
2460
                    break;
2461
                case 0x031: /* VIS I fmul8x16 */
2462
                    gen_op_load_fpr_DT0(rs1);
2463
                    gen_op_load_fpr_DT1(rs2);
2464
                    gen_op_fmul8x16();
2465
                    gen_op_store_DT0_fpr(rd);
2466
                    break;
2467
                case 0x033: /* VIS I fmul8x16au */
2468
                    gen_op_load_fpr_DT0(rs1);
2469
                    gen_op_load_fpr_DT1(rs2);
2470
                    gen_op_fmul8x16au();
2471
                    gen_op_store_DT0_fpr(rd);
2472
                    break;
2473
                case 0x035: /* VIS I fmul8x16al */
2474
                    gen_op_load_fpr_DT0(rs1);
2475
                    gen_op_load_fpr_DT1(rs2);
2476
                    gen_op_fmul8x16al();
2477
                    gen_op_store_DT0_fpr(rd);
2478
                    break;
2479
                case 0x036: /* VIS I fmul8sux16 */
2480
                    gen_op_load_fpr_DT0(rs1);
2481
                    gen_op_load_fpr_DT1(rs2);
2482
                    gen_op_fmul8sux16();
2483
                    gen_op_store_DT0_fpr(rd);
2484
                    break;
2485
                case 0x037: /* VIS I fmul8ulx16 */
2486
                    gen_op_load_fpr_DT0(rs1);
2487
                    gen_op_load_fpr_DT1(rs2);
2488
                    gen_op_fmul8ulx16();
2489
                    gen_op_store_DT0_fpr(rd);
2490
                    break;
2491
                case 0x038: /* VIS I fmuld8sux16 */
2492
                    gen_op_load_fpr_DT0(rs1);
2493
                    gen_op_load_fpr_DT1(rs2);
2494
                    gen_op_fmuld8sux16();
2495
                    gen_op_store_DT0_fpr(rd);
2496
                    break;
2497
                case 0x039: /* VIS I fmuld8ulx16 */
2498
                    gen_op_load_fpr_DT0(rs1);
2499
                    gen_op_load_fpr_DT1(rs2);
2500
                    gen_op_fmuld8ulx16();
2501
                    gen_op_store_DT0_fpr(rd);
2502
                    break;
2503
                case 0x03a: /* VIS I fpack32 */
2504
                case 0x03b: /* VIS I fpack16 */
2505
                case 0x03d: /* VIS I fpackfix */
2506
                case 0x03e: /* VIS I pdist */
2507
                    // XXX
2508
                    goto illegal_insn;
2509
                case 0x048: /* VIS I faligndata */
2510
                    gen_op_load_fpr_DT0(rs1);
2511
                    gen_op_load_fpr_DT1(rs2);
2512
                    gen_op_faligndata();
2513
                    gen_op_store_DT0_fpr(rd);
2514
                    break;
2515
                case 0x04b: /* VIS I fpmerge */
2516
                    gen_op_load_fpr_DT0(rs1);
2517
                    gen_op_load_fpr_DT1(rs2);
2518
                    gen_op_fpmerge();
2519
                    gen_op_store_DT0_fpr(rd);
2520
                    break;
2521
                case 0x04c: /* VIS II bshuffle */
2522
                    // XXX
2523
                    goto illegal_insn;
2524
                case 0x04d: /* VIS I fexpand */
2525
                    gen_op_load_fpr_DT0(rs1);
2526
                    gen_op_load_fpr_DT1(rs2);
2527
                    gen_op_fexpand();
2528
                    gen_op_store_DT0_fpr(rd);
2529
                    break;
2530
                case 0x050: /* VIS I fpadd16 */
2531
                    gen_op_load_fpr_DT0(rs1);
2532
                    gen_op_load_fpr_DT1(rs2);
2533
                    gen_op_fpadd16();
2534
                    gen_op_store_DT0_fpr(rd);
2535
                    break;
2536
                case 0x051: /* VIS I fpadd16s */
2537
                    gen_op_load_fpr_FT0(rs1);
2538
                    gen_op_load_fpr_FT1(rs2);
2539
                    gen_op_fpadd16s();
2540
                    gen_op_store_FT0_fpr(rd);
2541
                    break;
2542
                case 0x052: /* VIS I fpadd32 */
2543
                    gen_op_load_fpr_DT0(rs1);
2544
                    gen_op_load_fpr_DT1(rs2);
2545
                    gen_op_fpadd32();
2546
                    gen_op_store_DT0_fpr(rd);
2547
                    break;
2548
                case 0x053: /* VIS I fpadd32s */
2549
                    gen_op_load_fpr_FT0(rs1);
2550
                    gen_op_load_fpr_FT1(rs2);
2551
                    gen_op_fpadd32s();
2552
                    gen_op_store_FT0_fpr(rd);
2553
                    break;
2554
                case 0x054: /* VIS I fpsub16 */
2555
                    gen_op_load_fpr_DT0(rs1);
2556
                    gen_op_load_fpr_DT1(rs2);
2557
                    gen_op_fpsub16();
2558
                    gen_op_store_DT0_fpr(rd);
2559
                    break;
2560
                case 0x055: /* VIS I fpsub16s */
2561
                    gen_op_load_fpr_FT0(rs1);
2562
                    gen_op_load_fpr_FT1(rs2);
2563
                    gen_op_fpsub16s();
2564
                    gen_op_store_FT0_fpr(rd);
2565
                    break;
2566
                case 0x056: /* VIS I fpsub32 */
2567
                    gen_op_load_fpr_DT0(rs1);
2568
                    gen_op_load_fpr_DT1(rs2);
2569
                    gen_op_fpadd32();
2570
                    gen_op_store_DT0_fpr(rd);
2571
                    break;
2572
                case 0x057: /* VIS I fpsub32s */
2573
                    gen_op_load_fpr_FT0(rs1);
2574
                    gen_op_load_fpr_FT1(rs2);
2575
                    gen_op_fpsub32s();
2576
                    gen_op_store_FT0_fpr(rd);
2577
                    break;
2578
                case 0x060: /* VIS I fzero */
2579
                    gen_op_movl_DT0_0();
2580
                    gen_op_store_DT0_fpr(rd);
2581
                    break;
2582
                case 0x061: /* VIS I fzeros */
2583
                    gen_op_movl_FT0_0();
2584
                    gen_op_store_FT0_fpr(rd);
2585
                    break;
2586
                case 0x062: /* VIS I fnor */
2587
                    gen_op_load_fpr_DT0(rs1);
2588
                    gen_op_load_fpr_DT1(rs2);
2589
                    gen_op_fnor();
2590
                    gen_op_store_DT0_fpr(rd);
2591
                    break;
2592
                case 0x063: /* VIS I fnors */
2593
                    gen_op_load_fpr_FT0(rs1);
2594
                    gen_op_load_fpr_FT1(rs2);
2595
                    gen_op_fnors();
2596
                    gen_op_store_FT0_fpr(rd);
2597
                    break;
2598
                case 0x064: /* VIS I fandnot2 */
2599
                    gen_op_load_fpr_DT1(rs1);
2600
                    gen_op_load_fpr_DT0(rs2);
2601
                    gen_op_fandnot();
2602
                    gen_op_store_DT0_fpr(rd);
2603
                    break;
2604
                case 0x065: /* VIS I fandnot2s */
2605
                    gen_op_load_fpr_FT1(rs1);
2606
                    gen_op_load_fpr_FT0(rs2);
2607
                    gen_op_fandnots();
2608
                    gen_op_store_FT0_fpr(rd);
2609
                    break;
2610
                case 0x066: /* VIS I fnot2 */
2611
                    gen_op_load_fpr_DT1(rs2);
2612
                    gen_op_fnot();
2613
                    gen_op_store_DT0_fpr(rd);
2614
                    break;
2615
                case 0x067: /* VIS I fnot2s */
2616
                    gen_op_load_fpr_FT1(rs2);
2617
                    gen_op_fnot();
2618
                    gen_op_store_FT0_fpr(rd);
2619
                    break;
2620
                case 0x068: /* VIS I fandnot1 */
2621
                    gen_op_load_fpr_DT0(rs1);
2622
                    gen_op_load_fpr_DT1(rs2);
2623
                    gen_op_fandnot();
2624
                    gen_op_store_DT0_fpr(rd);
2625
                    break;
2626
                case 0x069: /* VIS I fandnot1s */
2627
                    gen_op_load_fpr_FT0(rs1);
2628
                    gen_op_load_fpr_FT1(rs2);
2629
                    gen_op_fandnots();
2630
                    gen_op_store_FT0_fpr(rd);
2631
                    break;
2632
                case 0x06a: /* VIS I fnot1 */
2633
                    gen_op_load_fpr_DT1(rs1);
2634
                    gen_op_fnot();
2635
                    gen_op_store_DT0_fpr(rd);
2636
                    break;
2637
                case 0x06b: /* VIS I fnot1s */
2638
                    gen_op_load_fpr_FT1(rs1);
2639
                    gen_op_fnot();
2640
                    gen_op_store_FT0_fpr(rd);
2641
                    break;
2642
                case 0x06c: /* VIS I fxor */
2643
                    gen_op_load_fpr_DT0(rs1);
2644
                    gen_op_load_fpr_DT1(rs2);
2645
                    gen_op_fxor();
2646
                    gen_op_store_DT0_fpr(rd);
2647
                    break;
2648
                case 0x06d: /* VIS I fxors */
2649
                    gen_op_load_fpr_FT0(rs1);
2650
                    gen_op_load_fpr_FT1(rs2);
2651
                    gen_op_fxors();
2652
                    gen_op_store_FT0_fpr(rd);
2653
                    break;
2654
                case 0x06e: /* VIS I fnand */
2655
                    gen_op_load_fpr_DT0(rs1);
2656
                    gen_op_load_fpr_DT1(rs2);
2657
                    gen_op_fnand();
2658
                    gen_op_store_DT0_fpr(rd);
2659
                    break;
2660
                case 0x06f: /* VIS I fnands */
2661
                    gen_op_load_fpr_FT0(rs1);
2662
                    gen_op_load_fpr_FT1(rs2);
2663
                    gen_op_fnands();
2664
                    gen_op_store_FT0_fpr(rd);
2665
                    break;
2666
                case 0x070: /* VIS I fand */
2667
                    gen_op_load_fpr_DT0(rs1);
2668
                    gen_op_load_fpr_DT1(rs2);
2669
                    gen_op_fand();
2670
                    gen_op_store_DT0_fpr(rd);
2671
                    break;
2672
                case 0x071: /* VIS I fands */
2673
                    gen_op_load_fpr_FT0(rs1);
2674
                    gen_op_load_fpr_FT1(rs2);
2675
                    gen_op_fands();
2676
                    gen_op_store_FT0_fpr(rd);
2677
                    break;
2678
                case 0x072: /* VIS I fxnor */
2679
                    gen_op_load_fpr_DT0(rs1);
2680
                    gen_op_load_fpr_DT1(rs2);
2681
                    gen_op_fxnor();
2682
                    gen_op_store_DT0_fpr(rd);
2683
                    break;
2684
                case 0x073: /* VIS I fxnors */
2685
                    gen_op_load_fpr_FT0(rs1);
2686
                    gen_op_load_fpr_FT1(rs2);
2687
                    gen_op_fxnors();
2688
                    gen_op_store_FT0_fpr(rd);
2689
                    break;
2690
                case 0x074: /* VIS I fsrc1 */
2691
                    gen_op_load_fpr_DT0(rs1);
2692
                    gen_op_store_DT0_fpr(rd);
2693
                    break;
2694
                case 0x075: /* VIS I fsrc1s */
2695
                    gen_op_load_fpr_FT0(rs1);
2696
                    gen_op_store_FT0_fpr(rd);
2697
                    break;
2698
                case 0x076: /* VIS I fornot2 */
2699
                    gen_op_load_fpr_DT1(rs1);
2700
                    gen_op_load_fpr_DT0(rs2);
2701
                    gen_op_fornot();
2702
                    gen_op_store_DT0_fpr(rd);
2703
                    break;
2704
                case 0x077: /* VIS I fornot2s */
2705
                    gen_op_load_fpr_FT1(rs1);
2706
                    gen_op_load_fpr_FT0(rs2);
2707
                    gen_op_fornots();
2708
                    gen_op_store_FT0_fpr(rd);
2709
                    break;
2710
                case 0x078: /* VIS I fsrc2 */
2711
                    gen_op_load_fpr_DT0(rs2);
2712
                    gen_op_store_DT0_fpr(rd);
2713
                    break;
2714
                case 0x079: /* VIS I fsrc2s */
2715
                    gen_op_load_fpr_FT0(rs2);
2716
                    gen_op_store_FT0_fpr(rd);
2717
                    break;
2718
                case 0x07a: /* VIS I fornot1 */
2719
                    gen_op_load_fpr_DT0(rs1);
2720
                    gen_op_load_fpr_DT1(rs2);
2721
                    gen_op_fornot();
2722
                    gen_op_store_DT0_fpr(rd);
2723
                    break;
2724
                case 0x07b: /* VIS I fornot1s */
2725
                    gen_op_load_fpr_FT0(rs1);
2726
                    gen_op_load_fpr_FT1(rs2);
2727
                    gen_op_fornots();
2728
                    gen_op_store_FT0_fpr(rd);
2729
                    break;
2730
                case 0x07c: /* VIS I for */
2731
                    gen_op_load_fpr_DT0(rs1);
2732
                    gen_op_load_fpr_DT1(rs2);
2733
                    gen_op_for();
2734
                    gen_op_store_DT0_fpr(rd);
2735
                    break;
2736
                case 0x07d: /* VIS I fors */
2737
                    gen_op_load_fpr_FT0(rs1);
2738
                    gen_op_load_fpr_FT1(rs2);
2739
                    gen_op_fors();
2740
                    gen_op_store_FT0_fpr(rd);
2741
                    break;
2742
                case 0x07e: /* VIS I fone */
2743
                    gen_op_movl_DT0_1();
2744
                    gen_op_store_DT0_fpr(rd);
2745
                    break;
2746
                case 0x07f: /* VIS I fones */
2747
                    gen_op_movl_FT0_1();
2748
                    gen_op_store_FT0_fpr(rd);
2749
                    break;
2750
                case 0x080: /* VIS I shutdown */
2751
                case 0x081: /* VIS II siam */
2752
                    // XXX
2753
                    goto illegal_insn;
2754
                default:
2755
                    goto illegal_insn;
2756
                }
2757
#else
2758
                goto ncp_insn;
2759
#endif
2760
            } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
2761
#ifdef TARGET_SPARC64
2762
                goto illegal_insn;
2763
#else
2764
                goto ncp_insn;
2765
#endif
2766
#ifdef TARGET_SPARC64
2767
            } else if (xop == 0x39) { /* V9 return */
2768
                rs1 = GET_FIELD(insn, 13, 17);
2769
                save_state(dc);
2770
                gen_movl_reg_T0(rs1);
2771
                if (IS_IMM) {   /* immediate */
2772
                    rs2 = GET_FIELDs(insn, 19, 31);
2773
#if defined(OPTIM)
2774
                    if (rs2) {
2775
#endif
2776
                        gen_movl_simm_T1(rs2);
2777
                        gen_op_add_T1_T0();
2778
#if defined(OPTIM)
2779
                    }
2780
#endif
2781
                } else {                /* register */
2782
                    rs2 = GET_FIELD(insn, 27, 31);
2783
#if defined(OPTIM)
2784
                    if (rs2) {
2785
#endif
2786
                        gen_movl_reg_T1(rs2);
2787
                        gen_op_add_T1_T0();
2788
#if defined(OPTIM)
2789
                    }
2790
#endif
2791
                }
2792
                gen_op_restore();
2793
                gen_mov_pc_npc(dc);
2794
                gen_op_check_align_T0_3();
2795
                gen_op_movl_npc_T0();
2796
                dc->npc = DYNAMIC_PC;
2797
                goto jmp_insn;
2798
#endif
2799
            } else {
2800
                rs1 = GET_FIELD(insn, 13, 17);
2801
                gen_movl_reg_T0(rs1);
2802
                if (IS_IMM) {   /* immediate */
2803
                    rs2 = GET_FIELDs(insn, 19, 31);
2804
#if defined(OPTIM)
2805
                    if (rs2) {
2806
#endif
2807
                        gen_movl_simm_T1(rs2);
2808
                        gen_op_add_T1_T0();
2809
#if defined(OPTIM)
2810
                    }
2811
#endif
2812
                } else {                /* register */
2813
                    rs2 = GET_FIELD(insn, 27, 31);
2814
#if defined(OPTIM)
2815
                    if (rs2) {
2816
#endif
2817
                        gen_movl_reg_T1(rs2);
2818
                        gen_op_add_T1_T0();
2819
#if defined(OPTIM)
2820
                    }
2821
#endif
2822
                }
2823
                switch (xop) {
2824
                case 0x38:      /* jmpl */
2825
                    {
2826
                        if (rd != 0) {
2827
#ifdef TARGET_SPARC64
2828
                            if (dc->pc == (uint32_t)dc->pc) {
2829
                                gen_op_movl_T1_im(dc->pc);
2830
                            } else {
2831
                                gen_op_movq_T1_im64(dc->pc >> 32, dc->pc);
2832
                            }
2833
#else
2834
                            gen_op_movl_T1_im(dc->pc);
2835
#endif
2836
                            gen_movl_T1_reg(rd);
2837
                        }
2838
                        gen_mov_pc_npc(dc);
2839
                        gen_op_check_align_T0_3();
2840
                        gen_op_movl_npc_T0();
2841
                        dc->npc = DYNAMIC_PC;
2842
                    }
2843
                    goto jmp_insn;
2844
#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
2845
                case 0x39:      /* rett, V9 return */
2846
                    {
2847
                        if (!supervisor(dc))
2848
                            goto priv_insn;
2849
                        gen_mov_pc_npc(dc);
2850
                        gen_op_check_align_T0_3();
2851
                        gen_op_movl_npc_T0();
2852
                        dc->npc = DYNAMIC_PC;
2853
                        gen_op_rett();
2854
                    }
2855
                    goto jmp_insn;
2856
#endif
2857
                case 0x3b: /* flush */
2858
                    gen_op_flush_T0();
2859
                    break;
2860
                case 0x3c:      /* save */
2861
                    save_state(dc);
2862
                    gen_op_save();
2863
                    gen_movl_T0_reg(rd);
2864
                    break;
2865
                case 0x3d:      /* restore */
2866
                    save_state(dc);
2867
                    gen_op_restore();
2868
                    gen_movl_T0_reg(rd);
2869
                    break;
2870
#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
2871
                case 0x3e:      /* V9 done/retry */
2872
                    {
2873
                        switch (rd) {
2874
                        case 0:
2875
                            if (!supervisor(dc))
2876
                                goto priv_insn;
2877
                            dc->npc = DYNAMIC_PC;
2878
                            dc->pc = DYNAMIC_PC;
2879
                            gen_op_done();
2880
                            goto jmp_insn;
2881
                        case 1:
2882
                            if (!supervisor(dc))
2883
                                goto priv_insn;
2884
                            dc->npc = DYNAMIC_PC;
2885
                            dc->pc = DYNAMIC_PC;
2886
                            gen_op_retry();
2887
                            goto jmp_insn;
2888
                        default:
2889
                            goto illegal_insn;
2890
                        }
2891
                    }
2892
                    break;
2893
#endif
2894
                default:
2895
                    goto illegal_insn;
2896
                }
2897
            }
2898
            break;
2899
        }
2900
        break;
2901
    case 3:                     /* load/store instructions */
2902
        {
2903
            unsigned int xop = GET_FIELD(insn, 7, 12);
2904
            rs1 = GET_FIELD(insn, 13, 17);
2905
            save_state(dc);
2906
            gen_movl_reg_T0(rs1);
2907
            if (xop == 0x3c || xop == 0x3e)
2908
            {
2909
                rs2 = GET_FIELD(insn, 27, 31);
2910
                gen_movl_reg_T1(rs2);
2911
            }
2912
            else if (IS_IMM) {       /* immediate */
2913
                rs2 = GET_FIELDs(insn, 19, 31);
2914
#if defined(OPTIM)
2915
                if (rs2 != 0) {
2916
#endif
2917
                    gen_movl_simm_T1(rs2);
2918
                    gen_op_add_T1_T0();
2919
#if defined(OPTIM)
2920
                }
2921
#endif
2922
            } else {            /* register */
2923
                rs2 = GET_FIELD(insn, 27, 31);
2924
#if defined(OPTIM)
2925
                if (rs2 != 0) {
2926
#endif
2927
                    gen_movl_reg_T1(rs2);
2928
                    gen_op_add_T1_T0();
2929
#if defined(OPTIM)
2930
                }
2931
#endif
2932
            }
2933
            if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
2934
                (xop > 0x17 && xop <= 0x1d ) ||
2935
                (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
2936
                switch (xop) {
2937
                case 0x0:       /* load word */
2938
                    gen_op_check_align_T0_3();
2939
#ifndef TARGET_SPARC64
2940
                    gen_op_ldst(ld);
2941
#else
2942
                    gen_op_ldst(lduw);
2943
#endif
2944
                    break;
2945
                case 0x1:       /* load unsigned byte */
2946
                    gen_op_ldst(ldub);
2947
                    break;
2948
                case 0x2:       /* load unsigned halfword */
2949
                    gen_op_check_align_T0_1();
2950
                    gen_op_ldst(lduh);
2951
                    break;
2952
                case 0x3:       /* load double word */
2953
                    if (rd & 1)
2954
                        goto illegal_insn;
2955
                    gen_op_check_align_T0_7();
2956
                    gen_op_ldst(ldd);
2957
                    gen_movl_T0_reg(rd + 1);
2958
                    break;
2959
                case 0x9:       /* load signed byte */
2960
                    gen_op_ldst(ldsb);
2961
                    break;
2962
                case 0xa:       /* load signed halfword */
2963
                    gen_op_check_align_T0_1();
2964
                    gen_op_ldst(ldsh);
2965
                    break;
2966
                case 0xd:       /* ldstub -- XXX: should be atomically */
2967
                    gen_op_ldst(ldstub);
2968
                    break;
2969
                case 0x0f:      /* swap register with memory. Also atomically */
2970
                    gen_op_check_align_T0_3();
2971
                    gen_movl_reg_T1(rd);
2972
                    gen_op_ldst(swap);
2973
                    break;
2974
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
2975
                case 0x10:      /* load word alternate */
2976
#ifndef TARGET_SPARC64
2977
                    if (IS_IMM)
2978
                        goto illegal_insn;
2979
                    if (!supervisor(dc))
2980
                        goto priv_insn;
2981
#endif
2982
                    gen_op_check_align_T0_3();
2983
                    gen_ld_asi(insn, 4, 0);
2984
                    break;
2985
                case 0x11:      /* load unsigned byte alternate */
2986
#ifndef TARGET_SPARC64
2987
                    if (IS_IMM)
2988
                        goto illegal_insn;
2989
                    if (!supervisor(dc))
2990
                        goto priv_insn;
2991
#endif
2992
                    gen_ld_asi(insn, 1, 0);
2993
                    break;
2994
                case 0x12:      /* load unsigned halfword alternate */
2995
#ifndef TARGET_SPARC64
2996
                    if (IS_IMM)
2997
                        goto illegal_insn;
2998
                    if (!supervisor(dc))
2999
                        goto priv_insn;
3000
#endif
3001
                    gen_op_check_align_T0_1();
3002
                    gen_ld_asi(insn, 2, 0);
3003
                    break;
3004
                case 0x13:      /* load double word alternate */
3005
#ifndef TARGET_SPARC64
3006
                    if (IS_IMM)
3007
                        goto illegal_insn;
3008
                    if (!supervisor(dc))
3009
                        goto priv_insn;
3010
#endif
3011
                    if (rd & 1)
3012
                        goto illegal_insn;
3013
                    gen_op_check_align_T0_7();
3014
                    gen_ldda_asi(insn);
3015
                    gen_movl_T0_reg(rd + 1);
3016
                    break;
3017
                case 0x19:      /* load signed byte alternate */
3018
#ifndef TARGET_SPARC64
3019
                    if (IS_IMM)
3020
                        goto illegal_insn;
3021
                    if (!supervisor(dc))
3022
                        goto priv_insn;
3023
#endif
3024
                    gen_ld_asi(insn, 1, 1);
3025
                    break;
3026
                case 0x1a:      /* load signed halfword alternate */
3027
#ifndef TARGET_SPARC64
3028
                    if (IS_IMM)
3029
                        goto illegal_insn;
3030
                    if (!supervisor(dc))
3031
                        goto priv_insn;
3032
#endif
3033
                    gen_op_check_align_T0_1();
3034
                    gen_ld_asi(insn, 2, 1);
3035
                    break;
3036
                case 0x1d:      /* ldstuba -- XXX: should be atomically */
3037
#ifndef TARGET_SPARC64
3038
                    if (IS_IMM)
3039
                        goto illegal_insn;
3040
                    if (!supervisor(dc))
3041
                        goto priv_insn;
3042
#endif
3043
                    gen_ldstub_asi(insn);
3044
                    break;
3045
                case 0x1f:      /* swap reg with alt. memory. Also atomically */
3046
#ifndef TARGET_SPARC64
3047
                    if (IS_IMM)
3048
                        goto illegal_insn;
3049
                    if (!supervisor(dc))
3050
                        goto priv_insn;
3051
#endif
3052
                    gen_op_check_align_T0_3();
3053
                    gen_movl_reg_T1(rd);
3054
                    gen_swap_asi(insn);
3055
                    break;
3056

    
3057
#ifndef TARGET_SPARC64
3058
                case 0x30: /* ldc */
3059
                case 0x31: /* ldcsr */
3060
                case 0x33: /* lddc */
3061
                    goto ncp_insn;
3062
#endif
3063
#endif
3064
#ifdef TARGET_SPARC64
3065
                case 0x08: /* V9 ldsw */
3066
                    gen_op_check_align_T0_3();
3067
                    gen_op_ldst(ldsw);
3068
                    break;
3069
                case 0x0b: /* V9 ldx */
3070
                    gen_op_check_align_T0_7();
3071
                    gen_op_ldst(ldx);
3072
                    break;
3073
                case 0x18: /* V9 ldswa */
3074
                    gen_op_check_align_T0_3();
3075
                    gen_ld_asi(insn, 4, 1);
3076
                    break;
3077
                case 0x1b: /* V9 ldxa */
3078
                    gen_op_check_align_T0_7();
3079
                    gen_ld_asi(insn, 8, 0);
3080
                    break;
3081
                case 0x2d: /* V9 prefetch, no effect */
3082
                    goto skip_move;
3083
                case 0x30: /* V9 ldfa */
3084
                    gen_op_check_align_T0_3();
3085
                    gen_ldf_asi(insn, 4);
3086
                    goto skip_move;
3087
                case 0x33: /* V9 lddfa */
3088
                    gen_op_check_align_T0_3();
3089
                    gen_ldf_asi(insn, 8);
3090
                    goto skip_move;
3091
                case 0x3d: /* V9 prefetcha, no effect */
3092
                    goto skip_move;
3093
                case 0x32: /* V9 ldqfa */
3094
                    goto nfpu_insn;
3095
#endif
3096
                default:
3097
                    goto illegal_insn;
3098
                }
3099
                gen_movl_T1_reg(rd);
3100
#ifdef TARGET_SPARC64
3101
            skip_move: ;
3102
#endif
3103
            } else if (xop >= 0x20 && xop < 0x24) {
3104
                if (gen_trap_ifnofpu(dc))
3105
                    goto jmp_insn;
3106
                switch (xop) {
3107
                case 0x20:      /* load fpreg */
3108
                    gen_op_check_align_T0_3();
3109
                    gen_op_ldst(ldf);
3110
                    gen_op_store_FT0_fpr(rd);
3111
                    break;
3112
                case 0x21:      /* load fsr */
3113
                    gen_op_check_align_T0_3();
3114
                    gen_op_ldst(ldf);
3115
                    gen_op_ldfsr();
3116
                    break;
3117
                case 0x22:      /* load quad fpreg */
3118
                    goto nfpu_insn;
3119
                case 0x23:      /* load double fpreg */
3120
                    gen_op_check_align_T0_7();
3121
                    gen_op_ldst(lddf);
3122
                    gen_op_store_DT0_fpr(DFPREG(rd));
3123
                    break;
3124
                default:
3125
                    goto illegal_insn;
3126
                }
3127
            } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
3128
                       xop == 0xe || xop == 0x1e) {
3129
                gen_movl_reg_T1(rd);
3130
                switch (xop) {
3131
                case 0x4:
3132
                    gen_op_check_align_T0_3();
3133
                    gen_op_ldst(st);
3134
                    break;
3135
                case 0x5:
3136
                    gen_op_ldst(stb);
3137
                    break;
3138
                case 0x6:
3139
                    gen_op_check_align_T0_1();
3140
                    gen_op_ldst(sth);
3141
                    break;
3142
                case 0x7:
3143
                    if (rd & 1)
3144
                        goto illegal_insn;
3145
                    gen_op_check_align_T0_7();
3146
                    flush_T2(dc);
3147
                    gen_movl_reg_T2(rd + 1);
3148
                    gen_op_ldst(std);
3149
                    break;
3150
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
3151
                case 0x14:
3152
#ifndef TARGET_SPARC64
3153
                    if (IS_IMM)
3154
                        goto illegal_insn;
3155
                    if (!supervisor(dc))
3156
                        goto priv_insn;
3157
#endif
3158
                    gen_op_check_align_T0_3();
3159
                    gen_st_asi(insn, 4);
3160
                    break;
3161
                case 0x15:
3162
#ifndef TARGET_SPARC64
3163
                    if (IS_IMM)
3164
                        goto illegal_insn;
3165
                    if (!supervisor(dc))
3166
                        goto priv_insn;
3167
#endif
3168
                    gen_st_asi(insn, 1);
3169
                    break;
3170
                case 0x16:
3171
#ifndef TARGET_SPARC64
3172
                    if (IS_IMM)
3173
                        goto illegal_insn;
3174
                    if (!supervisor(dc))
3175
                        goto priv_insn;
3176
#endif
3177
                    gen_op_check_align_T0_1();
3178
                    gen_st_asi(insn, 2);
3179
                    break;
3180
                case 0x17:
3181
#ifndef TARGET_SPARC64
3182
                    if (IS_IMM)
3183
                        goto illegal_insn;
3184
                    if (!supervisor(dc))
3185
                        goto priv_insn;
3186
#endif
3187
                    if (rd & 1)
3188
                        goto illegal_insn;
3189
                    gen_op_check_align_T0_7();
3190
                    flush_T2(dc);
3191
                    gen_movl_reg_T2(rd + 1);
3192
                    gen_stda_asi(insn);
3193
                    break;
3194
#endif
3195
#ifdef TARGET_SPARC64
3196
                case 0x0e: /* V9 stx */
3197
                    gen_op_check_align_T0_7();
3198
                    gen_op_ldst(stx);
3199
                    break;
3200
                case 0x1e: /* V9 stxa */
3201
                    gen_op_check_align_T0_7();
3202
                    gen_st_asi(insn, 8);
3203
                    break;
3204
#endif
3205
                default:
3206
                    goto illegal_insn;
3207
                }
3208
            } else if (xop > 0x23 && xop < 0x28) {
3209
                if (gen_trap_ifnofpu(dc))
3210
                    goto jmp_insn;
3211
                switch (xop) {
3212
                case 0x24:
3213
                    gen_op_check_align_T0_3();
3214
                    gen_op_load_fpr_FT0(rd);
3215
                    gen_op_ldst(stf);
3216
                    break;
3217
                case 0x25: /* stfsr, V9 stxfsr */
3218
#ifdef CONFIG_USER_ONLY
3219
                    gen_op_check_align_T0_3();
3220
#endif
3221
                    gen_op_stfsr();
3222
                    gen_op_ldst(stf);
3223
                    break;
3224
#if !defined(CONFIG_USER_ONLY)
3225
                case 0x26: /* stdfq */
3226
                    if (!supervisor(dc))
3227
                        goto priv_insn;
3228
                    if (gen_trap_ifnofpu(dc))
3229
                        goto jmp_insn;
3230
                    goto nfq_insn;
3231
#endif
3232
                case 0x27:
3233
                    gen_op_check_align_T0_7();
3234
                    gen_op_load_fpr_DT0(DFPREG(rd));
3235
                    gen_op_ldst(stdf);
3236
                    break;
3237
                default:
3238
                    goto illegal_insn;
3239
                }
3240
            } else if (xop > 0x33 && xop < 0x3f) {
3241
                switch (xop) {
3242
#ifdef TARGET_SPARC64
3243
                case 0x34: /* V9 stfa */
3244
                    gen_op_check_align_T0_3();
3245
                    gen_op_load_fpr_FT0(rd);
3246
                    gen_stf_asi(insn, 4);
3247
                    break;
3248
                case 0x37: /* V9 stdfa */
3249
                    gen_op_check_align_T0_3();
3250
                    gen_op_load_fpr_DT0(DFPREG(rd));
3251
                    gen_stf_asi(insn, 8);
3252
                    break;
3253
                case 0x3c: /* V9 casa */
3254
                    gen_op_check_align_T0_3();
3255
                    flush_T2(dc);
3256
                    gen_movl_reg_T2(rd);
3257
                    gen_cas_asi(insn);
3258
                    gen_movl_T1_reg(rd);
3259
                    break;
3260
                case 0x3e: /* V9 casxa */
3261
                    gen_op_check_align_T0_7();
3262
                    flush_T2(dc);
3263
                    gen_movl_reg_T2(rd);
3264
                    gen_casx_asi(insn);
3265
                    gen_movl_T1_reg(rd);
3266
                    break;
3267
                case 0x36: /* V9 stqfa */
3268
                    goto nfpu_insn;
3269
#else
3270
                case 0x34: /* stc */
3271
                case 0x35: /* stcsr */
3272
                case 0x36: /* stdcq */
3273
                case 0x37: /* stdc */
3274
                    goto ncp_insn;
3275
#endif
3276
                default:
3277
                    goto illegal_insn;
3278
                }
3279
            }
3280
            else
3281
                goto illegal_insn;
3282
        }
3283
        break;
3284
    }
3285
    /* default case for non jump instructions */
3286
    if (dc->npc == DYNAMIC_PC) {
3287
        dc->pc = DYNAMIC_PC;
3288
        gen_op_next_insn();
3289
    } else if (dc->npc == JUMP_PC) {
3290
        /* we can do a static jump */
3291
        gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1]);
3292
        dc->is_br = 1;
3293
    } else {
3294
        dc->pc = dc->npc;
3295
        dc->npc = dc->npc + 4;
3296
    }
3297
 jmp_insn:
3298
    return;
3299
 illegal_insn:
3300
    save_state(dc);
3301
    gen_op_exception(TT_ILL_INSN);
3302
    dc->is_br = 1;
3303
    return;
3304
#if !defined(CONFIG_USER_ONLY)
3305
 priv_insn:
3306
    save_state(dc);
3307
    gen_op_exception(TT_PRIV_INSN);
3308
    dc->is_br = 1;
3309
    return;
3310
#endif
3311
 nfpu_insn:
3312
    save_state(dc);
3313
    gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
3314
    dc->is_br = 1;
3315
    return;
3316
#if !defined(CONFIG_USER_ONLY)
3317
 nfq_insn:
3318
    save_state(dc);
3319
    gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
3320
    dc->is_br = 1;
3321
    return;
3322
#endif
3323
#ifndef TARGET_SPARC64
3324
 ncp_insn:
3325
    save_state(dc);
3326
    gen_op_exception(TT_NCP_INSN);
3327
    dc->is_br = 1;
3328
    return;
3329
#endif
3330
}
3331

    
3332
static inline int gen_intermediate_code_internal(TranslationBlock * tb,
3333
                                                 int spc, CPUSPARCState *env)
3334
{
3335
    target_ulong pc_start, last_pc;
3336
    uint16_t *gen_opc_end;
3337
    DisasContext dc1, *dc = &dc1;
3338
    int j, lj = -1;
3339

    
3340
    memset(dc, 0, sizeof(DisasContext));
3341
    dc->tb = tb;
3342
    pc_start = tb->pc;
3343
    dc->pc = pc_start;
3344
    last_pc = dc->pc;
3345
    dc->npc = (target_ulong) tb->cs_base;
3346
    dc->mem_idx = cpu_mmu_index(env);
3347
    dc->fpu_enabled = cpu_fpu_enabled(env);
3348
    gen_opc_ptr = gen_opc_buf;
3349
    gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
3350
    gen_opparam_ptr = gen_opparam_buf;
3351
    nb_gen_labels = 0;
3352

    
3353
    do {
3354
        if (env->nb_breakpoints > 0) {
3355
            for(j = 0; j < env->nb_breakpoints; j++) {
3356
                if (env->breakpoints[j] == dc->pc) {
3357
                    if (dc->pc != pc_start)
3358
                        save_state(dc);
3359
                    gen_op_debug();
3360
                    gen_op_movl_T0_0();
3361
                    gen_op_exit_tb();
3362
                    dc->is_br = 1;
3363
                    goto exit_gen_loop;
3364
                }
3365
            }
3366
        }
3367
        if (spc) {
3368
            if (loglevel > 0)
3369
                fprintf(logfile, "Search PC...\n");
3370
            j = gen_opc_ptr - gen_opc_buf;
3371
            if (lj < j) {
3372
                lj++;
3373
                while (lj < j)
3374
                    gen_opc_instr_start[lj++] = 0;
3375
                gen_opc_pc[lj] = dc->pc;
3376
                gen_opc_npc[lj] = dc->npc;
3377
                gen_opc_instr_start[lj] = 1;
3378
            }
3379
        }
3380
        last_pc = dc->pc;
3381
        disas_sparc_insn(dc);
3382

    
3383
        if (dc->is_br)
3384
            break;
3385
        /* if the next PC is different, we abort now */
3386
        if (dc->pc != (last_pc + 4))
3387
            break;
3388
        /* if we reach a page boundary, we stop generation so that the
3389
           PC of a TT_TFAULT exception is always in the right page */
3390
        if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
3391
            break;
3392
        /* if single step mode, we generate only one instruction and
3393
           generate an exception */
3394
        if (env->singlestep_enabled) {
3395
            gen_jmp_im(dc->pc);
3396
            gen_op_movl_T0_0();
3397
            gen_op_exit_tb();
3398
            break;
3399
        }
3400
    } while ((gen_opc_ptr < gen_opc_end) &&
3401
             (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
3402

    
3403
 exit_gen_loop:
3404
    if (!dc->is_br) {
3405
        if (dc->pc != DYNAMIC_PC &&
3406
            (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
3407
            /* static PC and NPC: we can use direct chaining */
3408
            gen_branch(dc, dc->pc, dc->npc);
3409
        } else {
3410
            if (dc->pc != DYNAMIC_PC)
3411
                gen_jmp_im(dc->pc);
3412
            save_npc(dc);
3413
            gen_op_movl_T0_0();
3414
            gen_op_exit_tb();
3415
        }
3416
    }
3417
    *gen_opc_ptr = INDEX_op_end;
3418
    if (spc) {
3419
        j = gen_opc_ptr - gen_opc_buf;
3420
        lj++;
3421
        while (lj <= j)
3422
            gen_opc_instr_start[lj++] = 0;
3423
#if 0
3424
        if (loglevel > 0) {
3425
            page_dump(logfile);
3426
        }
3427
#endif
3428
        gen_opc_jump_pc[0] = dc->jump_pc[0];
3429
        gen_opc_jump_pc[1] = dc->jump_pc[1];
3430
    } else {
3431
        tb->size = last_pc + 4 - pc_start;
3432
    }
3433
#ifdef DEBUG_DISAS
3434
    if (loglevel & CPU_LOG_TB_IN_ASM) {
3435
        fprintf(logfile, "--------------\n");
3436
        fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
3437
        target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
3438
        fprintf(logfile, "\n");
3439
        if (loglevel & CPU_LOG_TB_OP) {
3440
            fprintf(logfile, "OP:\n");
3441
            dump_ops(gen_opc_buf, gen_opparam_buf);
3442
            fprintf(logfile, "\n");
3443
        }
3444
    }
3445
#endif
3446
    return 0;
3447
}
3448

    
3449
int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
3450
{
3451
    return gen_intermediate_code_internal(tb, 0, env);
3452
}
3453

    
3454
int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
3455
{
3456
    return gen_intermediate_code_internal(tb, 1, env);
3457
}
3458

    
3459
extern int ram_size;
3460

    
3461
void cpu_reset(CPUSPARCState *env)
3462
{
3463
    tlb_flush(env, 1);
3464
    env->cwp = 0;
3465
    env->wim = 1;
3466
    env->regwptr = env->regbase + (env->cwp * 16);
3467
#if defined(CONFIG_USER_ONLY)
3468
    env->user_mode_only = 1;
3469
#ifdef TARGET_SPARC64
3470
    env->cleanwin = NWINDOWS - 2;
3471
    env->cansave = NWINDOWS - 2;
3472
    env->pstate = PS_RMO | PS_PEF | PS_IE;
3473
    env->asi = 0x82; // Primary no-fault
3474
#endif
3475
#else
3476
    env->psret = 0;
3477
    env->psrs = 1;
3478
    env->psrps = 1;
3479
#ifdef TARGET_SPARC64
3480
    env->pstate = PS_PRIV;
3481
    env->hpstate = HS_PRIV;
3482
    env->pc = 0x1fff0000000ULL;
3483
#else
3484
    env->pc = 0;
3485
    env->mmuregs[0] &= ~(MMU_E | MMU_NF);
3486
    env->mmuregs[0] |= env->mmu_bm;
3487
#endif
3488
    env->npc = env->pc + 4;
3489
#endif
3490
}
3491

    
3492
CPUSPARCState *cpu_sparc_init(void)
3493
{
3494
    CPUSPARCState *env;
3495

    
3496
    env = qemu_mallocz(sizeof(CPUSPARCState));
3497
    if (!env)
3498
        return NULL;
3499
    cpu_exec_init(env);
3500
    return (env);
3501
}
3502

    
3503
static const sparc_def_t sparc_defs[] = {
3504
#ifdef TARGET_SPARC64
3505
    {
3506
        .name = "TI UltraSparc II",
3507
        .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0 << 24)
3508
                       | (MAXTL << 8) | (NWINDOWS - 1)),
3509
        .fpu_version = 0x00000000,
3510
        .mmu_version = 0,
3511
    },
3512
#else
3513
    {
3514
        .name = "Fujitsu MB86904",
3515
        .iu_version = 0x04 << 24, /* Impl 0, ver 4 */
3516
        .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
3517
        .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
3518
        .mmu_bm = 0x00004000,
3519
    },
3520
    {
3521
        .name = "Fujitsu MB86907",
3522
        .iu_version = 0x05 << 24, /* Impl 0, ver 5 */
3523
        .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
3524
        .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
3525
        .mmu_bm = 0x00004000,
3526
    },
3527
    {
3528
        .name = "TI MicroSparc I",
3529
        .iu_version = 0x41000000,
3530
        .fpu_version = 4 << 17,
3531
        .mmu_version = 0x41000000,
3532
        .mmu_bm = 0x00004000,
3533
    },
3534
    {
3535
        .name = "TI SuperSparc II",
3536
        .iu_version = 0x40000000,
3537
        .fpu_version = 0 << 17,
3538
        .mmu_version = 0x04000000,
3539
        .mmu_bm = 0x00002000,
3540
    },
3541
    {
3542
        .name = "Ross RT620",
3543
        .iu_version = 0x1e000000,
3544
        .fpu_version = 1 << 17,
3545
        .mmu_version = 0x17000000,
3546
        .mmu_bm = 0x00004000,
3547
    },
3548
#endif
3549
};
3550

    
3551
int sparc_find_by_name(const unsigned char *name, const sparc_def_t **def)
3552
{
3553
    int ret;
3554
    unsigned int i;
3555

    
3556
    ret = -1;
3557
    *def = NULL;
3558
    for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) {
3559
        if (strcasecmp(name, sparc_defs[i].name) == 0) {
3560
            *def = &sparc_defs[i];
3561
            ret = 0;
3562
            break;
3563
        }
3564
    }
3565

    
3566
    return ret;
3567
}
3568

    
3569
void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
3570
{
3571
    unsigned int i;
3572

    
3573
    for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) {
3574
        (*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx " FPU %08x MMU %08x\n",
3575
                       sparc_defs[i].name,
3576
                       sparc_defs[i].iu_version,
3577
                       sparc_defs[i].fpu_version,
3578
                       sparc_defs[i].mmu_version);
3579
    }
3580
}
3581

    
3582
int cpu_sparc_register (CPUSPARCState *env, const sparc_def_t *def, unsigned int cpu)
3583
{
3584
    env->version = def->iu_version;
3585
    env->fsr = def->fpu_version;
3586
#if !defined(TARGET_SPARC64)
3587
    env->mmu_bm = def->mmu_bm;
3588
    env->mmuregs[0] |= def->mmu_version;
3589
    env->mxccregs[7] = ((cpu + 8) & 0xf) << 24;
3590
#endif
3591
    cpu_reset(env);
3592
    return 0;
3593
}
3594

    
3595
#define GET_FLAG(a,b) ((env->psr & a)?b:'-')
3596

    
3597
void cpu_dump_state(CPUState *env, FILE *f,
3598
                    int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
3599
                    int flags)
3600
{
3601
    int i, x;
3602

    
3603
    cpu_fprintf(f, "pc: " TARGET_FMT_lx "  npc: " TARGET_FMT_lx "\n", env->pc, env->npc);
3604
    cpu_fprintf(f, "General Registers:\n");
3605
    for (i = 0; i < 4; i++)
3606
        cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
3607
    cpu_fprintf(f, "\n");
3608
    for (; i < 8; i++)
3609
        cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
3610
    cpu_fprintf(f, "\nCurrent Register Window:\n");
3611
    for (x = 0; x < 3; x++) {
3612
        for (i = 0; i < 4; i++)
3613
            cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
3614
                    (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i,
3615
                    env->regwptr[i + x * 8]);
3616
        cpu_fprintf(f, "\n");
3617
        for (; i < 8; i++)
3618
            cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
3619
                    (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i,
3620
                    env->regwptr[i + x * 8]);
3621
        cpu_fprintf(f, "\n");
3622
    }
3623
    cpu_fprintf(f, "\nFloating Point Registers:\n");
3624
    for (i = 0; i < 32; i++) {
3625
        if ((i & 3) == 0)
3626
            cpu_fprintf(f, "%%f%02d:", i);
3627
        cpu_fprintf(f, " %016lf", env->fpr[i]);
3628
        if ((i & 3) == 3)
3629
            cpu_fprintf(f, "\n");
3630
    }
3631
#ifdef TARGET_SPARC64
3632
    cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n",
3633
                env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs);
3634
    cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d cleanwin %d cwp %d\n",
3635
                env->cansave, env->canrestore, env->otherwin, env->wstate,
3636
                env->cleanwin, NWINDOWS - 1 - env->cwp);
3637
#else
3638
    cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env),
3639
            GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
3640
            GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
3641
            env->psrs?'S':'-', env->psrps?'P':'-',
3642
            env->psret?'E':'-', env->wim);
3643
#endif
3644
    cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env));
3645
}
3646

    
3647
#if defined(CONFIG_USER_ONLY)
3648
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
3649
{
3650
    return addr;
3651
}
3652

    
3653
#else
3654
extern int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot,
3655
                                 int *access_index, target_ulong address, int rw,
3656
                                 int mmu_idx);
3657

    
3658
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
3659
{
3660
    target_phys_addr_t phys_addr;
3661
    int prot, access_index;
3662

    
3663
    if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2, 0) != 0)
3664
        if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 0, 0) != 0)
3665
            return -1;
3666
    if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED)
3667
        return -1;
3668
    return phys_addr;
3669
}
3670
#endif
3671

    
3672
void helper_flush(target_ulong addr)
3673
{
3674
    addr &= ~7;
3675
    tb_invalidate_page_range(addr, addr + 8);
3676
}