root / tcg / tcg-op.h @ 6ddbc6e4
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1 | c896fe29 | bellard | /*
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2 | c896fe29 | bellard | * Tiny Code Generator for QEMU
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3 | c896fe29 | bellard | *
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4 | c896fe29 | bellard | * Copyright (c) 2008 Fabrice Bellard
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5 | c896fe29 | bellard | *
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6 | c896fe29 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | c896fe29 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | c896fe29 | bellard | * in the Software without restriction, including without limitation the rights
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9 | c896fe29 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | c896fe29 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | c896fe29 | bellard | * furnished to do so, subject to the following conditions:
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12 | c896fe29 | bellard | *
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13 | c896fe29 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | c896fe29 | bellard | * all copies or substantial portions of the Software.
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15 | c896fe29 | bellard | *
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16 | c896fe29 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | c896fe29 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | c896fe29 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | c896fe29 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | c896fe29 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | c896fe29 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | c896fe29 | bellard | * THE SOFTWARE.
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23 | c896fe29 | bellard | */
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24 | c896fe29 | bellard | #include "tcg.h" |
25 | c896fe29 | bellard | |
26 | cf2be984 | blueswir1 | #ifndef CONFIG_NO_DYNGEN_OP
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27 | c896fe29 | bellard | /* legacy dyngen operations */
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28 | c896fe29 | bellard | #include "gen-op.h" |
29 | cf2be984 | blueswir1 | #endif
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30 | c896fe29 | bellard | |
31 | c896fe29 | bellard | int gen_new_label(void); |
32 | c896fe29 | bellard | |
33 | ac56dd48 | pbrook | static inline void tcg_gen_op1(int opc, TCGv arg1) |
34 | c896fe29 | bellard | { |
35 | c896fe29 | bellard | *gen_opc_ptr++ = opc; |
36 | ac56dd48 | pbrook | *gen_opparam_ptr++ = GET_TCGV(arg1); |
37 | c896fe29 | bellard | } |
38 | c896fe29 | bellard | |
39 | ac56dd48 | pbrook | static inline void tcg_gen_op1i(int opc, TCGArg arg1) |
40 | c896fe29 | bellard | { |
41 | c896fe29 | bellard | *gen_opc_ptr++ = opc; |
42 | c896fe29 | bellard | *gen_opparam_ptr++ = arg1; |
43 | c896fe29 | bellard | } |
44 | c896fe29 | bellard | |
45 | ac56dd48 | pbrook | static inline void tcg_gen_op2(int opc, TCGv arg1, TCGv arg2) |
46 | c896fe29 | bellard | { |
47 | c896fe29 | bellard | *gen_opc_ptr++ = opc; |
48 | ac56dd48 | pbrook | *gen_opparam_ptr++ = GET_TCGV(arg1); |
49 | ac56dd48 | pbrook | *gen_opparam_ptr++ = GET_TCGV(arg2); |
50 | c896fe29 | bellard | } |
51 | c896fe29 | bellard | |
52 | ac56dd48 | pbrook | static inline void tcg_gen_op2i(int opc, TCGv arg1, TCGArg arg2) |
53 | c896fe29 | bellard | { |
54 | c896fe29 | bellard | *gen_opc_ptr++ = opc; |
55 | ac56dd48 | pbrook | *gen_opparam_ptr++ = GET_TCGV(arg1); |
56 | c896fe29 | bellard | *gen_opparam_ptr++ = arg2; |
57 | ac56dd48 | pbrook | } |
58 | ac56dd48 | pbrook | |
59 | ac56dd48 | pbrook | static inline void tcg_gen_op3(int opc, TCGv arg1, TCGv arg2, TCGv arg3) |
60 | ac56dd48 | pbrook | { |
61 | ac56dd48 | pbrook | *gen_opc_ptr++ = opc; |
62 | ac56dd48 | pbrook | *gen_opparam_ptr++ = GET_TCGV(arg1); |
63 | ac56dd48 | pbrook | *gen_opparam_ptr++ = GET_TCGV(arg2); |
64 | ac56dd48 | pbrook | *gen_opparam_ptr++ = GET_TCGV(arg3); |
65 | ac56dd48 | pbrook | } |
66 | ac56dd48 | pbrook | |
67 | ac56dd48 | pbrook | static inline void tcg_gen_op3i(int opc, TCGv arg1, TCGv arg2, TCGArg arg3) |
68 | ac56dd48 | pbrook | { |
69 | ac56dd48 | pbrook | *gen_opc_ptr++ = opc; |
70 | ac56dd48 | pbrook | *gen_opparam_ptr++ = GET_TCGV(arg1); |
71 | ac56dd48 | pbrook | *gen_opparam_ptr++ = GET_TCGV(arg2); |
72 | c896fe29 | bellard | *gen_opparam_ptr++ = arg3; |
73 | ac56dd48 | pbrook | } |
74 | ac56dd48 | pbrook | |
75 | ac56dd48 | pbrook | static inline void tcg_gen_op4(int opc, TCGv arg1, TCGv arg2, TCGv arg3, |
76 | ac56dd48 | pbrook | TCGv arg4) |
77 | ac56dd48 | pbrook | { |
78 | ac56dd48 | pbrook | *gen_opc_ptr++ = opc; |
79 | ac56dd48 | pbrook | *gen_opparam_ptr++ = GET_TCGV(arg1); |
80 | ac56dd48 | pbrook | *gen_opparam_ptr++ = GET_TCGV(arg2); |
81 | ac56dd48 | pbrook | *gen_opparam_ptr++ = GET_TCGV(arg3); |
82 | ac56dd48 | pbrook | *gen_opparam_ptr++ = GET_TCGV(arg4); |
83 | ac56dd48 | pbrook | } |
84 | ac56dd48 | pbrook | |
85 | ac56dd48 | pbrook | static inline void tcg_gen_op4i(int opc, TCGv arg1, TCGv arg2, TCGv arg3, |
86 | ac56dd48 | pbrook | TCGArg arg4) |
87 | ac56dd48 | pbrook | { |
88 | ac56dd48 | pbrook | *gen_opc_ptr++ = opc; |
89 | ac56dd48 | pbrook | *gen_opparam_ptr++ = GET_TCGV(arg1); |
90 | ac56dd48 | pbrook | *gen_opparam_ptr++ = GET_TCGV(arg2); |
91 | ac56dd48 | pbrook | *gen_opparam_ptr++ = GET_TCGV(arg3); |
92 | c896fe29 | bellard | *gen_opparam_ptr++ = arg4; |
93 | c896fe29 | bellard | } |
94 | c896fe29 | bellard | |
95 | ac56dd48 | pbrook | static inline void tcg_gen_op4ii(int opc, TCGv arg1, TCGv arg2, TCGArg arg3, |
96 | ac56dd48 | pbrook | TCGArg arg4) |
97 | c896fe29 | bellard | { |
98 | c896fe29 | bellard | *gen_opc_ptr++ = opc; |
99 | ac56dd48 | pbrook | *gen_opparam_ptr++ = GET_TCGV(arg1); |
100 | ac56dd48 | pbrook | *gen_opparam_ptr++ = GET_TCGV(arg2); |
101 | c896fe29 | bellard | *gen_opparam_ptr++ = arg3; |
102 | c896fe29 | bellard | *gen_opparam_ptr++ = arg4; |
103 | ac56dd48 | pbrook | } |
104 | ac56dd48 | pbrook | |
105 | ac56dd48 | pbrook | static inline void tcg_gen_op5(int opc, TCGv arg1, TCGv arg2, |
106 | ac56dd48 | pbrook | TCGv arg3, TCGv arg4, |
107 | ac56dd48 | pbrook | TCGv arg5) |
108 | ac56dd48 | pbrook | { |
109 | ac56dd48 | pbrook | *gen_opc_ptr++ = opc; |
110 | ac56dd48 | pbrook | *gen_opparam_ptr++ = GET_TCGV(arg1); |
111 | ac56dd48 | pbrook | *gen_opparam_ptr++ = GET_TCGV(arg2); |
112 | ac56dd48 | pbrook | *gen_opparam_ptr++ = GET_TCGV(arg3); |
113 | ac56dd48 | pbrook | *gen_opparam_ptr++ = GET_TCGV(arg4); |
114 | ac56dd48 | pbrook | *gen_opparam_ptr++ = GET_TCGV(arg5); |
115 | ac56dd48 | pbrook | } |
116 | ac56dd48 | pbrook | |
117 | ac56dd48 | pbrook | static inline void tcg_gen_op5i(int opc, TCGv arg1, TCGv arg2, |
118 | ac56dd48 | pbrook | TCGv arg3, TCGv arg4, |
119 | ac56dd48 | pbrook | TCGArg arg5) |
120 | ac56dd48 | pbrook | { |
121 | ac56dd48 | pbrook | *gen_opc_ptr++ = opc; |
122 | ac56dd48 | pbrook | *gen_opparam_ptr++ = GET_TCGV(arg1); |
123 | ac56dd48 | pbrook | *gen_opparam_ptr++ = GET_TCGV(arg2); |
124 | ac56dd48 | pbrook | *gen_opparam_ptr++ = GET_TCGV(arg3); |
125 | ac56dd48 | pbrook | *gen_opparam_ptr++ = GET_TCGV(arg4); |
126 | c896fe29 | bellard | *gen_opparam_ptr++ = arg5; |
127 | c896fe29 | bellard | } |
128 | c896fe29 | bellard | |
129 | ac56dd48 | pbrook | static inline void tcg_gen_op6(int opc, TCGv arg1, TCGv arg2, |
130 | ac56dd48 | pbrook | TCGv arg3, TCGv arg4, |
131 | ac56dd48 | pbrook | TCGv arg5, TCGv arg6) |
132 | c896fe29 | bellard | { |
133 | c896fe29 | bellard | *gen_opc_ptr++ = opc; |
134 | ac56dd48 | pbrook | *gen_opparam_ptr++ = GET_TCGV(arg1); |
135 | ac56dd48 | pbrook | *gen_opparam_ptr++ = GET_TCGV(arg2); |
136 | ac56dd48 | pbrook | *gen_opparam_ptr++ = GET_TCGV(arg3); |
137 | ac56dd48 | pbrook | *gen_opparam_ptr++ = GET_TCGV(arg4); |
138 | ac56dd48 | pbrook | *gen_opparam_ptr++ = GET_TCGV(arg5); |
139 | ac56dd48 | pbrook | *gen_opparam_ptr++ = GET_TCGV(arg6); |
140 | ac56dd48 | pbrook | } |
141 | ac56dd48 | pbrook | |
142 | ac56dd48 | pbrook | static inline void tcg_gen_op6ii(int opc, TCGv arg1, TCGv arg2, |
143 | ac56dd48 | pbrook | TCGv arg3, TCGv arg4, |
144 | ac56dd48 | pbrook | TCGArg arg5, TCGArg arg6) |
145 | ac56dd48 | pbrook | { |
146 | ac56dd48 | pbrook | *gen_opc_ptr++ = opc; |
147 | ac56dd48 | pbrook | *gen_opparam_ptr++ = GET_TCGV(arg1); |
148 | ac56dd48 | pbrook | *gen_opparam_ptr++ = GET_TCGV(arg2); |
149 | ac56dd48 | pbrook | *gen_opparam_ptr++ = GET_TCGV(arg3); |
150 | ac56dd48 | pbrook | *gen_opparam_ptr++ = GET_TCGV(arg4); |
151 | c896fe29 | bellard | *gen_opparam_ptr++ = arg5; |
152 | c896fe29 | bellard | *gen_opparam_ptr++ = arg6; |
153 | c896fe29 | bellard | } |
154 | c896fe29 | bellard | |
155 | c896fe29 | bellard | static inline void gen_set_label(int n) |
156 | c896fe29 | bellard | { |
157 | ac56dd48 | pbrook | tcg_gen_op1i(INDEX_op_set_label, n); |
158 | c896fe29 | bellard | } |
159 | c896fe29 | bellard | |
160 | fb50d413 | blueswir1 | static inline void tcg_gen_br(int label) |
161 | fb50d413 | blueswir1 | { |
162 | fb50d413 | blueswir1 | tcg_gen_op1i(INDEX_op_br, label); |
163 | fb50d413 | blueswir1 | } |
164 | fb50d413 | blueswir1 | |
165 | ac56dd48 | pbrook | static inline void tcg_gen_mov_i32(TCGv ret, TCGv arg) |
166 | c896fe29 | bellard | { |
167 | c896fe29 | bellard | tcg_gen_op2(INDEX_op_mov_i32, ret, arg); |
168 | c896fe29 | bellard | } |
169 | c896fe29 | bellard | |
170 | ac56dd48 | pbrook | static inline void tcg_gen_movi_i32(TCGv ret, int32_t arg) |
171 | c896fe29 | bellard | { |
172 | ac56dd48 | pbrook | tcg_gen_op2i(INDEX_op_movi_i32, ret, arg); |
173 | c896fe29 | bellard | } |
174 | c896fe29 | bellard | |
175 | c896fe29 | bellard | /* helper calls */
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176 | c896fe29 | bellard | #define TCG_HELPER_CALL_FLAGS 0 |
177 | c896fe29 | bellard | |
178 | c896fe29 | bellard | static inline void tcg_gen_helper_0_0(void *func) |
179 | c896fe29 | bellard | { |
180 | c896fe29 | bellard | tcg_gen_call(&tcg_ctx, |
181 | c896fe29 | bellard | tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS, |
182 | c896fe29 | bellard | 0, NULL, 0, NULL); |
183 | c896fe29 | bellard | } |
184 | c896fe29 | bellard | |
185 | ac56dd48 | pbrook | static inline void tcg_gen_helper_0_1(void *func, TCGv arg) |
186 | c896fe29 | bellard | { |
187 | c896fe29 | bellard | tcg_gen_call(&tcg_ctx, |
188 | c896fe29 | bellard | tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS, |
189 | c896fe29 | bellard | 0, NULL, 1, &arg); |
190 | c896fe29 | bellard | } |
191 | c896fe29 | bellard | |
192 | ac56dd48 | pbrook | static inline void tcg_gen_helper_0_2(void *func, TCGv arg1, TCGv arg2) |
193 | c896fe29 | bellard | { |
194 | ac56dd48 | pbrook | TCGv args[2];
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195 | c896fe29 | bellard | args[0] = arg1;
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196 | c896fe29 | bellard | args[1] = arg2;
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197 | c896fe29 | bellard | tcg_gen_call(&tcg_ctx, |
198 | c896fe29 | bellard | tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS, |
199 | c896fe29 | bellard | 0, NULL, 2, args); |
200 | c896fe29 | bellard | } |
201 | c896fe29 | bellard | |
202 | f8422f52 | blueswir1 | static inline void tcg_gen_helper_0_4(void *func, TCGv arg1, TCGv arg2, |
203 | f8422f52 | blueswir1 | TCGv arg3, TCGv arg4) |
204 | f8422f52 | blueswir1 | { |
205 | f8422f52 | blueswir1 | TCGv args[4];
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206 | f8422f52 | blueswir1 | args[0] = arg1;
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207 | f8422f52 | blueswir1 | args[1] = arg2;
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208 | f8422f52 | blueswir1 | args[2] = arg3;
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209 | f8422f52 | blueswir1 | args[3] = arg4;
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210 | f8422f52 | blueswir1 | tcg_gen_call(&tcg_ctx, |
211 | f8422f52 | blueswir1 | tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS, |
212 | f8422f52 | blueswir1 | 0, NULL, 4, args); |
213 | f8422f52 | blueswir1 | } |
214 | f8422f52 | blueswir1 | |
215 | f8422f52 | blueswir1 | static inline void tcg_gen_helper_1_0(void *func, TCGv ret) |
216 | f8422f52 | blueswir1 | { |
217 | f8422f52 | blueswir1 | tcg_gen_call(&tcg_ctx, |
218 | f8422f52 | blueswir1 | tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS, |
219 | f8422f52 | blueswir1 | 1, &ret, 0, NULL); |
220 | f8422f52 | blueswir1 | } |
221 | f8422f52 | blueswir1 | |
222 | f8422f52 | blueswir1 | static inline void tcg_gen_helper_1_1(void *func, TCGv ret, TCGv arg1) |
223 | f8422f52 | blueswir1 | { |
224 | f8422f52 | blueswir1 | tcg_gen_call(&tcg_ctx, |
225 | f8422f52 | blueswir1 | tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS, |
226 | f8422f52 | blueswir1 | 1, &ret, 1, &arg1); |
227 | f8422f52 | blueswir1 | } |
228 | f8422f52 | blueswir1 | |
229 | ac56dd48 | pbrook | static inline void tcg_gen_helper_1_2(void *func, TCGv ret, |
230 | ac56dd48 | pbrook | TCGv arg1, TCGv arg2) |
231 | c896fe29 | bellard | { |
232 | ac56dd48 | pbrook | TCGv args[2];
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233 | c896fe29 | bellard | args[0] = arg1;
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234 | c896fe29 | bellard | args[1] = arg2;
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235 | c896fe29 | bellard | tcg_gen_call(&tcg_ctx, |
236 | c896fe29 | bellard | tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS, |
237 | c896fe29 | bellard | 1, &ret, 2, args); |
238 | c896fe29 | bellard | } |
239 | c896fe29 | bellard | |
240 | 6ddbc6e4 | pbrook | static inline void tcg_gen_helper_1_3(void *func, TCGv ret, |
241 | 6ddbc6e4 | pbrook | TCGv arg1, TCGv arg2, TCGv arg3) |
242 | 6ddbc6e4 | pbrook | { |
243 | 6ddbc6e4 | pbrook | TCGv args[3];
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244 | 6ddbc6e4 | pbrook | args[0] = arg1;
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245 | 6ddbc6e4 | pbrook | args[1] = arg2;
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246 | 6ddbc6e4 | pbrook | args[2] = arg3;
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247 | 6ddbc6e4 | pbrook | tcg_gen_call(&tcg_ctx, |
248 | 6ddbc6e4 | pbrook | tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS, |
249 | 6ddbc6e4 | pbrook | 1, &ret, 3, args); |
250 | 6ddbc6e4 | pbrook | } |
251 | 6ddbc6e4 | pbrook | |
252 | f8422f52 | blueswir1 | static inline void tcg_gen_helper_1_4(void *func, TCGv ret, |
253 | f8422f52 | blueswir1 | TCGv arg1, TCGv arg2, TCGv arg3, |
254 | f8422f52 | blueswir1 | TCGv arg4) |
255 | f8422f52 | blueswir1 | { |
256 | f8422f52 | blueswir1 | TCGv args[4];
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257 | f8422f52 | blueswir1 | args[0] = arg1;
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258 | f8422f52 | blueswir1 | args[1] = arg2;
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259 | f8422f52 | blueswir1 | args[2] = arg3;
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260 | f8422f52 | blueswir1 | args[3] = arg4;
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261 | f8422f52 | blueswir1 | tcg_gen_call(&tcg_ctx, |
262 | f8422f52 | blueswir1 | tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS, |
263 | f8422f52 | blueswir1 | 1, &ret, 4, args); |
264 | f8422f52 | blueswir1 | } |
265 | f8422f52 | blueswir1 | |
266 | c896fe29 | bellard | /* 32 bit ops */
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267 | c896fe29 | bellard | |
268 | ac56dd48 | pbrook | static inline void tcg_gen_ld8u_i32(TCGv ret, TCGv arg2, tcg_target_long offset) |
269 | c896fe29 | bellard | { |
270 | ac56dd48 | pbrook | tcg_gen_op3i(INDEX_op_ld8u_i32, ret, arg2, offset); |
271 | c896fe29 | bellard | } |
272 | c896fe29 | bellard | |
273 | ac56dd48 | pbrook | static inline void tcg_gen_ld8s_i32(TCGv ret, TCGv arg2, tcg_target_long offset) |
274 | c896fe29 | bellard | { |
275 | ac56dd48 | pbrook | tcg_gen_op3i(INDEX_op_ld8s_i32, ret, arg2, offset); |
276 | c896fe29 | bellard | } |
277 | c896fe29 | bellard | |
278 | ac56dd48 | pbrook | static inline void tcg_gen_ld16u_i32(TCGv ret, TCGv arg2, tcg_target_long offset) |
279 | c896fe29 | bellard | { |
280 | ac56dd48 | pbrook | tcg_gen_op3i(INDEX_op_ld16u_i32, ret, arg2, offset); |
281 | c896fe29 | bellard | } |
282 | c896fe29 | bellard | |
283 | ac56dd48 | pbrook | static inline void tcg_gen_ld16s_i32(TCGv ret, TCGv arg2, tcg_target_long offset) |
284 | c896fe29 | bellard | { |
285 | ac56dd48 | pbrook | tcg_gen_op3i(INDEX_op_ld16s_i32, ret, arg2, offset); |
286 | c896fe29 | bellard | } |
287 | c896fe29 | bellard | |
288 | ac56dd48 | pbrook | static inline void tcg_gen_ld_i32(TCGv ret, TCGv arg2, tcg_target_long offset) |
289 | c896fe29 | bellard | { |
290 | ac56dd48 | pbrook | tcg_gen_op3i(INDEX_op_ld_i32, ret, arg2, offset); |
291 | c896fe29 | bellard | } |
292 | c896fe29 | bellard | |
293 | ac56dd48 | pbrook | static inline void tcg_gen_st8_i32(TCGv arg1, TCGv arg2, tcg_target_long offset) |
294 | c896fe29 | bellard | { |
295 | ac56dd48 | pbrook | tcg_gen_op3i(INDEX_op_st8_i32, arg1, arg2, offset); |
296 | c896fe29 | bellard | } |
297 | c896fe29 | bellard | |
298 | ac56dd48 | pbrook | static inline void tcg_gen_st16_i32(TCGv arg1, TCGv arg2, tcg_target_long offset) |
299 | c896fe29 | bellard | { |
300 | ac56dd48 | pbrook | tcg_gen_op3i(INDEX_op_st16_i32, arg1, arg2, offset); |
301 | c896fe29 | bellard | } |
302 | c896fe29 | bellard | |
303 | ac56dd48 | pbrook | static inline void tcg_gen_st_i32(TCGv arg1, TCGv arg2, tcg_target_long offset) |
304 | c896fe29 | bellard | { |
305 | ac56dd48 | pbrook | tcg_gen_op3i(INDEX_op_st_i32, arg1, arg2, offset); |
306 | c896fe29 | bellard | } |
307 | c896fe29 | bellard | |
308 | ac56dd48 | pbrook | static inline void tcg_gen_add_i32(TCGv ret, TCGv arg1, TCGv arg2) |
309 | c896fe29 | bellard | { |
310 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_add_i32, ret, arg1, arg2); |
311 | c896fe29 | bellard | } |
312 | c896fe29 | bellard | |
313 | ac56dd48 | pbrook | static inline void tcg_gen_addi_i32(TCGv ret, TCGv arg1, int32_t arg2) |
314 | c896fe29 | bellard | { |
315 | 7089442c | blueswir1 | /* some cases can be optimized here */
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316 | 7089442c | blueswir1 | if (arg2 == 0) { |
317 | 7089442c | blueswir1 | tcg_gen_mov_i32(ret, arg1); |
318 | 7089442c | blueswir1 | } else {
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319 | 7089442c | blueswir1 | tcg_gen_add_i32(ret, arg1, tcg_const_i32(arg2)); |
320 | 7089442c | blueswir1 | } |
321 | c896fe29 | bellard | } |
322 | c896fe29 | bellard | |
323 | ac56dd48 | pbrook | static inline void tcg_gen_sub_i32(TCGv ret, TCGv arg1, TCGv arg2) |
324 | c896fe29 | bellard | { |
325 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_sub_i32, ret, arg1, arg2); |
326 | c896fe29 | bellard | } |
327 | c896fe29 | bellard | |
328 | ac56dd48 | pbrook | static inline void tcg_gen_subi_i32(TCGv ret, TCGv arg1, int32_t arg2) |
329 | c896fe29 | bellard | { |
330 | 7089442c | blueswir1 | /* some cases can be optimized here */
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331 | 7089442c | blueswir1 | if (arg2 == 0) { |
332 | 7089442c | blueswir1 | tcg_gen_mov_i32(ret, arg1); |
333 | 7089442c | blueswir1 | } else {
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334 | 7089442c | blueswir1 | tcg_gen_sub_i32(ret, arg1, tcg_const_i32(arg2)); |
335 | 7089442c | blueswir1 | } |
336 | c896fe29 | bellard | } |
337 | c896fe29 | bellard | |
338 | ac56dd48 | pbrook | static inline void tcg_gen_and_i32(TCGv ret, TCGv arg1, TCGv arg2) |
339 | c896fe29 | bellard | { |
340 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_and_i32, ret, arg1, arg2); |
341 | c896fe29 | bellard | } |
342 | c896fe29 | bellard | |
343 | ac56dd48 | pbrook | static inline void tcg_gen_andi_i32(TCGv ret, TCGv arg1, int32_t arg2) |
344 | c896fe29 | bellard | { |
345 | c896fe29 | bellard | /* some cases can be optimized here */
|
346 | c896fe29 | bellard | if (arg2 == 0) { |
347 | c896fe29 | bellard | tcg_gen_movi_i32(ret, 0);
|
348 | c896fe29 | bellard | } else if (arg2 == 0xffffffff) { |
349 | c896fe29 | bellard | tcg_gen_mov_i32(ret, arg1); |
350 | c896fe29 | bellard | } else {
|
351 | c896fe29 | bellard | tcg_gen_and_i32(ret, arg1, tcg_const_i32(arg2)); |
352 | c896fe29 | bellard | } |
353 | c896fe29 | bellard | } |
354 | c896fe29 | bellard | |
355 | ac56dd48 | pbrook | static inline void tcg_gen_or_i32(TCGv ret, TCGv arg1, TCGv arg2) |
356 | c896fe29 | bellard | { |
357 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_or_i32, ret, arg1, arg2); |
358 | c896fe29 | bellard | } |
359 | c896fe29 | bellard | |
360 | ac56dd48 | pbrook | static inline void tcg_gen_ori_i32(TCGv ret, TCGv arg1, int32_t arg2) |
361 | c896fe29 | bellard | { |
362 | c896fe29 | bellard | /* some cases can be optimized here */
|
363 | c896fe29 | bellard | if (arg2 == 0xffffffff) { |
364 | 7089442c | blueswir1 | tcg_gen_movi_i32(ret, 0xffffffff);
|
365 | c896fe29 | bellard | } else if (arg2 == 0) { |
366 | c896fe29 | bellard | tcg_gen_mov_i32(ret, arg1); |
367 | c896fe29 | bellard | } else {
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368 | c896fe29 | bellard | tcg_gen_or_i32(ret, arg1, tcg_const_i32(arg2)); |
369 | c896fe29 | bellard | } |
370 | c896fe29 | bellard | } |
371 | c896fe29 | bellard | |
372 | ac56dd48 | pbrook | static inline void tcg_gen_xor_i32(TCGv ret, TCGv arg1, TCGv arg2) |
373 | c896fe29 | bellard | { |
374 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_xor_i32, ret, arg1, arg2); |
375 | c896fe29 | bellard | } |
376 | c896fe29 | bellard | |
377 | ac56dd48 | pbrook | static inline void tcg_gen_xori_i32(TCGv ret, TCGv arg1, int32_t arg2) |
378 | c896fe29 | bellard | { |
379 | c896fe29 | bellard | /* some cases can be optimized here */
|
380 | c896fe29 | bellard | if (arg2 == 0) { |
381 | c896fe29 | bellard | tcg_gen_mov_i32(ret, arg1); |
382 | c896fe29 | bellard | } else {
|
383 | c896fe29 | bellard | tcg_gen_xor_i32(ret, arg1, tcg_const_i32(arg2)); |
384 | c896fe29 | bellard | } |
385 | c896fe29 | bellard | } |
386 | c896fe29 | bellard | |
387 | ac56dd48 | pbrook | static inline void tcg_gen_shl_i32(TCGv ret, TCGv arg1, TCGv arg2) |
388 | c896fe29 | bellard | { |
389 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_shl_i32, ret, arg1, arg2); |
390 | c896fe29 | bellard | } |
391 | c896fe29 | bellard | |
392 | ac56dd48 | pbrook | static inline void tcg_gen_shli_i32(TCGv ret, TCGv arg1, int32_t arg2) |
393 | c896fe29 | bellard | { |
394 | c896fe29 | bellard | tcg_gen_shl_i32(ret, arg1, tcg_const_i32(arg2)); |
395 | c896fe29 | bellard | } |
396 | c896fe29 | bellard | |
397 | ac56dd48 | pbrook | static inline void tcg_gen_shr_i32(TCGv ret, TCGv arg1, TCGv arg2) |
398 | c896fe29 | bellard | { |
399 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_shr_i32, ret, arg1, arg2); |
400 | c896fe29 | bellard | } |
401 | c896fe29 | bellard | |
402 | ac56dd48 | pbrook | static inline void tcg_gen_shri_i32(TCGv ret, TCGv arg1, int32_t arg2) |
403 | c896fe29 | bellard | { |
404 | c896fe29 | bellard | tcg_gen_shr_i32(ret, arg1, tcg_const_i32(arg2)); |
405 | c896fe29 | bellard | } |
406 | c896fe29 | bellard | |
407 | ac56dd48 | pbrook | static inline void tcg_gen_sar_i32(TCGv ret, TCGv arg1, TCGv arg2) |
408 | c896fe29 | bellard | { |
409 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_sar_i32, ret, arg1, arg2); |
410 | c896fe29 | bellard | } |
411 | c896fe29 | bellard | |
412 | ac56dd48 | pbrook | static inline void tcg_gen_sari_i32(TCGv ret, TCGv arg1, int32_t arg2) |
413 | c896fe29 | bellard | { |
414 | c896fe29 | bellard | tcg_gen_sar_i32(ret, arg1, tcg_const_i32(arg2)); |
415 | c896fe29 | bellard | } |
416 | c896fe29 | bellard | |
417 | ac56dd48 | pbrook | static inline void tcg_gen_brcond_i32(int cond, TCGv arg1, TCGv arg2, |
418 | c896fe29 | bellard | int label_index)
|
419 | c896fe29 | bellard | { |
420 | ac56dd48 | pbrook | tcg_gen_op4ii(INDEX_op_brcond_i32, arg1, arg2, cond, label_index); |
421 | c896fe29 | bellard | } |
422 | c896fe29 | bellard | |
423 | ac56dd48 | pbrook | static inline void tcg_gen_mul_i32(TCGv ret, TCGv arg1, TCGv arg2) |
424 | c896fe29 | bellard | { |
425 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_mul_i32, ret, arg1, arg2); |
426 | c896fe29 | bellard | } |
427 | c896fe29 | bellard | |
428 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_div_i32
|
429 | ac56dd48 | pbrook | static inline void tcg_gen_div_i32(TCGv ret, TCGv arg1, TCGv arg2) |
430 | c896fe29 | bellard | { |
431 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_div_i32, ret, arg1, arg2); |
432 | c896fe29 | bellard | } |
433 | c896fe29 | bellard | |
434 | ac56dd48 | pbrook | static inline void tcg_gen_rem_i32(TCGv ret, TCGv arg1, TCGv arg2) |
435 | c896fe29 | bellard | { |
436 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_rem_i32, ret, arg1, arg2); |
437 | c896fe29 | bellard | } |
438 | c896fe29 | bellard | |
439 | ac56dd48 | pbrook | static inline void tcg_gen_divu_i32(TCGv ret, TCGv arg1, TCGv arg2) |
440 | c896fe29 | bellard | { |
441 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_divu_i32, ret, arg1, arg2); |
442 | c896fe29 | bellard | } |
443 | c896fe29 | bellard | |
444 | ac56dd48 | pbrook | static inline void tcg_gen_remu_i32(TCGv ret, TCGv arg1, TCGv arg2) |
445 | c896fe29 | bellard | { |
446 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_remu_i32, ret, arg1, arg2); |
447 | c896fe29 | bellard | } |
448 | c896fe29 | bellard | #else
|
449 | ac56dd48 | pbrook | static inline void tcg_gen_div_i32(TCGv ret, TCGv arg1, TCGv arg2) |
450 | c896fe29 | bellard | { |
451 | ac56dd48 | pbrook | TCGv t0; |
452 | c896fe29 | bellard | t0 = tcg_temp_new(TCG_TYPE_I32); |
453 | c896fe29 | bellard | tcg_gen_sari_i32(t0, arg1, 31);
|
454 | c896fe29 | bellard | tcg_gen_op5(INDEX_op_div2_i32, ret, t0, arg1, t0, arg2); |
455 | c896fe29 | bellard | } |
456 | c896fe29 | bellard | |
457 | ac56dd48 | pbrook | static inline void tcg_gen_rem_i32(TCGv ret, TCGv arg1, TCGv arg2) |
458 | c896fe29 | bellard | { |
459 | ac56dd48 | pbrook | TCGv t0; |
460 | c896fe29 | bellard | t0 = tcg_temp_new(TCG_TYPE_I32); |
461 | c896fe29 | bellard | tcg_gen_sari_i32(t0, arg1, 31);
|
462 | c896fe29 | bellard | tcg_gen_op5(INDEX_op_div2_i32, t0, ret, arg1, t0, arg2); |
463 | c896fe29 | bellard | } |
464 | c896fe29 | bellard | |
465 | ac56dd48 | pbrook | static inline void tcg_gen_divu_i32(TCGv ret, TCGv arg1, TCGv arg2) |
466 | c896fe29 | bellard | { |
467 | ac56dd48 | pbrook | TCGv t0; |
468 | c896fe29 | bellard | t0 = tcg_temp_new(TCG_TYPE_I32); |
469 | c896fe29 | bellard | tcg_gen_movi_i32(t0, 0);
|
470 | c896fe29 | bellard | tcg_gen_op5(INDEX_op_divu2_i32, ret, t0, arg1, t0, arg2); |
471 | c896fe29 | bellard | } |
472 | c896fe29 | bellard | |
473 | ac56dd48 | pbrook | static inline void tcg_gen_remu_i32(TCGv ret, TCGv arg1, TCGv arg2) |
474 | c896fe29 | bellard | { |
475 | ac56dd48 | pbrook | TCGv t0; |
476 | c896fe29 | bellard | t0 = tcg_temp_new(TCG_TYPE_I32); |
477 | c896fe29 | bellard | tcg_gen_movi_i32(t0, 0);
|
478 | c896fe29 | bellard | tcg_gen_op5(INDEX_op_divu2_i32, t0, ret, arg1, t0, arg2); |
479 | c896fe29 | bellard | } |
480 | c896fe29 | bellard | #endif
|
481 | c896fe29 | bellard | |
482 | c896fe29 | bellard | #if TCG_TARGET_REG_BITS == 32 |
483 | c896fe29 | bellard | |
484 | ac56dd48 | pbrook | static inline void tcg_gen_mov_i64(TCGv ret, TCGv arg) |
485 | c896fe29 | bellard | { |
486 | c896fe29 | bellard | tcg_gen_mov_i32(ret, arg); |
487 | ac56dd48 | pbrook | tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); |
488 | c896fe29 | bellard | } |
489 | c896fe29 | bellard | |
490 | ac56dd48 | pbrook | static inline void tcg_gen_movi_i64(TCGv ret, int64_t arg) |
491 | c896fe29 | bellard | { |
492 | c896fe29 | bellard | tcg_gen_movi_i32(ret, arg); |
493 | ac56dd48 | pbrook | tcg_gen_movi_i32(TCGV_HIGH(ret), arg >> 32);
|
494 | c896fe29 | bellard | } |
495 | c896fe29 | bellard | |
496 | ac56dd48 | pbrook | static inline void tcg_gen_ld8u_i64(TCGv ret, TCGv arg2, tcg_target_long offset) |
497 | c896fe29 | bellard | { |
498 | c896fe29 | bellard | tcg_gen_ld8u_i32(ret, arg2, offset); |
499 | ac56dd48 | pbrook | tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
500 | c896fe29 | bellard | } |
501 | c896fe29 | bellard | |
502 | ac56dd48 | pbrook | static inline void tcg_gen_ld8s_i64(TCGv ret, TCGv arg2, tcg_target_long offset) |
503 | c896fe29 | bellard | { |
504 | c896fe29 | bellard | tcg_gen_ld8s_i32(ret, arg2, offset); |
505 | ac56dd48 | pbrook | tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
|
506 | c896fe29 | bellard | } |
507 | c896fe29 | bellard | |
508 | ac56dd48 | pbrook | static inline void tcg_gen_ld16u_i64(TCGv ret, TCGv arg2, tcg_target_long offset) |
509 | c896fe29 | bellard | { |
510 | c896fe29 | bellard | tcg_gen_ld16u_i32(ret, arg2, offset); |
511 | ac56dd48 | pbrook | tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
512 | c896fe29 | bellard | } |
513 | c896fe29 | bellard | |
514 | ac56dd48 | pbrook | static inline void tcg_gen_ld16s_i64(TCGv ret, TCGv arg2, tcg_target_long offset) |
515 | c896fe29 | bellard | { |
516 | c896fe29 | bellard | tcg_gen_ld16s_i32(ret, arg2, offset); |
517 | ac56dd48 | pbrook | tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
|
518 | c896fe29 | bellard | } |
519 | c896fe29 | bellard | |
520 | ac56dd48 | pbrook | static inline void tcg_gen_ld32u_i64(TCGv ret, TCGv arg2, tcg_target_long offset) |
521 | c896fe29 | bellard | { |
522 | c896fe29 | bellard | tcg_gen_ld_i32(ret, arg2, offset); |
523 | ac56dd48 | pbrook | tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
524 | c896fe29 | bellard | } |
525 | c896fe29 | bellard | |
526 | ac56dd48 | pbrook | static inline void tcg_gen_ld32s_i64(TCGv ret, TCGv arg2, tcg_target_long offset) |
527 | c896fe29 | bellard | { |
528 | c896fe29 | bellard | tcg_gen_ld_i32(ret, arg2, offset); |
529 | ac56dd48 | pbrook | tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
|
530 | c896fe29 | bellard | } |
531 | c896fe29 | bellard | |
532 | ac56dd48 | pbrook | static inline void tcg_gen_ld_i64(TCGv ret, TCGv arg2, tcg_target_long offset) |
533 | c896fe29 | bellard | { |
534 | c896fe29 | bellard | /* since arg2 and ret have different types, they cannot be the
|
535 | c896fe29 | bellard | same temporary */
|
536 | c896fe29 | bellard | #ifdef TCG_TARGET_WORDS_BIGENDIAN
|
537 | ac56dd48 | pbrook | tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset); |
538 | c896fe29 | bellard | tcg_gen_ld_i32(ret, arg2, offset + 4);
|
539 | c896fe29 | bellard | #else
|
540 | c896fe29 | bellard | tcg_gen_ld_i32(ret, arg2, offset); |
541 | ac56dd48 | pbrook | tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset + 4);
|
542 | c896fe29 | bellard | #endif
|
543 | c896fe29 | bellard | } |
544 | c896fe29 | bellard | |
545 | ac56dd48 | pbrook | static inline void tcg_gen_st8_i64(TCGv arg1, TCGv arg2, tcg_target_long offset) |
546 | c896fe29 | bellard | { |
547 | c896fe29 | bellard | tcg_gen_st8_i32(arg1, arg2, offset); |
548 | c896fe29 | bellard | } |
549 | c896fe29 | bellard | |
550 | ac56dd48 | pbrook | static inline void tcg_gen_st16_i64(TCGv arg1, TCGv arg2, tcg_target_long offset) |
551 | c896fe29 | bellard | { |
552 | c896fe29 | bellard | tcg_gen_st16_i32(arg1, arg2, offset); |
553 | c896fe29 | bellard | } |
554 | c896fe29 | bellard | |
555 | ac56dd48 | pbrook | static inline void tcg_gen_st32_i64(TCGv arg1, TCGv arg2, tcg_target_long offset) |
556 | c896fe29 | bellard | { |
557 | c896fe29 | bellard | tcg_gen_st_i32(arg1, arg2, offset); |
558 | c896fe29 | bellard | } |
559 | c896fe29 | bellard | |
560 | ac56dd48 | pbrook | static inline void tcg_gen_st_i64(TCGv arg1, TCGv arg2, tcg_target_long offset) |
561 | c896fe29 | bellard | { |
562 | c896fe29 | bellard | #ifdef TCG_TARGET_WORDS_BIGENDIAN
|
563 | ac56dd48 | pbrook | tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset); |
564 | c896fe29 | bellard | tcg_gen_st_i32(arg1, arg2, offset + 4);
|
565 | c896fe29 | bellard | #else
|
566 | c896fe29 | bellard | tcg_gen_st_i32(arg1, arg2, offset); |
567 | ac56dd48 | pbrook | tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset + 4);
|
568 | c896fe29 | bellard | #endif
|
569 | c896fe29 | bellard | } |
570 | c896fe29 | bellard | |
571 | ac56dd48 | pbrook | static inline void tcg_gen_add_i64(TCGv ret, TCGv arg1, TCGv arg2) |
572 | c896fe29 | bellard | { |
573 | ac56dd48 | pbrook | tcg_gen_op6(INDEX_op_add2_i32, ret, TCGV_HIGH(ret), |
574 | ac56dd48 | pbrook | arg1, TCGV_HIGH(arg1), arg2, TCGV_HIGH(arg2)); |
575 | c896fe29 | bellard | } |
576 | c896fe29 | bellard | |
577 | ac56dd48 | pbrook | static inline void tcg_gen_addi_i64(TCGv ret, TCGv arg1, int64_t arg2) |
578 | c896fe29 | bellard | { |
579 | c896fe29 | bellard | tcg_gen_add_i64(ret, arg1, tcg_const_i64(arg2)); |
580 | c896fe29 | bellard | } |
581 | c896fe29 | bellard | |
582 | ac56dd48 | pbrook | static inline void tcg_gen_sub_i64(TCGv ret, TCGv arg1, TCGv arg2) |
583 | c896fe29 | bellard | { |
584 | ac56dd48 | pbrook | tcg_gen_op6(INDEX_op_sub2_i32, ret, TCGV_HIGH(ret), |
585 | ac56dd48 | pbrook | arg1, TCGV_HIGH(arg1), arg2, TCGV_HIGH(arg2)); |
586 | c896fe29 | bellard | } |
587 | c896fe29 | bellard | |
588 | ac56dd48 | pbrook | static inline void tcg_gen_subi_i64(TCGv ret, TCGv arg1, int64_t arg2) |
589 | c896fe29 | bellard | { |
590 | c896fe29 | bellard | tcg_gen_sub_i64(ret, arg1, tcg_const_i64(arg2)); |
591 | c896fe29 | bellard | } |
592 | c896fe29 | bellard | |
593 | ac56dd48 | pbrook | static inline void tcg_gen_and_i64(TCGv ret, TCGv arg1, TCGv arg2) |
594 | c896fe29 | bellard | { |
595 | c896fe29 | bellard | tcg_gen_and_i32(ret, arg1, arg2); |
596 | ac56dd48 | pbrook | tcg_gen_and_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
597 | c896fe29 | bellard | } |
598 | c896fe29 | bellard | |
599 | ac56dd48 | pbrook | static inline void tcg_gen_andi_i64(TCGv ret, TCGv arg1, int64_t arg2) |
600 | c896fe29 | bellard | { |
601 | c896fe29 | bellard | tcg_gen_andi_i32(ret, arg1, arg2); |
602 | ac56dd48 | pbrook | tcg_gen_andi_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
|
603 | c896fe29 | bellard | } |
604 | c896fe29 | bellard | |
605 | ac56dd48 | pbrook | static inline void tcg_gen_or_i64(TCGv ret, TCGv arg1, TCGv arg2) |
606 | c896fe29 | bellard | { |
607 | c896fe29 | bellard | tcg_gen_or_i32(ret, arg1, arg2); |
608 | ac56dd48 | pbrook | tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
609 | c896fe29 | bellard | } |
610 | c896fe29 | bellard | |
611 | ac56dd48 | pbrook | static inline void tcg_gen_ori_i64(TCGv ret, TCGv arg1, int64_t arg2) |
612 | c896fe29 | bellard | { |
613 | c896fe29 | bellard | tcg_gen_ori_i32(ret, arg1, arg2); |
614 | ac56dd48 | pbrook | tcg_gen_ori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
|
615 | c896fe29 | bellard | } |
616 | c896fe29 | bellard | |
617 | ac56dd48 | pbrook | static inline void tcg_gen_xor_i64(TCGv ret, TCGv arg1, TCGv arg2) |
618 | c896fe29 | bellard | { |
619 | c896fe29 | bellard | tcg_gen_xor_i32(ret, arg1, arg2); |
620 | ac56dd48 | pbrook | tcg_gen_xor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
621 | c896fe29 | bellard | } |
622 | c896fe29 | bellard | |
623 | ac56dd48 | pbrook | static inline void tcg_gen_xori_i64(TCGv ret, TCGv arg1, int64_t arg2) |
624 | c896fe29 | bellard | { |
625 | c896fe29 | bellard | tcg_gen_xori_i32(ret, arg1, arg2); |
626 | ac56dd48 | pbrook | tcg_gen_xori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
|
627 | c896fe29 | bellard | } |
628 | c896fe29 | bellard | |
629 | c896fe29 | bellard | /* XXX: use generic code when basic block handling is OK or CPU
|
630 | c896fe29 | bellard | specific code (x86) */
|
631 | ac56dd48 | pbrook | static inline void tcg_gen_shl_i64(TCGv ret, TCGv arg1, TCGv arg2) |
632 | c896fe29 | bellard | { |
633 | c896fe29 | bellard | tcg_gen_helper_1_2(tcg_helper_shl_i64, ret, arg1, arg2); |
634 | c896fe29 | bellard | } |
635 | c896fe29 | bellard | |
636 | ac56dd48 | pbrook | static inline void tcg_gen_shli_i64(TCGv ret, TCGv arg1, int64_t arg2) |
637 | c896fe29 | bellard | { |
638 | c896fe29 | bellard | tcg_gen_shifti_i64(ret, arg1, arg2, 0, 0); |
639 | c896fe29 | bellard | } |
640 | c896fe29 | bellard | |
641 | ac56dd48 | pbrook | static inline void tcg_gen_shr_i64(TCGv ret, TCGv arg1, TCGv arg2) |
642 | c896fe29 | bellard | { |
643 | c896fe29 | bellard | tcg_gen_helper_1_2(tcg_helper_shr_i64, ret, arg1, arg2); |
644 | c896fe29 | bellard | } |
645 | c896fe29 | bellard | |
646 | ac56dd48 | pbrook | static inline void tcg_gen_shri_i64(TCGv ret, TCGv arg1, int64_t arg2) |
647 | c896fe29 | bellard | { |
648 | c896fe29 | bellard | tcg_gen_shifti_i64(ret, arg1, arg2, 1, 0); |
649 | c896fe29 | bellard | } |
650 | c896fe29 | bellard | |
651 | ac56dd48 | pbrook | static inline void tcg_gen_sar_i64(TCGv ret, TCGv arg1, TCGv arg2) |
652 | c896fe29 | bellard | { |
653 | c896fe29 | bellard | tcg_gen_helper_1_2(tcg_helper_sar_i64, ret, arg1, arg2); |
654 | c896fe29 | bellard | } |
655 | c896fe29 | bellard | |
656 | ac56dd48 | pbrook | static inline void tcg_gen_sari_i64(TCGv ret, TCGv arg1, int64_t arg2) |
657 | c896fe29 | bellard | { |
658 | c896fe29 | bellard | tcg_gen_shifti_i64(ret, arg1, arg2, 1, 1); |
659 | c896fe29 | bellard | } |
660 | c896fe29 | bellard | |
661 | ac56dd48 | pbrook | static inline void tcg_gen_brcond_i64(int cond, TCGv arg1, TCGv arg2, |
662 | c896fe29 | bellard | int label_index)
|
663 | c896fe29 | bellard | { |
664 | ac56dd48 | pbrook | tcg_gen_op6ii(INDEX_op_brcond2_i32, |
665 | ac56dd48 | pbrook | arg1, TCGV_HIGH(arg1), arg2, TCGV_HIGH(arg2), |
666 | ac56dd48 | pbrook | cond, label_index); |
667 | c896fe29 | bellard | } |
668 | c896fe29 | bellard | |
669 | ac56dd48 | pbrook | static inline void tcg_gen_mul_i64(TCGv ret, TCGv arg1, TCGv arg2) |
670 | c896fe29 | bellard | { |
671 | ac56dd48 | pbrook | TCGv t0, t1; |
672 | c896fe29 | bellard | |
673 | c896fe29 | bellard | t0 = tcg_temp_new(TCG_TYPE_I64); |
674 | c896fe29 | bellard | t1 = tcg_temp_new(TCG_TYPE_I32); |
675 | c896fe29 | bellard | |
676 | ac56dd48 | pbrook | tcg_gen_op4(INDEX_op_mulu2_i32, t0, TCGV_HIGH(t0), arg1, arg2); |
677 | c896fe29 | bellard | |
678 | ac56dd48 | pbrook | tcg_gen_mul_i32(t1, arg1, TCGV_HIGH(arg2)); |
679 | ac56dd48 | pbrook | tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1); |
680 | ac56dd48 | pbrook | tcg_gen_mul_i32(t1, TCGV_HIGH(arg1), arg2); |
681 | ac56dd48 | pbrook | tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1); |
682 | c896fe29 | bellard | |
683 | c896fe29 | bellard | tcg_gen_mov_i64(ret, t0); |
684 | c896fe29 | bellard | } |
685 | c896fe29 | bellard | |
686 | ac56dd48 | pbrook | static inline void tcg_gen_div_i64(TCGv ret, TCGv arg1, TCGv arg2) |
687 | c896fe29 | bellard | { |
688 | c896fe29 | bellard | tcg_gen_helper_1_2(tcg_helper_div_i64, ret, arg1, arg2); |
689 | c896fe29 | bellard | } |
690 | c896fe29 | bellard | |
691 | ac56dd48 | pbrook | static inline void tcg_gen_rem_i64(TCGv ret, TCGv arg1, TCGv arg2) |
692 | c896fe29 | bellard | { |
693 | c896fe29 | bellard | tcg_gen_helper_1_2(tcg_helper_rem_i64, ret, arg1, arg2); |
694 | c896fe29 | bellard | } |
695 | c896fe29 | bellard | |
696 | ac56dd48 | pbrook | static inline void tcg_gen_divu_i64(TCGv ret, TCGv arg1, TCGv arg2) |
697 | c896fe29 | bellard | { |
698 | c896fe29 | bellard | tcg_gen_helper_1_2(tcg_helper_divu_i64, ret, arg1, arg2); |
699 | c896fe29 | bellard | } |
700 | c896fe29 | bellard | |
701 | ac56dd48 | pbrook | static inline void tcg_gen_remu_i64(TCGv ret, TCGv arg1, TCGv arg2) |
702 | c896fe29 | bellard | { |
703 | c896fe29 | bellard | tcg_gen_helper_1_2(tcg_helper_remu_i64, ret, arg1, arg2); |
704 | c896fe29 | bellard | } |
705 | c896fe29 | bellard | |
706 | c896fe29 | bellard | #else
|
707 | c896fe29 | bellard | |
708 | ac56dd48 | pbrook | static inline void tcg_gen_mov_i64(TCGv ret, TCGv arg) |
709 | c896fe29 | bellard | { |
710 | c896fe29 | bellard | tcg_gen_op2(INDEX_op_mov_i64, ret, arg); |
711 | c896fe29 | bellard | } |
712 | c896fe29 | bellard | |
713 | ac56dd48 | pbrook | static inline void tcg_gen_movi_i64(TCGv ret, int64_t arg) |
714 | c896fe29 | bellard | { |
715 | ac56dd48 | pbrook | tcg_gen_op2i(INDEX_op_movi_i64, ret, arg); |
716 | c896fe29 | bellard | } |
717 | c896fe29 | bellard | |
718 | ac56dd48 | pbrook | static inline void tcg_gen_ld8u_i64(TCGv ret, TCGv arg2, |
719 | ac56dd48 | pbrook | tcg_target_long offset) |
720 | c896fe29 | bellard | { |
721 | ac56dd48 | pbrook | tcg_gen_op3i(INDEX_op_ld8u_i64, ret, arg2, offset); |
722 | c896fe29 | bellard | } |
723 | c896fe29 | bellard | |
724 | ac56dd48 | pbrook | static inline void tcg_gen_ld8s_i64(TCGv ret, TCGv arg2, |
725 | ac56dd48 | pbrook | tcg_target_long offset) |
726 | c896fe29 | bellard | { |
727 | ac56dd48 | pbrook | tcg_gen_op3i(INDEX_op_ld8s_i64, ret, arg2, offset); |
728 | c896fe29 | bellard | } |
729 | c896fe29 | bellard | |
730 | ac56dd48 | pbrook | static inline void tcg_gen_ld16u_i64(TCGv ret, TCGv arg2, |
731 | ac56dd48 | pbrook | tcg_target_long offset) |
732 | c896fe29 | bellard | { |
733 | ac56dd48 | pbrook | tcg_gen_op3i(INDEX_op_ld16u_i64, ret, arg2, offset); |
734 | c896fe29 | bellard | } |
735 | c896fe29 | bellard | |
736 | ac56dd48 | pbrook | static inline void tcg_gen_ld16s_i64(TCGv ret, TCGv arg2, |
737 | ac56dd48 | pbrook | tcg_target_long offset) |
738 | c896fe29 | bellard | { |
739 | ac56dd48 | pbrook | tcg_gen_op3i(INDEX_op_ld16s_i64, ret, arg2, offset); |
740 | c896fe29 | bellard | } |
741 | c896fe29 | bellard | |
742 | ac56dd48 | pbrook | static inline void tcg_gen_ld32u_i64(TCGv ret, TCGv arg2, |
743 | ac56dd48 | pbrook | tcg_target_long offset) |
744 | c896fe29 | bellard | { |
745 | ac56dd48 | pbrook | tcg_gen_op3i(INDEX_op_ld32u_i64, ret, arg2, offset); |
746 | c896fe29 | bellard | } |
747 | c896fe29 | bellard | |
748 | ac56dd48 | pbrook | static inline void tcg_gen_ld32s_i64(TCGv ret, TCGv arg2, |
749 | ac56dd48 | pbrook | tcg_target_long offset) |
750 | c896fe29 | bellard | { |
751 | ac56dd48 | pbrook | tcg_gen_op3i(INDEX_op_ld32s_i64, ret, arg2, offset); |
752 | c896fe29 | bellard | } |
753 | c896fe29 | bellard | |
754 | ac56dd48 | pbrook | static inline void tcg_gen_ld_i64(TCGv ret, TCGv arg2, tcg_target_long offset) |
755 | c896fe29 | bellard | { |
756 | ac56dd48 | pbrook | tcg_gen_op3i(INDEX_op_ld_i64, ret, arg2, offset); |
757 | c896fe29 | bellard | } |
758 | c896fe29 | bellard | |
759 | ac56dd48 | pbrook | static inline void tcg_gen_st8_i64(TCGv arg1, TCGv arg2, |
760 | ac56dd48 | pbrook | tcg_target_long offset) |
761 | c896fe29 | bellard | { |
762 | ac56dd48 | pbrook | tcg_gen_op3i(INDEX_op_st8_i64, arg1, arg2, offset); |
763 | c896fe29 | bellard | } |
764 | c896fe29 | bellard | |
765 | ac56dd48 | pbrook | static inline void tcg_gen_st16_i64(TCGv arg1, TCGv arg2, |
766 | ac56dd48 | pbrook | tcg_target_long offset) |
767 | c896fe29 | bellard | { |
768 | ac56dd48 | pbrook | tcg_gen_op3i(INDEX_op_st16_i64, arg1, arg2, offset); |
769 | c896fe29 | bellard | } |
770 | c896fe29 | bellard | |
771 | ac56dd48 | pbrook | static inline void tcg_gen_st32_i64(TCGv arg1, TCGv arg2, |
772 | ac56dd48 | pbrook | tcg_target_long offset) |
773 | c896fe29 | bellard | { |
774 | ac56dd48 | pbrook | tcg_gen_op3i(INDEX_op_st32_i64, arg1, arg2, offset); |
775 | c896fe29 | bellard | } |
776 | c896fe29 | bellard | |
777 | ac56dd48 | pbrook | static inline void tcg_gen_st_i64(TCGv arg1, TCGv arg2, tcg_target_long offset) |
778 | c896fe29 | bellard | { |
779 | ac56dd48 | pbrook | tcg_gen_op3i(INDEX_op_st_i64, arg1, arg2, offset); |
780 | c896fe29 | bellard | } |
781 | c896fe29 | bellard | |
782 | ac56dd48 | pbrook | static inline void tcg_gen_add_i64(TCGv ret, TCGv arg1, TCGv arg2) |
783 | c896fe29 | bellard | { |
784 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_add_i64, ret, arg1, arg2); |
785 | c896fe29 | bellard | } |
786 | c896fe29 | bellard | |
787 | ac56dd48 | pbrook | static inline void tcg_gen_addi_i64(TCGv ret, TCGv arg1, int64_t arg2) |
788 | c896fe29 | bellard | { |
789 | c896fe29 | bellard | tcg_gen_add_i64(ret, arg1, tcg_const_i64(arg2)); |
790 | c896fe29 | bellard | } |
791 | c896fe29 | bellard | |
792 | ac56dd48 | pbrook | static inline void tcg_gen_sub_i64(TCGv ret, TCGv arg1, TCGv arg2) |
793 | c896fe29 | bellard | { |
794 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_sub_i64, ret, arg1, arg2); |
795 | c896fe29 | bellard | } |
796 | c896fe29 | bellard | |
797 | ac56dd48 | pbrook | static inline void tcg_gen_subi_i64(TCGv ret, TCGv arg1, int64_t arg2) |
798 | c896fe29 | bellard | { |
799 | c896fe29 | bellard | tcg_gen_sub_i64(ret, arg1, tcg_const_i64(arg2)); |
800 | c896fe29 | bellard | } |
801 | c896fe29 | bellard | |
802 | ac56dd48 | pbrook | static inline void tcg_gen_and_i64(TCGv ret, TCGv arg1, TCGv arg2) |
803 | c896fe29 | bellard | { |
804 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_and_i64, ret, arg1, arg2); |
805 | c896fe29 | bellard | } |
806 | c896fe29 | bellard | |
807 | ac56dd48 | pbrook | static inline void tcg_gen_andi_i64(TCGv ret, TCGv arg1, int64_t arg2) |
808 | c896fe29 | bellard | { |
809 | c896fe29 | bellard | tcg_gen_and_i64(ret, arg1, tcg_const_i64(arg2)); |
810 | c896fe29 | bellard | } |
811 | c896fe29 | bellard | |
812 | ac56dd48 | pbrook | static inline void tcg_gen_or_i64(TCGv ret, TCGv arg1, TCGv arg2) |
813 | c896fe29 | bellard | { |
814 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_or_i64, ret, arg1, arg2); |
815 | c896fe29 | bellard | } |
816 | c896fe29 | bellard | |
817 | ac56dd48 | pbrook | static inline void tcg_gen_ori_i64(TCGv ret, TCGv arg1, int64_t arg2) |
818 | c896fe29 | bellard | { |
819 | c896fe29 | bellard | tcg_gen_or_i64(ret, arg1, tcg_const_i64(arg2)); |
820 | c896fe29 | bellard | } |
821 | c896fe29 | bellard | |
822 | ac56dd48 | pbrook | static inline void tcg_gen_xor_i64(TCGv ret, TCGv arg1, TCGv arg2) |
823 | c896fe29 | bellard | { |
824 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_xor_i64, ret, arg1, arg2); |
825 | c896fe29 | bellard | } |
826 | c896fe29 | bellard | |
827 | ac56dd48 | pbrook | static inline void tcg_gen_xori_i64(TCGv ret, TCGv arg1, int64_t arg2) |
828 | c896fe29 | bellard | { |
829 | c896fe29 | bellard | tcg_gen_xor_i64(ret, arg1, tcg_const_i64(arg2)); |
830 | c896fe29 | bellard | } |
831 | c896fe29 | bellard | |
832 | ac56dd48 | pbrook | static inline void tcg_gen_shl_i64(TCGv ret, TCGv arg1, TCGv arg2) |
833 | c896fe29 | bellard | { |
834 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_shl_i64, ret, arg1, arg2); |
835 | c896fe29 | bellard | } |
836 | c896fe29 | bellard | |
837 | ac56dd48 | pbrook | static inline void tcg_gen_shli_i64(TCGv ret, TCGv arg1, int64_t arg2) |
838 | c896fe29 | bellard | { |
839 | c896fe29 | bellard | tcg_gen_shl_i64(ret, arg1, tcg_const_i64(arg2)); |
840 | c896fe29 | bellard | } |
841 | c896fe29 | bellard | |
842 | ac56dd48 | pbrook | static inline void tcg_gen_shr_i64(TCGv ret, TCGv arg1, TCGv arg2) |
843 | c896fe29 | bellard | { |
844 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_shr_i64, ret, arg1, arg2); |
845 | c896fe29 | bellard | } |
846 | c896fe29 | bellard | |
847 | ac56dd48 | pbrook | static inline void tcg_gen_shri_i64(TCGv ret, TCGv arg1, int64_t arg2) |
848 | c896fe29 | bellard | { |
849 | c896fe29 | bellard | tcg_gen_shr_i64(ret, arg1, tcg_const_i64(arg2)); |
850 | c896fe29 | bellard | } |
851 | c896fe29 | bellard | |
852 | ac56dd48 | pbrook | static inline void tcg_gen_sar_i64(TCGv ret, TCGv arg1, TCGv arg2) |
853 | c896fe29 | bellard | { |
854 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_sar_i64, ret, arg1, arg2); |
855 | c896fe29 | bellard | } |
856 | c896fe29 | bellard | |
857 | ac56dd48 | pbrook | static inline void tcg_gen_sari_i64(TCGv ret, TCGv arg1, int64_t arg2) |
858 | c896fe29 | bellard | { |
859 | c896fe29 | bellard | tcg_gen_sar_i64(ret, arg1, tcg_const_i64(arg2)); |
860 | c896fe29 | bellard | } |
861 | c896fe29 | bellard | |
862 | ac56dd48 | pbrook | static inline void tcg_gen_brcond_i64(int cond, TCGv arg1, TCGv arg2, |
863 | c896fe29 | bellard | int label_index)
|
864 | c896fe29 | bellard | { |
865 | ac56dd48 | pbrook | tcg_gen_op4ii(INDEX_op_brcond_i64, arg1, arg2, cond, label_index); |
866 | c896fe29 | bellard | } |
867 | c896fe29 | bellard | |
868 | ac56dd48 | pbrook | static inline void tcg_gen_mul_i64(TCGv ret, TCGv arg1, TCGv arg2) |
869 | c896fe29 | bellard | { |
870 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_mul_i64, ret, arg1, arg2); |
871 | c896fe29 | bellard | } |
872 | c896fe29 | bellard | |
873 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_div_i64
|
874 | ac56dd48 | pbrook | static inline void tcg_gen_div_i64(TCGv ret, TCGv arg1, TCGv arg2) |
875 | c896fe29 | bellard | { |
876 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_div_i64, ret, arg1, arg2); |
877 | c896fe29 | bellard | } |
878 | c896fe29 | bellard | |
879 | ac56dd48 | pbrook | static inline void tcg_gen_rem_i64(TCGv ret, TCGv arg1, TCGv arg2) |
880 | c896fe29 | bellard | { |
881 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_rem_i64, ret, arg1, arg2); |
882 | c896fe29 | bellard | } |
883 | c896fe29 | bellard | |
884 | ac56dd48 | pbrook | static inline void tcg_gen_divu_i64(TCGv ret, TCGv arg1, TCGv arg2) |
885 | c896fe29 | bellard | { |
886 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_divu_i64, ret, arg1, arg2); |
887 | c896fe29 | bellard | } |
888 | c896fe29 | bellard | |
889 | ac56dd48 | pbrook | static inline void tcg_gen_remu_i64(TCGv ret, TCGv arg1, TCGv arg2) |
890 | c896fe29 | bellard | { |
891 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_remu_i64, ret, arg1, arg2); |
892 | c896fe29 | bellard | } |
893 | c896fe29 | bellard | #else
|
894 | ac56dd48 | pbrook | static inline void tcg_gen_div_i64(TCGv ret, TCGv arg1, TCGv arg2) |
895 | c896fe29 | bellard | { |
896 | ac56dd48 | pbrook | TCGv t0; |
897 | c896fe29 | bellard | t0 = tcg_temp_new(TCG_TYPE_I64); |
898 | c896fe29 | bellard | tcg_gen_sari_i64(t0, arg1, 63);
|
899 | c896fe29 | bellard | tcg_gen_op5(INDEX_op_div2_i64, ret, t0, arg1, t0, arg2); |
900 | c896fe29 | bellard | } |
901 | c896fe29 | bellard | |
902 | ac56dd48 | pbrook | static inline void tcg_gen_rem_i64(TCGv ret, TCGv arg1, TCGv arg2) |
903 | c896fe29 | bellard | { |
904 | ac56dd48 | pbrook | TCGv t0; |
905 | c896fe29 | bellard | t0 = tcg_temp_new(TCG_TYPE_I64); |
906 | c896fe29 | bellard | tcg_gen_sari_i64(t0, arg1, 63);
|
907 | c896fe29 | bellard | tcg_gen_op5(INDEX_op_div2_i64, t0, ret, arg1, t0, arg2); |
908 | c896fe29 | bellard | } |
909 | c896fe29 | bellard | |
910 | ac56dd48 | pbrook | static inline void tcg_gen_divu_i64(TCGv ret, TCGv arg1, TCGv arg2) |
911 | c896fe29 | bellard | { |
912 | ac56dd48 | pbrook | TCGv t0; |
913 | c896fe29 | bellard | t0 = tcg_temp_new(TCG_TYPE_I64); |
914 | c896fe29 | bellard | tcg_gen_movi_i64(t0, 0);
|
915 | c896fe29 | bellard | tcg_gen_op5(INDEX_op_divu2_i64, ret, t0, arg1, t0, arg2); |
916 | c896fe29 | bellard | } |
917 | c896fe29 | bellard | |
918 | ac56dd48 | pbrook | static inline void tcg_gen_remu_i64(TCGv ret, TCGv arg1, TCGv arg2) |
919 | c896fe29 | bellard | { |
920 | ac56dd48 | pbrook | TCGv t0; |
921 | c896fe29 | bellard | t0 = tcg_temp_new(TCG_TYPE_I64); |
922 | c896fe29 | bellard | tcg_gen_movi_i64(t0, 0);
|
923 | c896fe29 | bellard | tcg_gen_op5(INDEX_op_divu2_i64, t0, ret, arg1, t0, arg2); |
924 | c896fe29 | bellard | } |
925 | c896fe29 | bellard | #endif
|
926 | c896fe29 | bellard | |
927 | c896fe29 | bellard | #endif
|
928 | c896fe29 | bellard | |
929 | c896fe29 | bellard | /***************************************/
|
930 | c896fe29 | bellard | /* optional operations */
|
931 | c896fe29 | bellard | |
932 | ac56dd48 | pbrook | static inline void tcg_gen_ext8s_i32(TCGv ret, TCGv arg) |
933 | c896fe29 | bellard | { |
934 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_ext8s_i32
|
935 | c896fe29 | bellard | tcg_gen_op2(INDEX_op_ext8s_i32, ret, arg); |
936 | c896fe29 | bellard | #else
|
937 | c896fe29 | bellard | tcg_gen_shli_i32(ret, arg, 24);
|
938 | 5ff9d6a4 | bellard | tcg_gen_sari_i32(ret, ret, 24);
|
939 | c896fe29 | bellard | #endif
|
940 | c896fe29 | bellard | } |
941 | c896fe29 | bellard | |
942 | ac56dd48 | pbrook | static inline void tcg_gen_ext16s_i32(TCGv ret, TCGv arg) |
943 | c896fe29 | bellard | { |
944 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_ext16s_i32
|
945 | c896fe29 | bellard | tcg_gen_op2(INDEX_op_ext16s_i32, ret, arg); |
946 | c896fe29 | bellard | #else
|
947 | c896fe29 | bellard | tcg_gen_shli_i32(ret, arg, 16);
|
948 | 5ff9d6a4 | bellard | tcg_gen_sari_i32(ret, ret, 16);
|
949 | c896fe29 | bellard | #endif
|
950 | c896fe29 | bellard | } |
951 | c896fe29 | bellard | |
952 | c896fe29 | bellard | /* Note: we assume the two high bytes are set to zero */
|
953 | ac56dd48 | pbrook | static inline void tcg_gen_bswap16_i32(TCGv ret, TCGv arg) |
954 | c896fe29 | bellard | { |
955 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_bswap16_i32
|
956 | c896fe29 | bellard | tcg_gen_op2(INDEX_op_bswap16_i32, ret, arg); |
957 | c896fe29 | bellard | #else
|
958 | ac56dd48 | pbrook | TCGv t0, t1; |
959 | c896fe29 | bellard | t0 = tcg_temp_new(TCG_TYPE_I32); |
960 | c896fe29 | bellard | t1 = tcg_temp_new(TCG_TYPE_I32); |
961 | c896fe29 | bellard | |
962 | c896fe29 | bellard | tcg_gen_shri_i32(t0, arg, 8);
|
963 | c896fe29 | bellard | tcg_gen_andi_i32(t1, arg, 0x000000ff);
|
964 | c896fe29 | bellard | tcg_gen_shli_i32(t1, t1, 8);
|
965 | c896fe29 | bellard | tcg_gen_or_i32(ret, t0, t1); |
966 | c896fe29 | bellard | #endif
|
967 | c896fe29 | bellard | } |
968 | c896fe29 | bellard | |
969 | ac56dd48 | pbrook | static inline void tcg_gen_bswap_i32(TCGv ret, TCGv arg) |
970 | c896fe29 | bellard | { |
971 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_bswap_i32
|
972 | c896fe29 | bellard | tcg_gen_op2(INDEX_op_bswap_i32, ret, arg); |
973 | c896fe29 | bellard | #else
|
974 | ac56dd48 | pbrook | TCGv t0, t1; |
975 | c896fe29 | bellard | t0 = tcg_temp_new(TCG_TYPE_I32); |
976 | c896fe29 | bellard | t1 = tcg_temp_new(TCG_TYPE_I32); |
977 | c896fe29 | bellard | |
978 | c896fe29 | bellard | tcg_gen_shli_i32(t0, arg, 24);
|
979 | c896fe29 | bellard | |
980 | c896fe29 | bellard | tcg_gen_andi_i32(t1, arg, 0x0000ff00);
|
981 | c896fe29 | bellard | tcg_gen_shli_i32(t1, t1, 8);
|
982 | c896fe29 | bellard | tcg_gen_or_i32(t0, t0, t1); |
983 | c896fe29 | bellard | |
984 | c896fe29 | bellard | tcg_gen_shri_i32(t1, arg, 8);
|
985 | c896fe29 | bellard | tcg_gen_andi_i32(t1, t1, 0x0000ff00);
|
986 | c896fe29 | bellard | tcg_gen_or_i32(t0, t0, t1); |
987 | c896fe29 | bellard | |
988 | c896fe29 | bellard | tcg_gen_shri_i32(t1, arg, 24);
|
989 | c896fe29 | bellard | tcg_gen_or_i32(ret, t0, t1); |
990 | c896fe29 | bellard | #endif
|
991 | c896fe29 | bellard | } |
992 | c896fe29 | bellard | |
993 | c896fe29 | bellard | #if TCG_TARGET_REG_BITS == 32 |
994 | ac56dd48 | pbrook | static inline void tcg_gen_ext8s_i64(TCGv ret, TCGv arg) |
995 | c896fe29 | bellard | { |
996 | c896fe29 | bellard | tcg_gen_ext8s_i32(ret, arg); |
997 | ac56dd48 | pbrook | tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
|
998 | c896fe29 | bellard | } |
999 | c896fe29 | bellard | |
1000 | ac56dd48 | pbrook | static inline void tcg_gen_ext16s_i64(TCGv ret, TCGv arg) |
1001 | c896fe29 | bellard | { |
1002 | c896fe29 | bellard | tcg_gen_ext16s_i32(ret, arg); |
1003 | ac56dd48 | pbrook | tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
|
1004 | c896fe29 | bellard | } |
1005 | c896fe29 | bellard | |
1006 | ac56dd48 | pbrook | static inline void tcg_gen_ext32s_i64(TCGv ret, TCGv arg) |
1007 | c896fe29 | bellard | { |
1008 | c896fe29 | bellard | tcg_gen_mov_i32(ret, arg); |
1009 | ac56dd48 | pbrook | tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
|
1010 | c896fe29 | bellard | } |
1011 | c896fe29 | bellard | |
1012 | ac56dd48 | pbrook | static inline void tcg_gen_trunc_i64_i32(TCGv ret, TCGv arg) |
1013 | c896fe29 | bellard | { |
1014 | c896fe29 | bellard | tcg_gen_mov_i32(ret, arg); |
1015 | c896fe29 | bellard | } |
1016 | c896fe29 | bellard | |
1017 | ac56dd48 | pbrook | static inline void tcg_gen_extu_i32_i64(TCGv ret, TCGv arg) |
1018 | c896fe29 | bellard | { |
1019 | c896fe29 | bellard | tcg_gen_mov_i32(ret, arg); |
1020 | ac56dd48 | pbrook | tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
1021 | c896fe29 | bellard | } |
1022 | c896fe29 | bellard | |
1023 | ac56dd48 | pbrook | static inline void tcg_gen_ext_i32_i64(TCGv ret, TCGv arg) |
1024 | c896fe29 | bellard | { |
1025 | c896fe29 | bellard | tcg_gen_mov_i32(ret, arg); |
1026 | ac56dd48 | pbrook | tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
|
1027 | c896fe29 | bellard | } |
1028 | c896fe29 | bellard | |
1029 | ac56dd48 | pbrook | static inline void tcg_gen_bswap_i64(TCGv ret, TCGv arg) |
1030 | c896fe29 | bellard | { |
1031 | ac56dd48 | pbrook | TCGv t0, t1; |
1032 | c896fe29 | bellard | t0 = tcg_temp_new(TCG_TYPE_I32); |
1033 | c896fe29 | bellard | t1 = tcg_temp_new(TCG_TYPE_I32); |
1034 | c896fe29 | bellard | |
1035 | c896fe29 | bellard | tcg_gen_bswap_i32(t0, arg); |
1036 | ac56dd48 | pbrook | tcg_gen_bswap_i32(t1, TCGV_HIGH(arg)); |
1037 | c896fe29 | bellard | tcg_gen_mov_i32(ret, t1); |
1038 | ac56dd48 | pbrook | tcg_gen_mov_i32(TCGV_HIGH(ret), t0); |
1039 | c896fe29 | bellard | } |
1040 | c896fe29 | bellard | #else
|
1041 | c896fe29 | bellard | |
1042 | ac56dd48 | pbrook | static inline void tcg_gen_ext8s_i64(TCGv ret, TCGv arg) |
1043 | c896fe29 | bellard | { |
1044 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_ext8s_i64
|
1045 | c896fe29 | bellard | tcg_gen_op2(INDEX_op_ext8s_i64, ret, arg); |
1046 | c896fe29 | bellard | #else
|
1047 | c896fe29 | bellard | tcg_gen_shli_i64(ret, arg, 56);
|
1048 | 5ff9d6a4 | bellard | tcg_gen_sari_i64(ret, ret, 56);
|
1049 | c896fe29 | bellard | #endif
|
1050 | c896fe29 | bellard | } |
1051 | c896fe29 | bellard | |
1052 | ac56dd48 | pbrook | static inline void tcg_gen_ext16s_i64(TCGv ret, TCGv arg) |
1053 | c896fe29 | bellard | { |
1054 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_ext16s_i64
|
1055 | c896fe29 | bellard | tcg_gen_op2(INDEX_op_ext16s_i64, ret, arg); |
1056 | c896fe29 | bellard | #else
|
1057 | c896fe29 | bellard | tcg_gen_shli_i64(ret, arg, 48);
|
1058 | 5ff9d6a4 | bellard | tcg_gen_sari_i64(ret, ret, 48);
|
1059 | c896fe29 | bellard | #endif
|
1060 | c896fe29 | bellard | } |
1061 | c896fe29 | bellard | |
1062 | ac56dd48 | pbrook | static inline void tcg_gen_ext32s_i64(TCGv ret, TCGv arg) |
1063 | c896fe29 | bellard | { |
1064 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_ext32s_i64
|
1065 | c896fe29 | bellard | tcg_gen_op2(INDEX_op_ext32s_i64, ret, arg); |
1066 | c896fe29 | bellard | #else
|
1067 | c896fe29 | bellard | tcg_gen_shli_i64(ret, arg, 32);
|
1068 | 5ff9d6a4 | bellard | tcg_gen_sari_i64(ret, ret, 32);
|
1069 | c896fe29 | bellard | #endif
|
1070 | c896fe29 | bellard | } |
1071 | c896fe29 | bellard | |
1072 | c896fe29 | bellard | /* Note: we assume the target supports move between 32 and 64 bit
|
1073 | ac56dd48 | pbrook | registers. This will probably break MIPS64 targets. */
|
1074 | ac56dd48 | pbrook | static inline void tcg_gen_trunc_i64_i32(TCGv ret, TCGv arg) |
1075 | c896fe29 | bellard | { |
1076 | c896fe29 | bellard | tcg_gen_mov_i32(ret, arg); |
1077 | c896fe29 | bellard | } |
1078 | c896fe29 | bellard | |
1079 | c896fe29 | bellard | /* Note: we assume the target supports move between 32 and 64 bit
|
1080 | c896fe29 | bellard | registers */
|
1081 | ac56dd48 | pbrook | static inline void tcg_gen_extu_i32_i64(TCGv ret, TCGv arg) |
1082 | c896fe29 | bellard | { |
1083 | c896fe29 | bellard | tcg_gen_andi_i64(ret, arg, 0xffffffff);
|
1084 | c896fe29 | bellard | } |
1085 | c896fe29 | bellard | |
1086 | c896fe29 | bellard | /* Note: we assume the target supports move between 32 and 64 bit
|
1087 | c896fe29 | bellard | registers */
|
1088 | ac56dd48 | pbrook | static inline void tcg_gen_ext_i32_i64(TCGv ret, TCGv arg) |
1089 | c896fe29 | bellard | { |
1090 | c896fe29 | bellard | tcg_gen_ext32s_i64(ret, arg); |
1091 | c896fe29 | bellard | } |
1092 | c896fe29 | bellard | |
1093 | ac56dd48 | pbrook | static inline void tcg_gen_bswap_i64(TCGv ret, TCGv arg) |
1094 | c896fe29 | bellard | { |
1095 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_bswap_i64
|
1096 | c896fe29 | bellard | tcg_gen_op2(INDEX_op_bswap_i64, ret, arg); |
1097 | c896fe29 | bellard | #else
|
1098 | ac56dd48 | pbrook | TCGv t0, t1; |
1099 | c896fe29 | bellard | t0 = tcg_temp_new(TCG_TYPE_I32); |
1100 | c896fe29 | bellard | t1 = tcg_temp_new(TCG_TYPE_I32); |
1101 | c896fe29 | bellard | |
1102 | c896fe29 | bellard | tcg_gen_shli_i64(t0, arg, 56);
|
1103 | c896fe29 | bellard | |
1104 | c896fe29 | bellard | tcg_gen_andi_i64(t1, arg, 0x0000ff00);
|
1105 | c896fe29 | bellard | tcg_gen_shli_i64(t1, t1, 40);
|
1106 | c896fe29 | bellard | tcg_gen_or_i64(t0, t0, t1); |
1107 | c896fe29 | bellard | |
1108 | c896fe29 | bellard | tcg_gen_andi_i64(t1, arg, 0x00ff0000);
|
1109 | c896fe29 | bellard | tcg_gen_shli_i64(t1, t1, 24);
|
1110 | c896fe29 | bellard | tcg_gen_or_i64(t0, t0, t1); |
1111 | c896fe29 | bellard | |
1112 | c896fe29 | bellard | tcg_gen_andi_i64(t1, arg, 0xff000000);
|
1113 | c896fe29 | bellard | tcg_gen_shli_i64(t1, t1, 8);
|
1114 | c896fe29 | bellard | tcg_gen_or_i64(t0, t0, t1); |
1115 | c896fe29 | bellard | |
1116 | c896fe29 | bellard | tcg_gen_shri_i64(t1, arg, 8);
|
1117 | c896fe29 | bellard | tcg_gen_andi_i64(t1, t1, 0xff000000);
|
1118 | c896fe29 | bellard | tcg_gen_or_i64(t0, t0, t1); |
1119 | c896fe29 | bellard | |
1120 | c896fe29 | bellard | tcg_gen_shri_i64(t1, arg, 24);
|
1121 | c896fe29 | bellard | tcg_gen_andi_i64(t1, t1, 0x00ff0000);
|
1122 | c896fe29 | bellard | tcg_gen_or_i64(t0, t0, t1); |
1123 | c896fe29 | bellard | |
1124 | c896fe29 | bellard | tcg_gen_shri_i64(t1, arg, 40);
|
1125 | c896fe29 | bellard | tcg_gen_andi_i64(t1, t1, 0x0000ff00);
|
1126 | c896fe29 | bellard | tcg_gen_or_i64(t0, t0, t1); |
1127 | c896fe29 | bellard | |
1128 | c896fe29 | bellard | tcg_gen_shri_i64(t1, arg, 56);
|
1129 | c896fe29 | bellard | tcg_gen_or_i64(ret, t0, t1); |
1130 | c896fe29 | bellard | #endif
|
1131 | c896fe29 | bellard | } |
1132 | c896fe29 | bellard | |
1133 | c896fe29 | bellard | #endif
|
1134 | c896fe29 | bellard | |
1135 | 5ff9d6a4 | bellard | |
1136 | 5ff9d6a4 | bellard | static inline void tcg_gen_discard_i32(TCGv arg) |
1137 | 5ff9d6a4 | bellard | { |
1138 | 5ff9d6a4 | bellard | tcg_gen_op1(INDEX_op_discard, arg); |
1139 | 5ff9d6a4 | bellard | } |
1140 | 5ff9d6a4 | bellard | |
1141 | 5ff9d6a4 | bellard | #if TCG_TARGET_REG_BITS == 32 |
1142 | 5ff9d6a4 | bellard | static inline void tcg_gen_discard_i64(TCGv arg) |
1143 | 5ff9d6a4 | bellard | { |
1144 | 5ff9d6a4 | bellard | tcg_gen_discard_i32(arg); |
1145 | 5ff9d6a4 | bellard | tcg_gen_discard_i32(TCGV_HIGH(arg)); |
1146 | 5ff9d6a4 | bellard | } |
1147 | 5ff9d6a4 | bellard | #else
|
1148 | 5ff9d6a4 | bellard | static inline void tcg_gen_discard_i64(TCGv arg) |
1149 | 5ff9d6a4 | bellard | { |
1150 | 5ff9d6a4 | bellard | tcg_gen_op1(INDEX_op_discard, arg); |
1151 | 5ff9d6a4 | bellard | } |
1152 | 5ff9d6a4 | bellard | #endif
|
1153 | 5ff9d6a4 | bellard | |
1154 | c896fe29 | bellard | /***************************************/
|
1155 | ac56dd48 | pbrook | static inline void tcg_gen_macro_2(TCGv ret0, TCGv ret1, int macro_id) |
1156 | c896fe29 | bellard | { |
1157 | ac56dd48 | pbrook | tcg_gen_op3i(INDEX_op_macro_2, ret0, ret1, macro_id); |
1158 | c896fe29 | bellard | } |
1159 | c896fe29 | bellard | |
1160 | c896fe29 | bellard | /***************************************/
|
1161 | c896fe29 | bellard | /* QEMU specific operations. Their type depend on the QEMU CPU
|
1162 | c896fe29 | bellard | type. */
|
1163 | c896fe29 | bellard | #ifndef TARGET_LONG_BITS
|
1164 | c896fe29 | bellard | #error must include QEMU headers
|
1165 | c896fe29 | bellard | #endif
|
1166 | c896fe29 | bellard | |
1167 | c896fe29 | bellard | static inline void tcg_gen_exit_tb(tcg_target_long val) |
1168 | c896fe29 | bellard | { |
1169 | ac56dd48 | pbrook | tcg_gen_op1i(INDEX_op_exit_tb, val); |
1170 | c896fe29 | bellard | } |
1171 | c896fe29 | bellard | |
1172 | c896fe29 | bellard | static inline void tcg_gen_goto_tb(int idx) |
1173 | c896fe29 | bellard | { |
1174 | ac56dd48 | pbrook | tcg_gen_op1i(INDEX_op_goto_tb, idx); |
1175 | c896fe29 | bellard | } |
1176 | c896fe29 | bellard | |
1177 | c896fe29 | bellard | #if TCG_TARGET_REG_BITS == 32 |
1178 | ac56dd48 | pbrook | static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) |
1179 | c896fe29 | bellard | { |
1180 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
1181 | ac56dd48 | pbrook | tcg_gen_op3i(INDEX_op_qemu_ld8u, ret, addr, mem_index); |
1182 | c896fe29 | bellard | #else
|
1183 | ac56dd48 | pbrook | tcg_gen_op4i(INDEX_op_qemu_ld8u, ret, addr, TCGV_HIGH(addr), mem_index); |
1184 | ac56dd48 | pbrook | tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
1185 | c896fe29 | bellard | #endif
|
1186 | c896fe29 | bellard | } |
1187 | c896fe29 | bellard | |
1188 | ac56dd48 | pbrook | static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index) |
1189 | c896fe29 | bellard | { |
1190 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
1191 | ac56dd48 | pbrook | tcg_gen_op3i(INDEX_op_qemu_ld8s, ret, addr, mem_index); |
1192 | c896fe29 | bellard | #else
|
1193 | ac56dd48 | pbrook | tcg_gen_op4i(INDEX_op_qemu_ld8s, ret, addr, TCGV_HIGH(addr), mem_index); |
1194 | 21fc3cfc | pbrook | tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
|
1195 | c896fe29 | bellard | #endif
|
1196 | c896fe29 | bellard | } |
1197 | c896fe29 | bellard | |
1198 | ac56dd48 | pbrook | static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index) |
1199 | c896fe29 | bellard | { |
1200 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
1201 | ac56dd48 | pbrook | tcg_gen_op3i(INDEX_op_qemu_ld16u, ret, addr, mem_index); |
1202 | c896fe29 | bellard | #else
|
1203 | ac56dd48 | pbrook | tcg_gen_op4i(INDEX_op_qemu_ld16u, ret, addr, TCGV_HIGH(addr), mem_index); |
1204 | ac56dd48 | pbrook | tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
1205 | c896fe29 | bellard | #endif
|
1206 | c896fe29 | bellard | } |
1207 | c896fe29 | bellard | |
1208 | ac56dd48 | pbrook | static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index) |
1209 | c896fe29 | bellard | { |
1210 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
1211 | ac56dd48 | pbrook | tcg_gen_op3i(INDEX_op_qemu_ld16s, ret, addr, mem_index); |
1212 | c896fe29 | bellard | #else
|
1213 | ac56dd48 | pbrook | tcg_gen_op4i(INDEX_op_qemu_ld16s, ret, addr, TCGV_HIGH(addr), mem_index); |
1214 | 21fc3cfc | pbrook | tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
|
1215 | c896fe29 | bellard | #endif
|
1216 | c896fe29 | bellard | } |
1217 | c896fe29 | bellard | |
1218 | ac56dd48 | pbrook | static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index) |
1219 | c896fe29 | bellard | { |
1220 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
1221 | ac56dd48 | pbrook | tcg_gen_op3i(INDEX_op_qemu_ld32u, ret, addr, mem_index); |
1222 | c896fe29 | bellard | #else
|
1223 | ac56dd48 | pbrook | tcg_gen_op4i(INDEX_op_qemu_ld32u, ret, addr, TCGV_HIGH(addr), mem_index); |
1224 | ac56dd48 | pbrook | tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
1225 | c896fe29 | bellard | #endif
|
1226 | c896fe29 | bellard | } |
1227 | c896fe29 | bellard | |
1228 | ac56dd48 | pbrook | static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index) |
1229 | c896fe29 | bellard | { |
1230 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
1231 | ac56dd48 | pbrook | tcg_gen_op3i(INDEX_op_qemu_ld32u, ret, addr, mem_index); |
1232 | c896fe29 | bellard | #else
|
1233 | ac56dd48 | pbrook | tcg_gen_op4i(INDEX_op_qemu_ld32u, ret, addr, TCGV_HIGH(addr), mem_index); |
1234 | ac56dd48 | pbrook | tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
|
1235 | c896fe29 | bellard | #endif
|
1236 | c896fe29 | bellard | } |
1237 | c896fe29 | bellard | |
1238 | ac56dd48 | pbrook | static inline void tcg_gen_qemu_ld64(TCGv ret, TCGv addr, int mem_index) |
1239 | c896fe29 | bellard | { |
1240 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
1241 | ac56dd48 | pbrook | tcg_gen_op4i(INDEX_op_qemu_ld64, ret, TCGV_HIGH(ret), addr, mem_index); |
1242 | c896fe29 | bellard | #else
|
1243 | ac56dd48 | pbrook | tcg_gen_op5i(INDEX_op_qemu_ld64, ret, TCGV_HIGH(ret), |
1244 | ac56dd48 | pbrook | addr, TCGV_HIGH(addr), mem_index); |
1245 | c896fe29 | bellard | #endif
|
1246 | c896fe29 | bellard | } |
1247 | c896fe29 | bellard | |
1248 | ac56dd48 | pbrook | static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index) |
1249 | c896fe29 | bellard | { |
1250 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
1251 | ac56dd48 | pbrook | tcg_gen_op3i(INDEX_op_qemu_st8, arg, addr, mem_index); |
1252 | c896fe29 | bellard | #else
|
1253 | ac56dd48 | pbrook | tcg_gen_op4i(INDEX_op_qemu_st8, arg, addr, TCGV_HIGH(addr), mem_index); |
1254 | c896fe29 | bellard | #endif
|
1255 | c896fe29 | bellard | } |
1256 | c896fe29 | bellard | |
1257 | ac56dd48 | pbrook | static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index) |
1258 | c896fe29 | bellard | { |
1259 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
1260 | ac56dd48 | pbrook | tcg_gen_op3i(INDEX_op_qemu_st16, arg, addr, mem_index); |
1261 | c896fe29 | bellard | #else
|
1262 | ac56dd48 | pbrook | tcg_gen_op4i(INDEX_op_qemu_st16, arg, addr, TCGV_HIGH(addr), mem_index); |
1263 | c896fe29 | bellard | #endif
|
1264 | c896fe29 | bellard | } |
1265 | c896fe29 | bellard | |
1266 | ac56dd48 | pbrook | static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index) |
1267 | c896fe29 | bellard | { |
1268 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
1269 | ac56dd48 | pbrook | tcg_gen_op3i(INDEX_op_qemu_st32, arg, addr, mem_index); |
1270 | c896fe29 | bellard | #else
|
1271 | ac56dd48 | pbrook | tcg_gen_op4i(INDEX_op_qemu_st32, arg, addr, TCGV_HIGH(addr), mem_index); |
1272 | c896fe29 | bellard | #endif
|
1273 | c896fe29 | bellard | } |
1274 | c896fe29 | bellard | |
1275 | ac56dd48 | pbrook | static inline void tcg_gen_qemu_st64(TCGv arg, TCGv addr, int mem_index) |
1276 | c896fe29 | bellard | { |
1277 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
1278 | ac56dd48 | pbrook | tcg_gen_op4i(INDEX_op_qemu_st64, arg, TCGV_HIGH(arg), addr, mem_index); |
1279 | c896fe29 | bellard | #else
|
1280 | ac56dd48 | pbrook | tcg_gen_op5i(INDEX_op_qemu_st64, arg, TCGV_HIGH(arg), |
1281 | ac56dd48 | pbrook | addr, TCGV_HIGH(addr), mem_index); |
1282 | c896fe29 | bellard | #endif
|
1283 | c896fe29 | bellard | } |
1284 | c896fe29 | bellard | |
1285 | 56b8f567 | blueswir1 | #define tcg_gen_ld_ptr tcg_gen_ld_i32
|
1286 | a768e4b2 | blueswir1 | #define tcg_gen_discard_ptr tcg_gen_discard_i32
|
1287 | f8422f52 | blueswir1 | |
1288 | c896fe29 | bellard | #else /* TCG_TARGET_REG_BITS == 32 */ |
1289 | c896fe29 | bellard | |
1290 | ac56dd48 | pbrook | static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) |
1291 | c896fe29 | bellard | { |
1292 | ac56dd48 | pbrook | tcg_gen_op3i(INDEX_op_qemu_ld8u, ret, addr, mem_index); |
1293 | c896fe29 | bellard | } |
1294 | c896fe29 | bellard | |
1295 | ac56dd48 | pbrook | static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index) |
1296 | c896fe29 | bellard | { |
1297 | ac56dd48 | pbrook | tcg_gen_op3i(INDEX_op_qemu_ld8s, ret, addr, mem_index); |
1298 | c896fe29 | bellard | } |
1299 | c896fe29 | bellard | |
1300 | ac56dd48 | pbrook | static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index) |
1301 | c896fe29 | bellard | { |
1302 | ac56dd48 | pbrook | tcg_gen_op3i(INDEX_op_qemu_ld16u, ret, addr, mem_index); |
1303 | c896fe29 | bellard | } |
1304 | c896fe29 | bellard | |
1305 | ac56dd48 | pbrook | static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index) |
1306 | c896fe29 | bellard | { |
1307 | ac56dd48 | pbrook | tcg_gen_op3i(INDEX_op_qemu_ld16s, ret, addr, mem_index); |
1308 | c896fe29 | bellard | } |
1309 | c896fe29 | bellard | |
1310 | ac56dd48 | pbrook | static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index) |
1311 | c896fe29 | bellard | { |
1312 | ac56dd48 | pbrook | tcg_gen_op3i(INDEX_op_qemu_ld32u, ret, addr, mem_index); |
1313 | c896fe29 | bellard | } |
1314 | c896fe29 | bellard | |
1315 | ac56dd48 | pbrook | static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index) |
1316 | c896fe29 | bellard | { |
1317 | ac56dd48 | pbrook | tcg_gen_op3i(INDEX_op_qemu_ld32s, ret, addr, mem_index); |
1318 | c896fe29 | bellard | } |
1319 | c896fe29 | bellard | |
1320 | ac56dd48 | pbrook | static inline void tcg_gen_qemu_ld64(TCGv ret, TCGv addr, int mem_index) |
1321 | c896fe29 | bellard | { |
1322 | ac56dd48 | pbrook | tcg_gen_op3i(INDEX_op_qemu_ld64, ret, addr, mem_index); |
1323 | c896fe29 | bellard | } |
1324 | c896fe29 | bellard | |
1325 | ac56dd48 | pbrook | static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index) |
1326 | c896fe29 | bellard | { |
1327 | ac56dd48 | pbrook | tcg_gen_op3i(INDEX_op_qemu_st8, arg, addr, mem_index); |
1328 | c896fe29 | bellard | } |
1329 | c896fe29 | bellard | |
1330 | ac56dd48 | pbrook | static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index) |
1331 | c896fe29 | bellard | { |
1332 | ac56dd48 | pbrook | tcg_gen_op3i(INDEX_op_qemu_st16, arg, addr, mem_index); |
1333 | c896fe29 | bellard | } |
1334 | c896fe29 | bellard | |
1335 | ac56dd48 | pbrook | static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index) |
1336 | c896fe29 | bellard | { |
1337 | ac56dd48 | pbrook | tcg_gen_op3i(INDEX_op_qemu_st32, arg, addr, mem_index); |
1338 | c896fe29 | bellard | } |
1339 | c896fe29 | bellard | |
1340 | ac56dd48 | pbrook | static inline void tcg_gen_qemu_st64(TCGv arg, TCGv addr, int mem_index) |
1341 | c896fe29 | bellard | { |
1342 | ac56dd48 | pbrook | tcg_gen_op3i(INDEX_op_qemu_st64, arg, addr, mem_index); |
1343 | c896fe29 | bellard | } |
1344 | c896fe29 | bellard | |
1345 | 56b8f567 | blueswir1 | #define tcg_gen_ld_ptr tcg_gen_ld_i64
|
1346 | a768e4b2 | blueswir1 | #define tcg_gen_discard_ptr tcg_gen_discard_i64
|
1347 | f8422f52 | blueswir1 | |
1348 | c896fe29 | bellard | #endif /* TCG_TARGET_REG_BITS != 32 */ |
1349 | f8422f52 | blueswir1 | |
1350 | f8422f52 | blueswir1 | #if TARGET_LONG_BITS == 64 |
1351 | f8422f52 | blueswir1 | #define TCG_TYPE_TL TCG_TYPE_I64
|
1352 | f8422f52 | blueswir1 | #define tcg_gen_movi_tl tcg_gen_movi_i64
|
1353 | f8422f52 | blueswir1 | #define tcg_gen_mov_tl tcg_gen_mov_i64
|
1354 | f8422f52 | blueswir1 | #define tcg_gen_ld8u_tl tcg_gen_ld8u_i64
|
1355 | f8422f52 | blueswir1 | #define tcg_gen_ld8s_tl tcg_gen_ld8s_i64
|
1356 | f8422f52 | blueswir1 | #define tcg_gen_ld16u_tl tcg_gen_ld16u_i64
|
1357 | f8422f52 | blueswir1 | #define tcg_gen_ld16s_tl tcg_gen_ld16s_i64
|
1358 | f8422f52 | blueswir1 | #define tcg_gen_ld32u_tl tcg_gen_ld32u_i64
|
1359 | f8422f52 | blueswir1 | #define tcg_gen_ld32s_tl tcg_gen_ld32s_i64
|
1360 | f8422f52 | blueswir1 | #define tcg_gen_ld_tl tcg_gen_ld_i64
|
1361 | f8422f52 | blueswir1 | #define tcg_gen_st8_tl tcg_gen_st8_i64
|
1362 | f8422f52 | blueswir1 | #define tcg_gen_st16_tl tcg_gen_st16_i64
|
1363 | f8422f52 | blueswir1 | #define tcg_gen_st32_tl tcg_gen_st32_i64
|
1364 | f8422f52 | blueswir1 | #define tcg_gen_st_tl tcg_gen_st_i64
|
1365 | f8422f52 | blueswir1 | #define tcg_gen_add_tl tcg_gen_add_i64
|
1366 | f8422f52 | blueswir1 | #define tcg_gen_addi_tl tcg_gen_addi_i64
|
1367 | f8422f52 | blueswir1 | #define tcg_gen_sub_tl tcg_gen_sub_i64
|
1368 | f8422f52 | blueswir1 | #define tcg_gen_subi_tl tcg_gen_subi_i64
|
1369 | f8422f52 | blueswir1 | #define tcg_gen_and_tl tcg_gen_and_i64
|
1370 | f8422f52 | blueswir1 | #define tcg_gen_andi_tl tcg_gen_andi_i64
|
1371 | f8422f52 | blueswir1 | #define tcg_gen_or_tl tcg_gen_or_i64
|
1372 | f8422f52 | blueswir1 | #define tcg_gen_ori_tl tcg_gen_ori_i64
|
1373 | f8422f52 | blueswir1 | #define tcg_gen_xor_tl tcg_gen_xor_i64
|
1374 | f8422f52 | blueswir1 | #define tcg_gen_xori_tl tcg_gen_xori_i64
|
1375 | f8422f52 | blueswir1 | #define tcg_gen_shl_tl tcg_gen_shl_i64
|
1376 | f8422f52 | blueswir1 | #define tcg_gen_shli_tl tcg_gen_shli_i64
|
1377 | f8422f52 | blueswir1 | #define tcg_gen_shr_tl tcg_gen_shr_i64
|
1378 | f8422f52 | blueswir1 | #define tcg_gen_shri_tl tcg_gen_shri_i64
|
1379 | f8422f52 | blueswir1 | #define tcg_gen_sar_tl tcg_gen_sar_i64
|
1380 | f8422f52 | blueswir1 | #define tcg_gen_sari_tl tcg_gen_sari_i64
|
1381 | 0cf767d6 | blueswir1 | #define tcg_gen_brcond_tl tcg_gen_brcond_i64
|
1382 | a768e4b2 | blueswir1 | #define tcg_gen_discard_tl tcg_gen_discard_i64
|
1383 | e429073d | blueswir1 | #define tcg_gen_trunc_tl_i32 tcg_gen_trunc_i64_i32
|
1384 | e429073d | blueswir1 | #define tcg_gen_trunc_i64_tl tcg_gen_mov_i64
|
1385 | e429073d | blueswir1 | #define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64
|
1386 | e429073d | blueswir1 | #define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64
|
1387 | e429073d | blueswir1 | #define tcg_gen_extu_tl_i64 tcg_gen_mov_i64
|
1388 | e429073d | blueswir1 | #define tcg_gen_ext_tl_i64 tcg_gen_mov_i64
|
1389 | a98824ac | blueswir1 | #define tcg_const_tl tcg_const_i64
|
1390 | f8422f52 | blueswir1 | #else
|
1391 | f8422f52 | blueswir1 | #define TCG_TYPE_TL TCG_TYPE_I32
|
1392 | f8422f52 | blueswir1 | #define tcg_gen_movi_tl tcg_gen_movi_i32
|
1393 | f8422f52 | blueswir1 | #define tcg_gen_mov_tl tcg_gen_mov_i32
|
1394 | f8422f52 | blueswir1 | #define tcg_gen_ld8u_tl tcg_gen_ld8u_i32
|
1395 | f8422f52 | blueswir1 | #define tcg_gen_ld8s_tl tcg_gen_ld8s_i32
|
1396 | f8422f52 | blueswir1 | #define tcg_gen_ld16u_tl tcg_gen_ld16u_i32
|
1397 | f8422f52 | blueswir1 | #define tcg_gen_ld16s_tl tcg_gen_ld16s_i32
|
1398 | f8422f52 | blueswir1 | #define tcg_gen_ld32u_tl tcg_gen_ld_i32
|
1399 | f8422f52 | blueswir1 | #define tcg_gen_ld32s_tl tcg_gen_ld_i32
|
1400 | f8422f52 | blueswir1 | #define tcg_gen_ld_tl tcg_gen_ld_i32
|
1401 | f8422f52 | blueswir1 | #define tcg_gen_st8_tl tcg_gen_st8_i32
|
1402 | f8422f52 | blueswir1 | #define tcg_gen_st16_tl tcg_gen_st16_i32
|
1403 | f8422f52 | blueswir1 | #define tcg_gen_st32_tl tcg_gen_st_i32
|
1404 | f8422f52 | blueswir1 | #define tcg_gen_st_tl tcg_gen_st_i32
|
1405 | f8422f52 | blueswir1 | #define tcg_gen_add_tl tcg_gen_add_i32
|
1406 | f8422f52 | blueswir1 | #define tcg_gen_addi_tl tcg_gen_addi_i32
|
1407 | f8422f52 | blueswir1 | #define tcg_gen_sub_tl tcg_gen_sub_i32
|
1408 | f8422f52 | blueswir1 | #define tcg_gen_subi_tl tcg_gen_subi_i32
|
1409 | f8422f52 | blueswir1 | #define tcg_gen_and_tl tcg_gen_and_i32
|
1410 | f8422f52 | blueswir1 | #define tcg_gen_andi_tl tcg_gen_andi_i32
|
1411 | f8422f52 | blueswir1 | #define tcg_gen_or_tl tcg_gen_or_i32
|
1412 | f8422f52 | blueswir1 | #define tcg_gen_ori_tl tcg_gen_ori_i32
|
1413 | f8422f52 | blueswir1 | #define tcg_gen_xor_tl tcg_gen_xor_i32
|
1414 | f8422f52 | blueswir1 | #define tcg_gen_xori_tl tcg_gen_xori_i32
|
1415 | f8422f52 | blueswir1 | #define tcg_gen_shl_tl tcg_gen_shl_i32
|
1416 | f8422f52 | blueswir1 | #define tcg_gen_shli_tl tcg_gen_shli_i32
|
1417 | f8422f52 | blueswir1 | #define tcg_gen_shr_tl tcg_gen_shr_i32
|
1418 | f8422f52 | blueswir1 | #define tcg_gen_shri_tl tcg_gen_shri_i32
|
1419 | f8422f52 | blueswir1 | #define tcg_gen_sar_tl tcg_gen_sar_i32
|
1420 | f8422f52 | blueswir1 | #define tcg_gen_sari_tl tcg_gen_sari_i32
|
1421 | 0cf767d6 | blueswir1 | #define tcg_gen_brcond_tl tcg_gen_brcond_i32
|
1422 | a768e4b2 | blueswir1 | #define tcg_gen_discard_tl tcg_gen_discard_i32
|
1423 | e429073d | blueswir1 | #define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32
|
1424 | e429073d | blueswir1 | #define tcg_gen_trunc_i64_tl tcg_gen_trunc_i64_i32
|
1425 | e429073d | blueswir1 | #define tcg_gen_extu_i32_tl tcg_gen_mov_i32
|
1426 | e429073d | blueswir1 | #define tcg_gen_ext_i32_tl tcg_gen_mov_i32
|
1427 | e429073d | blueswir1 | #define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64
|
1428 | e429073d | blueswir1 | #define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64
|
1429 | a98824ac | blueswir1 | #define tcg_const_tl tcg_const_i32
|
1430 | f8422f52 | blueswir1 | #endif
|
1431 | 6ddbc6e4 | pbrook | |
1432 | 6ddbc6e4 | pbrook | #if TCG_TARGET_REG_BITS == 32 |
1433 | 6ddbc6e4 | pbrook | #define tcg_gen_addi_ptr tcg_gen_addi_i32
|
1434 | 6ddbc6e4 | pbrook | #else /* TCG_TARGET_REG_BITS == 32 */ |
1435 | 6ddbc6e4 | pbrook | #define tcg_gen_addi_ptr tcg_gen_addi_i64
|
1436 | 6ddbc6e4 | pbrook | #endif /* TCG_TARGET_REG_BITS != 32 */ |