root / target-arm / op.c @ 6ddbc6e4
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/*
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* ARM micro operations
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*
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* Copyright (c) 2003 Fabrice Bellard
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* Copyright (c) 2005-2007 CodeSourcery, LLC
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include "exec.h" |
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|
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void OPPROTO op_addl_T0_T1_cc(void) |
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{
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unsigned int src1; |
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src1 = T0; |
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T0 += T1; |
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env->NZF = T0; |
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env->CF = T0 < src1; |
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env->VF = (src1 ^ T1 ^ -1) & (src1 ^ T0);
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} |
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|
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void OPPROTO op_adcl_T0_T1_cc(void) |
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{
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unsigned int src1; |
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src1 = T0; |
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if (!env->CF) {
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T0 += T1; |
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env->CF = T0 < src1; |
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} else {
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T0 += T1 + 1;
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env->CF = T0 <= src1; |
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} |
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env->VF = (src1 ^ T1 ^ -1) & (src1 ^ T0);
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env->NZF = T0; |
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FORCE_RET(); |
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} |
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|
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#define OPSUB(sub, sbc, res, T0, T1) \
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\ |
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void OPPROTO op_ ## sub ## l_T0_T1_cc(void) \ |
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{ \
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unsigned int src1; \ |
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src1 = T0; \ |
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T0 -= T1; \ |
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env->NZF = T0; \ |
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env->CF = src1 >= T1; \ |
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env->VF = (src1 ^ T1) & (src1 ^ T0); \ |
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res = T0; \ |
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} \ |
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\ |
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void OPPROTO op_ ## sbc ## l_T0_T1_cc(void) \ |
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{ \
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unsigned int src1; \ |
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src1 = T0; \ |
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if (!env->CF) { \
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T0 = T0 - T1 - 1; \
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env->CF = src1 > T1; \ |
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} else { \
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T0 = T0 - T1; \ |
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env->CF = src1 >= T1; \ |
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} \ |
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env->VF = (src1 ^ T1) & (src1 ^ T0); \ |
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env->NZF = T0; \ |
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res = T0; \ |
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FORCE_RET(); \ |
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} |
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|
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OPSUB(sub, sbc, T0, T0, T1) |
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|
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OPSUB(rsb, rsc, T0, T1, T0) |
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|
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#define EIP (env->regs[15]) |
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|
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void OPPROTO op_test_eq(void) |
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{
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if (env->NZF == 0) |
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GOTO_LABEL_PARAM(1);;
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FORCE_RET(); |
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} |
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|
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void OPPROTO op_test_ne(void) |
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{
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if (env->NZF != 0) |
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GOTO_LABEL_PARAM(1);;
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FORCE_RET(); |
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} |
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|
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void OPPROTO op_test_cs(void) |
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{
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if (env->CF != 0) |
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GOTO_LABEL_PARAM(1);
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FORCE_RET(); |
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} |
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|
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void OPPROTO op_test_cc(void) |
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{
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if (env->CF == 0) |
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GOTO_LABEL_PARAM(1);
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FORCE_RET(); |
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} |
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|
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void OPPROTO op_test_mi(void) |
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{
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if ((env->NZF & 0x80000000) != 0) |
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GOTO_LABEL_PARAM(1);
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FORCE_RET(); |
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} |
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|
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void OPPROTO op_test_pl(void) |
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{
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if ((env->NZF & 0x80000000) == 0) |
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GOTO_LABEL_PARAM(1);
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FORCE_RET(); |
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} |
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|
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void OPPROTO op_test_vs(void) |
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{
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if ((env->VF & 0x80000000) != 0) |
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GOTO_LABEL_PARAM(1);
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FORCE_RET(); |
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} |
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|
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void OPPROTO op_test_vc(void) |
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{
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if ((env->VF & 0x80000000) == 0) |
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GOTO_LABEL_PARAM(1);
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FORCE_RET(); |
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} |
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|
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void OPPROTO op_test_hi(void) |
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{
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if (env->CF != 0 && env->NZF != 0) |
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GOTO_LABEL_PARAM(1);
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FORCE_RET(); |
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} |
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void OPPROTO op_test_ls(void) |
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{
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if (env->CF == 0 || env->NZF == 0) |
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GOTO_LABEL_PARAM(1);
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FORCE_RET(); |
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} |
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void OPPROTO op_test_ge(void) |
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{
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if (((env->VF ^ env->NZF) & 0x80000000) == 0) |
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GOTO_LABEL_PARAM(1);
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FORCE_RET(); |
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} |
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void OPPROTO op_test_lt(void) |
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{
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if (((env->VF ^ env->NZF) & 0x80000000) != 0) |
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GOTO_LABEL_PARAM(1);
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FORCE_RET(); |
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} |
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|
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void OPPROTO op_test_gt(void) |
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{
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if (env->NZF != 0 && ((env->VF ^ env->NZF) & 0x80000000) == 0) |
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GOTO_LABEL_PARAM(1);
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FORCE_RET(); |
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} |
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void OPPROTO op_test_le(void) |
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{
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if (env->NZF == 0 || ((env->VF ^ env->NZF) & 0x80000000) != 0) |
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GOTO_LABEL_PARAM(1);
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FORCE_RET(); |
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} |
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|
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void OPPROTO op_test_T0(void) |
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{
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if (T0)
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GOTO_LABEL_PARAM(1);
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FORCE_RET(); |
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} |
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void OPPROTO op_testn_T0(void) |
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{
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if (!T0)
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GOTO_LABEL_PARAM(1);
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FORCE_RET(); |
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} |
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|
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void OPPROTO op_movl_T0_cpsr(void) |
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{
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/* Execution state bits always read as zero. */
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T0 = cpsr_read(env) & ~CPSR_EXEC; |
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FORCE_RET(); |
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} |
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|
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void OPPROTO op_movl_T0_spsr(void) |
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{
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T0 = env->spsr; |
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} |
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void OPPROTO op_movl_spsr_T0(void) |
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{
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uint32_t mask = PARAM1; |
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env->spsr = (env->spsr & ~mask) | (T0 & mask); |
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} |
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void OPPROTO op_movl_cpsr_T0(void) |
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{
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cpsr_write(env, T0, PARAM1); |
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FORCE_RET(); |
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} |
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/* 48 bit signed mul, top 32 bits */
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void OPPROTO op_imulw_T0_T1(void) |
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{
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uint64_t res; |
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res = (int64_t)((int32_t)T0) * (int64_t)((int32_t)T1); |
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T0 = res >> 16;
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} |
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void OPPROTO op_addq_T0_T1(void) |
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{
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uint64_t res; |
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res = ((uint64_t)T1 << 32) | T0;
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res += ((uint64_t)(env->regs[PARAM2]) << 32) | (env->regs[PARAM1]);
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T1 = res >> 32;
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T0 = res; |
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} |
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void OPPROTO op_addq_lo_T0_T1(void) |
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{
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uint64_t res; |
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res = ((uint64_t)T1 << 32) | T0;
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res += (uint64_t)(env->regs[PARAM1]); |
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T1 = res >> 32;
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T0 = res; |
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} |
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/* Dual 16-bit accumulate. */
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void OPPROTO op_addq_T0_T1_dual(void) |
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{
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uint64_t res; |
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res = ((uint64_t)(env->regs[PARAM2]) << 32) | (env->regs[PARAM1]);
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res += (int32_t)T0; |
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res += (int32_t)T1; |
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env->regs[PARAM1] = (uint32_t)res; |
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env->regs[PARAM2] = res >> 32;
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} |
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/* Dual 16-bit subtract accumulate. */
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void OPPROTO op_subq_T0_T1_dual(void) |
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{
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uint64_t res; |
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res = ((uint64_t)(env->regs[PARAM2]) << 32) | (env->regs[PARAM1]);
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res += (int32_t)T0; |
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res -= (int32_t)T1; |
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env->regs[PARAM1] = (uint32_t)res; |
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env->regs[PARAM2] = res >> 32;
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} |
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|
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void OPPROTO op_logicq_cc(void) |
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{
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env->NZF = (T1 & 0x80000000) | ((T0 | T1) != 0); |
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} |
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/* memory access */
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#define MEMSUFFIX _raw
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#include "op_mem.h" |
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#if !defined(CONFIG_USER_ONLY)
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#define MEMSUFFIX _user
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#include "op_mem.h" |
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#define MEMSUFFIX _kernel
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#include "op_mem.h" |
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#endif
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|
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void OPPROTO op_clrex(void) |
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{
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cpu_lock(); |
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helper_clrex(env); |
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cpu_unlock(); |
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} |
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|
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/* T1 based, use T0 as shift count */
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void OPPROTO op_shll_T1_T0(void) |
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{
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int shift;
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shift = T0 & 0xff;
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if (shift >= 32) |
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T1 = 0;
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else
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T1 = T1 << shift; |
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FORCE_RET(); |
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} |
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|
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void OPPROTO op_shrl_T1_T0(void) |
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{
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int shift;
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shift = T0 & 0xff;
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if (shift >= 32) |
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T1 = 0;
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else
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T1 = (uint32_t)T1 >> shift; |
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FORCE_RET(); |
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} |
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|
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void OPPROTO op_sarl_T1_T0(void) |
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{
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int shift;
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shift = T0 & 0xff;
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if (shift >= 32) |
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shift = 31;
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T1 = (int32_t)T1 >> shift; |
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} |
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|
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void OPPROTO op_rorl_T1_T0(void) |
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{
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int shift;
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shift = T0 & 0x1f;
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if (shift) {
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T1 = ((uint32_t)T1 >> shift) | (T1 << (32 - shift));
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} |
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FORCE_RET(); |
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} |
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|
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/* T1 based, use T0 as shift count and compute CF */
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|
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void OPPROTO op_shll_T1_T0_cc(void) |
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{
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int shift;
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shift = T0 & 0xff;
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if (shift >= 32) { |
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if (shift == 32) |
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env->CF = T1 & 1;
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else
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env->CF = 0;
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T1 = 0;
|
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} else if (shift != 0) { |
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env->CF = (T1 >> (32 - shift)) & 1; |
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T1 = T1 << shift; |
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} |
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FORCE_RET(); |
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} |
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|
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void OPPROTO op_shrl_T1_T0_cc(void) |
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{
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int shift;
|
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shift = T0 & 0xff;
|
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if (shift >= 32) { |
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if (shift == 32) |
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env->CF = (T1 >> 31) & 1; |
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else
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env->CF = 0;
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T1 = 0;
|
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} else if (shift != 0) { |
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env->CF = (T1 >> (shift - 1)) & 1; |
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T1 = (uint32_t)T1 >> shift; |
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} |
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FORCE_RET(); |
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} |
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|
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void OPPROTO op_sarl_T1_T0_cc(void) |
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{
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int shift;
|
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shift = T0 & 0xff;
|
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if (shift >= 32) { |
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env->CF = (T1 >> 31) & 1; |
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T1 = (int32_t)T1 >> 31;
|
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} else if (shift != 0) { |
| 379 |
env->CF = (T1 >> (shift - 1)) & 1; |
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T1 = (int32_t)T1 >> shift; |
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} |
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FORCE_RET(); |
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} |
| 384 |
|
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void OPPROTO op_rorl_T1_T0_cc(void) |
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{
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int shift1, shift;
|
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shift1 = T0 & 0xff;
|
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shift = shift1 & 0x1f;
|
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if (shift == 0) { |
| 391 |
if (shift1 != 0) |
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env->CF = (T1 >> 31) & 1; |
| 393 |
} else {
|
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env->CF = (T1 >> (shift - 1)) & 1; |
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T1 = ((uint32_t)T1 >> shift) | (T1 << (32 - shift));
|
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} |
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FORCE_RET(); |
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} |
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|
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/* exceptions */
|
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|
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void OPPROTO op_swi(void) |
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{
|
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env->exception_index = EXCP_SWI; |
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cpu_loop_exit(); |
| 406 |
} |
| 407 |
|
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void OPPROTO op_undef_insn(void) |
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{
|
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env->exception_index = EXCP_UDEF; |
| 411 |
cpu_loop_exit(); |
| 412 |
} |
| 413 |
|
| 414 |
void OPPROTO op_debug(void) |
| 415 |
{
|
| 416 |
env->exception_index = EXCP_DEBUG; |
| 417 |
cpu_loop_exit(); |
| 418 |
} |
| 419 |
|
| 420 |
void OPPROTO op_wfi(void) |
| 421 |
{
|
| 422 |
env->exception_index = EXCP_HLT; |
| 423 |
env->halted = 1;
|
| 424 |
cpu_loop_exit(); |
| 425 |
} |
| 426 |
|
| 427 |
void OPPROTO op_bkpt(void) |
| 428 |
{
|
| 429 |
env->exception_index = EXCP_BKPT; |
| 430 |
cpu_loop_exit(); |
| 431 |
} |
| 432 |
|
| 433 |
void OPPROTO op_exception_exit(void) |
| 434 |
{
|
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env->exception_index = EXCP_EXCEPTION_EXIT; |
| 436 |
cpu_loop_exit(); |
| 437 |
} |
| 438 |
|
| 439 |
/* VFP support. We follow the convention used for VFP instrunctions:
|
| 440 |
Single precition routines have a "s" suffix, double precision a
|
| 441 |
"d" suffix. */
|
| 442 |
|
| 443 |
#define VFP_OP(name, p) void OPPROTO op_vfp_##name##p(void) |
| 444 |
|
| 445 |
#define VFP_BINOP(name) \
|
| 446 |
VFP_OP(name, s) \ |
| 447 |
{ \
|
| 448 |
FT0s = float32_ ## name (FT0s, FT1s, &env->vfp.fp_status); \ |
| 449 |
} \ |
| 450 |
VFP_OP(name, d) \ |
| 451 |
{ \
|
| 452 |
FT0d = float64_ ## name (FT0d, FT1d, &env->vfp.fp_status); \ |
| 453 |
} |
| 454 |
VFP_BINOP(add) |
| 455 |
VFP_BINOP(sub) |
| 456 |
VFP_BINOP(mul) |
| 457 |
VFP_BINOP(div) |
| 458 |
#undef VFP_BINOP
|
| 459 |
|
| 460 |
#define VFP_HELPER(name) \
|
| 461 |
VFP_OP(name, s) \ |
| 462 |
{ \
|
| 463 |
do_vfp_##name##s(); \ |
| 464 |
} \ |
| 465 |
VFP_OP(name, d) \ |
| 466 |
{ \
|
| 467 |
do_vfp_##name##d(); \ |
| 468 |
} |
| 469 |
VFP_HELPER(abs) |
| 470 |
VFP_HELPER(sqrt) |
| 471 |
VFP_HELPER(cmp) |
| 472 |
VFP_HELPER(cmpe) |
| 473 |
#undef VFP_HELPER
|
| 474 |
|
| 475 |
/* XXX: Will this do the right thing for NANs. Should invert the signbit
|
| 476 |
without looking at the rest of the value. */
|
| 477 |
VFP_OP(neg, s) |
| 478 |
{
|
| 479 |
FT0s = float32_chs(FT0s); |
| 480 |
} |
| 481 |
|
| 482 |
VFP_OP(neg, d) |
| 483 |
{
|
| 484 |
FT0d = float64_chs(FT0d); |
| 485 |
} |
| 486 |
|
| 487 |
VFP_OP(F1_ld0, s) |
| 488 |
{
|
| 489 |
union {
|
| 490 |
uint32_t i; |
| 491 |
float32 s; |
| 492 |
} v; |
| 493 |
v.i = 0;
|
| 494 |
FT1s = v.s; |
| 495 |
} |
| 496 |
|
| 497 |
VFP_OP(F1_ld0, d) |
| 498 |
{
|
| 499 |
union {
|
| 500 |
uint64_t i; |
| 501 |
float64 d; |
| 502 |
} v; |
| 503 |
v.i = 0;
|
| 504 |
FT1d = v.d; |
| 505 |
} |
| 506 |
|
| 507 |
/* Helper routines to perform bitwise copies between float and int. */
|
| 508 |
static inline float32 vfp_itos(uint32_t i) |
| 509 |
{
|
| 510 |
union {
|
| 511 |
uint32_t i; |
| 512 |
float32 s; |
| 513 |
} v; |
| 514 |
|
| 515 |
v.i = i; |
| 516 |
return v.s;
|
| 517 |
} |
| 518 |
|
| 519 |
static inline uint32_t vfp_stoi(float32 s) |
| 520 |
{
|
| 521 |
union {
|
| 522 |
uint32_t i; |
| 523 |
float32 s; |
| 524 |
} v; |
| 525 |
|
| 526 |
v.s = s; |
| 527 |
return v.i;
|
| 528 |
} |
| 529 |
|
| 530 |
static inline float64 vfp_itod(uint64_t i) |
| 531 |
{
|
| 532 |
union {
|
| 533 |
uint64_t i; |
| 534 |
float64 d; |
| 535 |
} v; |
| 536 |
|
| 537 |
v.i = i; |
| 538 |
return v.d;
|
| 539 |
} |
| 540 |
|
| 541 |
static inline uint64_t vfp_dtoi(float64 d) |
| 542 |
{
|
| 543 |
union {
|
| 544 |
uint64_t i; |
| 545 |
float64 d; |
| 546 |
} v; |
| 547 |
|
| 548 |
v.d = d; |
| 549 |
return v.i;
|
| 550 |
} |
| 551 |
|
| 552 |
/* Integer to float conversion. */
|
| 553 |
VFP_OP(uito, s) |
| 554 |
{
|
| 555 |
FT0s = uint32_to_float32(vfp_stoi(FT0s), &env->vfp.fp_status); |
| 556 |
} |
| 557 |
|
| 558 |
VFP_OP(uito, d) |
| 559 |
{
|
| 560 |
FT0d = uint32_to_float64(vfp_stoi(FT0s), &env->vfp.fp_status); |
| 561 |
} |
| 562 |
|
| 563 |
VFP_OP(sito, s) |
| 564 |
{
|
| 565 |
FT0s = int32_to_float32(vfp_stoi(FT0s), &env->vfp.fp_status); |
| 566 |
} |
| 567 |
|
| 568 |
VFP_OP(sito, d) |
| 569 |
{
|
| 570 |
FT0d = int32_to_float64(vfp_stoi(FT0s), &env->vfp.fp_status); |
| 571 |
} |
| 572 |
|
| 573 |
/* Float to integer conversion. */
|
| 574 |
VFP_OP(toui, s) |
| 575 |
{
|
| 576 |
FT0s = vfp_itos(float32_to_uint32(FT0s, &env->vfp.fp_status)); |
| 577 |
} |
| 578 |
|
| 579 |
VFP_OP(toui, d) |
| 580 |
{
|
| 581 |
FT0s = vfp_itos(float64_to_uint32(FT0d, &env->vfp.fp_status)); |
| 582 |
} |
| 583 |
|
| 584 |
VFP_OP(tosi, s) |
| 585 |
{
|
| 586 |
FT0s = vfp_itos(float32_to_int32(FT0s, &env->vfp.fp_status)); |
| 587 |
} |
| 588 |
|
| 589 |
VFP_OP(tosi, d) |
| 590 |
{
|
| 591 |
FT0s = vfp_itos(float64_to_int32(FT0d, &env->vfp.fp_status)); |
| 592 |
} |
| 593 |
|
| 594 |
/* TODO: Set rounding mode properly. */
|
| 595 |
VFP_OP(touiz, s) |
| 596 |
{
|
| 597 |
FT0s = vfp_itos(float32_to_uint32_round_to_zero(FT0s, &env->vfp.fp_status)); |
| 598 |
} |
| 599 |
|
| 600 |
VFP_OP(touiz, d) |
| 601 |
{
|
| 602 |
FT0s = vfp_itos(float64_to_uint32_round_to_zero(FT0d, &env->vfp.fp_status)); |
| 603 |
} |
| 604 |
|
| 605 |
VFP_OP(tosiz, s) |
| 606 |
{
|
| 607 |
FT0s = vfp_itos(float32_to_int32_round_to_zero(FT0s, &env->vfp.fp_status)); |
| 608 |
} |
| 609 |
|
| 610 |
VFP_OP(tosiz, d) |
| 611 |
{
|
| 612 |
FT0s = vfp_itos(float64_to_int32_round_to_zero(FT0d, &env->vfp.fp_status)); |
| 613 |
} |
| 614 |
|
| 615 |
/* floating point conversion */
|
| 616 |
VFP_OP(fcvtd, s) |
| 617 |
{
|
| 618 |
FT0d = float32_to_float64(FT0s, &env->vfp.fp_status); |
| 619 |
} |
| 620 |
|
| 621 |
VFP_OP(fcvts, d) |
| 622 |
{
|
| 623 |
FT0s = float64_to_float32(FT0d, &env->vfp.fp_status); |
| 624 |
} |
| 625 |
|
| 626 |
/* VFP3 fixed point conversion. */
|
| 627 |
#define VFP_CONV_FIX(name, p, ftype, itype, sign) \
|
| 628 |
VFP_OP(name##to, p) \ |
| 629 |
{ \
|
| 630 |
ftype tmp; \ |
| 631 |
tmp = sign##int32_to_##ftype ((itype)vfp_##p##toi(FT0##p), \ |
| 632 |
&env->vfp.fp_status); \ |
| 633 |
FT0##p = ftype##_scalbn(tmp, PARAM1, &env->vfp.fp_status); \ |
| 634 |
} \ |
| 635 |
VFP_OP(to##name, p) \ |
| 636 |
{ \
|
| 637 |
ftype tmp; \ |
| 638 |
tmp = ftype##_scalbn(FT0##p, PARAM1, &env->vfp.fp_status); \ |
| 639 |
FT0##p = vfp_ito##p((itype)ftype##_to_##sign##int32_round_to_zero(tmp, \ |
| 640 |
&env->vfp.fp_status)); \ |
| 641 |
} |
| 642 |
|
| 643 |
VFP_CONV_FIX(sh, d, float64, int16, ) |
| 644 |
VFP_CONV_FIX(sl, d, float64, int32, ) |
| 645 |
VFP_CONV_FIX(uh, d, float64, uint16, u) |
| 646 |
VFP_CONV_FIX(ul, d, float64, uint32, u) |
| 647 |
VFP_CONV_FIX(sh, s, float32, int16, ) |
| 648 |
VFP_CONV_FIX(sl, s, float32, int32, ) |
| 649 |
VFP_CONV_FIX(uh, s, float32, uint16, u) |
| 650 |
VFP_CONV_FIX(ul, s, float32, uint32, u) |
| 651 |
|
| 652 |
/* Get and Put values from registers. */
|
| 653 |
VFP_OP(getreg_F0, d) |
| 654 |
{
|
| 655 |
FT0d = *(float64 *)((char *) env + PARAM1);
|
| 656 |
} |
| 657 |
|
| 658 |
VFP_OP(getreg_F0, s) |
| 659 |
{
|
| 660 |
FT0s = *(float32 *)((char *) env + PARAM1);
|
| 661 |
} |
| 662 |
|
| 663 |
VFP_OP(getreg_F1, d) |
| 664 |
{
|
| 665 |
FT1d = *(float64 *)((char *) env + PARAM1);
|
| 666 |
} |
| 667 |
|
| 668 |
VFP_OP(getreg_F1, s) |
| 669 |
{
|
| 670 |
FT1s = *(float32 *)((char *) env + PARAM1);
|
| 671 |
} |
| 672 |
|
| 673 |
VFP_OP(setreg_F0, d) |
| 674 |
{
|
| 675 |
*(float64 *)((char *) env + PARAM1) = FT0d;
|
| 676 |
} |
| 677 |
|
| 678 |
VFP_OP(setreg_F0, s) |
| 679 |
{
|
| 680 |
*(float32 *)((char *) env + PARAM1) = FT0s;
|
| 681 |
} |
| 682 |
|
| 683 |
void OPPROTO op_vfp_movl_T0_fpscr(void) |
| 684 |
{
|
| 685 |
do_vfp_get_fpscr (); |
| 686 |
} |
| 687 |
|
| 688 |
void OPPROTO op_vfp_movl_T0_fpscr_flags(void) |
| 689 |
{
|
| 690 |
T0 = env->vfp.xregs[ARM_VFP_FPSCR] & (0xf << 28); |
| 691 |
} |
| 692 |
|
| 693 |
void OPPROTO op_vfp_movl_fpscr_T0(void) |
| 694 |
{
|
| 695 |
do_vfp_set_fpscr(); |
| 696 |
} |
| 697 |
|
| 698 |
void OPPROTO op_vfp_movl_T0_xreg(void) |
| 699 |
{
|
| 700 |
T0 = env->vfp.xregs[PARAM1]; |
| 701 |
} |
| 702 |
|
| 703 |
void OPPROTO op_vfp_movl_xreg_T0(void) |
| 704 |
{
|
| 705 |
env->vfp.xregs[PARAM1] = T0; |
| 706 |
} |
| 707 |
|
| 708 |
/* Move between FT0s to T0 */
|
| 709 |
void OPPROTO op_vfp_mrs(void) |
| 710 |
{
|
| 711 |
T0 = vfp_stoi(FT0s); |
| 712 |
} |
| 713 |
|
| 714 |
void OPPROTO op_vfp_msr(void) |
| 715 |
{
|
| 716 |
FT0s = vfp_itos(T0); |
| 717 |
} |
| 718 |
|
| 719 |
/* Move between FT0d and {T0,T1} */
|
| 720 |
void OPPROTO op_vfp_mrrd(void) |
| 721 |
{
|
| 722 |
CPU_DoubleU u; |
| 723 |
|
| 724 |
u.d = FT0d; |
| 725 |
T0 = u.l.lower; |
| 726 |
T1 = u.l.upper; |
| 727 |
} |
| 728 |
|
| 729 |
void OPPROTO op_vfp_mdrr(void) |
| 730 |
{
|
| 731 |
CPU_DoubleU u; |
| 732 |
|
| 733 |
u.l.lower = T0; |
| 734 |
u.l.upper = T1; |
| 735 |
FT0d = u.d; |
| 736 |
} |
| 737 |
|
| 738 |
/* Load immediate. PARAM1 is the 32 most significant bits of the value. */
|
| 739 |
void OPPROTO op_vfp_fconstd(void) |
| 740 |
{
|
| 741 |
CPU_DoubleU u; |
| 742 |
u.l.upper = PARAM1; |
| 743 |
u.l.lower = 0;
|
| 744 |
FT0d = u.d; |
| 745 |
} |
| 746 |
|
| 747 |
void OPPROTO op_vfp_fconsts(void) |
| 748 |
{
|
| 749 |
FT0s = vfp_itos(PARAM1); |
| 750 |
} |
| 751 |
|
| 752 |
void OPPROTO op_movl_cp_T0(void) |
| 753 |
{
|
| 754 |
helper_set_cp(env, PARAM1, T0); |
| 755 |
FORCE_RET(); |
| 756 |
} |
| 757 |
|
| 758 |
void OPPROTO op_movl_T0_cp(void) |
| 759 |
{
|
| 760 |
T0 = helper_get_cp(env, PARAM1); |
| 761 |
FORCE_RET(); |
| 762 |
} |
| 763 |
|
| 764 |
void OPPROTO op_movl_cp15_T0(void) |
| 765 |
{
|
| 766 |
helper_set_cp15(env, PARAM1, T0); |
| 767 |
FORCE_RET(); |
| 768 |
} |
| 769 |
|
| 770 |
void OPPROTO op_movl_T0_cp15(void) |
| 771 |
{
|
| 772 |
T0 = helper_get_cp15(env, PARAM1); |
| 773 |
FORCE_RET(); |
| 774 |
} |
| 775 |
|
| 776 |
/* Access to user mode registers from privileged modes. */
|
| 777 |
void OPPROTO op_movl_T0_user(void) |
| 778 |
{
|
| 779 |
int regno = PARAM1;
|
| 780 |
if (regno == 13) { |
| 781 |
T0 = env->banked_r13[0];
|
| 782 |
} else if (regno == 14) { |
| 783 |
T0 = env->banked_r14[0];
|
| 784 |
} else if ((env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) { |
| 785 |
T0 = env->usr_regs[regno - 8];
|
| 786 |
} else {
|
| 787 |
T0 = env->regs[regno]; |
| 788 |
} |
| 789 |
FORCE_RET(); |
| 790 |
} |
| 791 |
|
| 792 |
|
| 793 |
void OPPROTO op_movl_user_T0(void) |
| 794 |
{
|
| 795 |
int regno = PARAM1;
|
| 796 |
if (regno == 13) { |
| 797 |
env->banked_r13[0] = T0;
|
| 798 |
} else if (regno == 14) { |
| 799 |
env->banked_r14[0] = T0;
|
| 800 |
} else if ((env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) { |
| 801 |
env->usr_regs[regno - 8] = T0;
|
| 802 |
} else {
|
| 803 |
env->regs[regno] = T0; |
| 804 |
} |
| 805 |
FORCE_RET(); |
| 806 |
} |
| 807 |
|
| 808 |
void OPPROTO op_movl_T1_r13_banked(void) |
| 809 |
{
|
| 810 |
T1 = helper_get_r13_banked(env, PARAM1); |
| 811 |
} |
| 812 |
|
| 813 |
void OPPROTO op_movl_r13_T1_banked(void) |
| 814 |
{
|
| 815 |
helper_set_r13_banked(env, PARAM1, T1); |
| 816 |
} |
| 817 |
|
| 818 |
void OPPROTO op_v7m_mrs_T0(void) |
| 819 |
{
|
| 820 |
T0 = helper_v7m_mrs(env, PARAM1); |
| 821 |
} |
| 822 |
|
| 823 |
void OPPROTO op_v7m_msr_T0(void) |
| 824 |
{
|
| 825 |
helper_v7m_msr(env, PARAM1, T0); |
| 826 |
} |
| 827 |
|
| 828 |
void OPPROTO op_movl_T0_sp(void) |
| 829 |
{
|
| 830 |
if (PARAM1 == env->v7m.current_sp)
|
| 831 |
T0 = env->regs[13];
|
| 832 |
else
|
| 833 |
T0 = env->v7m.other_sp; |
| 834 |
FORCE_RET(); |
| 835 |
} |
| 836 |
|
| 837 |
#include "op_neon.h" |
| 838 |
|
| 839 |
/* iwMMXt support */
|
| 840 |
#include "op_iwmmxt.c" |