root / tcg / tcg-op.h @ 6ddbc6e4
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/*
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* Tiny Code Generator for QEMU
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*
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* Copyright (c) 2008 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "tcg.h" |
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#ifndef CONFIG_NO_DYNGEN_OP
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/* legacy dyngen operations */
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#include "gen-op.h" |
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#endif
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int gen_new_label(void); |
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static inline void tcg_gen_op1(int opc, TCGv arg1) |
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{
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV(arg1); |
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} |
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static inline void tcg_gen_op1i(int opc, TCGArg arg1) |
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{
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = arg1; |
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} |
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static inline void tcg_gen_op2(int opc, TCGv arg1, TCGv arg2) |
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{
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV(arg1); |
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*gen_opparam_ptr++ = GET_TCGV(arg2); |
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} |
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static inline void tcg_gen_op2i(int opc, TCGv arg1, TCGArg arg2) |
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{
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV(arg1); |
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*gen_opparam_ptr++ = arg2; |
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} |
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static inline void tcg_gen_op3(int opc, TCGv arg1, TCGv arg2, TCGv arg3) |
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{
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV(arg1); |
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*gen_opparam_ptr++ = GET_TCGV(arg2); |
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*gen_opparam_ptr++ = GET_TCGV(arg3); |
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} |
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static inline void tcg_gen_op3i(int opc, TCGv arg1, TCGv arg2, TCGArg arg3) |
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{
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV(arg1); |
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*gen_opparam_ptr++ = GET_TCGV(arg2); |
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*gen_opparam_ptr++ = arg3; |
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} |
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static inline void tcg_gen_op4(int opc, TCGv arg1, TCGv arg2, TCGv arg3, |
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TCGv arg4) |
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{
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV(arg1); |
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*gen_opparam_ptr++ = GET_TCGV(arg2); |
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*gen_opparam_ptr++ = GET_TCGV(arg3); |
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*gen_opparam_ptr++ = GET_TCGV(arg4); |
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} |
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static inline void tcg_gen_op4i(int opc, TCGv arg1, TCGv arg2, TCGv arg3, |
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TCGArg arg4) |
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{
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV(arg1); |
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*gen_opparam_ptr++ = GET_TCGV(arg2); |
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*gen_opparam_ptr++ = GET_TCGV(arg3); |
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*gen_opparam_ptr++ = arg4; |
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} |
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static inline void tcg_gen_op4ii(int opc, TCGv arg1, TCGv arg2, TCGArg arg3, |
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TCGArg arg4) |
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{
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV(arg1); |
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*gen_opparam_ptr++ = GET_TCGV(arg2); |
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*gen_opparam_ptr++ = arg3; |
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*gen_opparam_ptr++ = arg4; |
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} |
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static inline void tcg_gen_op5(int opc, TCGv arg1, TCGv arg2, |
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TCGv arg3, TCGv arg4, |
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TCGv arg5) |
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{
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV(arg1); |
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*gen_opparam_ptr++ = GET_TCGV(arg2); |
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*gen_opparam_ptr++ = GET_TCGV(arg3); |
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*gen_opparam_ptr++ = GET_TCGV(arg4); |
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*gen_opparam_ptr++ = GET_TCGV(arg5); |
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} |
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static inline void tcg_gen_op5i(int opc, TCGv arg1, TCGv arg2, |
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TCGv arg3, TCGv arg4, |
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TCGArg arg5) |
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{
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV(arg1); |
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*gen_opparam_ptr++ = GET_TCGV(arg2); |
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*gen_opparam_ptr++ = GET_TCGV(arg3); |
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*gen_opparam_ptr++ = GET_TCGV(arg4); |
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*gen_opparam_ptr++ = arg5; |
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} |
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static inline void tcg_gen_op6(int opc, TCGv arg1, TCGv arg2, |
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TCGv arg3, TCGv arg4, |
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TCGv arg5, TCGv arg6) |
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{
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV(arg1); |
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*gen_opparam_ptr++ = GET_TCGV(arg2); |
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*gen_opparam_ptr++ = GET_TCGV(arg3); |
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*gen_opparam_ptr++ = GET_TCGV(arg4); |
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*gen_opparam_ptr++ = GET_TCGV(arg5); |
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*gen_opparam_ptr++ = GET_TCGV(arg6); |
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} |
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static inline void tcg_gen_op6ii(int opc, TCGv arg1, TCGv arg2, |
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TCGv arg3, TCGv arg4, |
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TCGArg arg5, TCGArg arg6) |
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{
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV(arg1); |
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*gen_opparam_ptr++ = GET_TCGV(arg2); |
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*gen_opparam_ptr++ = GET_TCGV(arg3); |
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*gen_opparam_ptr++ = GET_TCGV(arg4); |
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*gen_opparam_ptr++ = arg5; |
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*gen_opparam_ptr++ = arg6; |
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} |
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static inline void gen_set_label(int n) |
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{
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tcg_gen_op1i(INDEX_op_set_label, n); |
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} |
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static inline void tcg_gen_br(int label) |
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{
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tcg_gen_op1i(INDEX_op_br, label); |
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} |
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static inline void tcg_gen_mov_i32(TCGv ret, TCGv arg) |
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{
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tcg_gen_op2(INDEX_op_mov_i32, ret, arg); |
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} |
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static inline void tcg_gen_movi_i32(TCGv ret, int32_t arg) |
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{
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tcg_gen_op2i(INDEX_op_movi_i32, ret, arg); |
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} |
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/* helper calls */
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#define TCG_HELPER_CALL_FLAGS 0 |
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static inline void tcg_gen_helper_0_0(void *func) |
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{
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tcg_gen_call(&tcg_ctx, |
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tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS, |
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0, NULL, 0, NULL); |
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} |
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static inline void tcg_gen_helper_0_1(void *func, TCGv arg) |
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{
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tcg_gen_call(&tcg_ctx, |
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tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS, |
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0, NULL, 1, &arg); |
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} |
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static inline void tcg_gen_helper_0_2(void *func, TCGv arg1, TCGv arg2) |
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{
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TCGv args[2];
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args[0] = arg1;
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args[1] = arg2;
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tcg_gen_call(&tcg_ctx, |
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tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS, |
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0, NULL, 2, args); |
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} |
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static inline void tcg_gen_helper_0_4(void *func, TCGv arg1, TCGv arg2, |
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TCGv arg3, TCGv arg4) |
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{
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TCGv args[4];
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args[0] = arg1;
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args[1] = arg2;
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args[2] = arg3;
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args[3] = arg4;
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tcg_gen_call(&tcg_ctx, |
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tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS, |
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0, NULL, 4, args); |
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} |
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static inline void tcg_gen_helper_1_0(void *func, TCGv ret) |
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{
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tcg_gen_call(&tcg_ctx, |
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tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS, |
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1, &ret, 0, NULL); |
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} |
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static inline void tcg_gen_helper_1_1(void *func, TCGv ret, TCGv arg1) |
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{
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tcg_gen_call(&tcg_ctx, |
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tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS, |
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1, &ret, 1, &arg1); |
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} |
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static inline void tcg_gen_helper_1_2(void *func, TCGv ret, |
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TCGv arg1, TCGv arg2) |
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{
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TCGv args[2];
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args[0] = arg1;
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args[1] = arg2;
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tcg_gen_call(&tcg_ctx, |
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tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS, |
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1, &ret, 2, args); |
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} |
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static inline void tcg_gen_helper_1_3(void *func, TCGv ret, |
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TCGv arg1, TCGv arg2, TCGv arg3) |
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{
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TCGv args[3];
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args[0] = arg1;
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args[1] = arg2;
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args[2] = arg3;
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tcg_gen_call(&tcg_ctx, |
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tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS, |
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1, &ret, 3, args); |
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} |
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static inline void tcg_gen_helper_1_4(void *func, TCGv ret, |
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TCGv arg1, TCGv arg2, TCGv arg3, |
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TCGv arg4) |
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{
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TCGv args[4];
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args[0] = arg1;
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args[1] = arg2;
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args[2] = arg3;
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args[3] = arg4;
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tcg_gen_call(&tcg_ctx, |
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tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS, |
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1, &ret, 4, args); |
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} |
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/* 32 bit ops */
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static inline void tcg_gen_ld8u_i32(TCGv ret, TCGv arg2, tcg_target_long offset) |
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{
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tcg_gen_op3i(INDEX_op_ld8u_i32, ret, arg2, offset); |
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} |
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static inline void tcg_gen_ld8s_i32(TCGv ret, TCGv arg2, tcg_target_long offset) |
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{
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tcg_gen_op3i(INDEX_op_ld8s_i32, ret, arg2, offset); |
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} |
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static inline void tcg_gen_ld16u_i32(TCGv ret, TCGv arg2, tcg_target_long offset) |
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{
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tcg_gen_op3i(INDEX_op_ld16u_i32, ret, arg2, offset); |
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} |
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static inline void tcg_gen_ld16s_i32(TCGv ret, TCGv arg2, tcg_target_long offset) |
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{
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tcg_gen_op3i(INDEX_op_ld16s_i32, ret, arg2, offset); |
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} |
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static inline void tcg_gen_ld_i32(TCGv ret, TCGv arg2, tcg_target_long offset) |
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{
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tcg_gen_op3i(INDEX_op_ld_i32, ret, arg2, offset); |
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} |
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static inline void tcg_gen_st8_i32(TCGv arg1, TCGv arg2, tcg_target_long offset) |
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{
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tcg_gen_op3i(INDEX_op_st8_i32, arg1, arg2, offset); |
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} |
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static inline void tcg_gen_st16_i32(TCGv arg1, TCGv arg2, tcg_target_long offset) |
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{
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tcg_gen_op3i(INDEX_op_st16_i32, arg1, arg2, offset); |
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} |
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static inline void tcg_gen_st_i32(TCGv arg1, TCGv arg2, tcg_target_long offset) |
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{
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tcg_gen_op3i(INDEX_op_st_i32, arg1, arg2, offset); |
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} |
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static inline void tcg_gen_add_i32(TCGv ret, TCGv arg1, TCGv arg2) |
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{
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tcg_gen_op3(INDEX_op_add_i32, ret, arg1, arg2); |
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} |
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static inline void tcg_gen_addi_i32(TCGv ret, TCGv arg1, int32_t arg2) |
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{
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/* some cases can be optimized here */
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if (arg2 == 0) { |
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tcg_gen_mov_i32(ret, arg1); |
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} else {
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tcg_gen_add_i32(ret, arg1, tcg_const_i32(arg2)); |
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} |
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} |
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|
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static inline void tcg_gen_sub_i32(TCGv ret, TCGv arg1, TCGv arg2) |
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{
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tcg_gen_op3(INDEX_op_sub_i32, ret, arg1, arg2); |
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} |
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static inline void tcg_gen_subi_i32(TCGv ret, TCGv arg1, int32_t arg2) |
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{
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/* some cases can be optimized here */
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if (arg2 == 0) { |
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tcg_gen_mov_i32(ret, arg1); |
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} else {
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tcg_gen_sub_i32(ret, arg1, tcg_const_i32(arg2)); |
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} |
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} |
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|
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static inline void tcg_gen_and_i32(TCGv ret, TCGv arg1, TCGv arg2) |
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{
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tcg_gen_op3(INDEX_op_and_i32, ret, arg1, arg2); |
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} |
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|
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static inline void tcg_gen_andi_i32(TCGv ret, TCGv arg1, int32_t arg2) |
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{
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/* some cases can be optimized here */
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if (arg2 == 0) { |
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tcg_gen_movi_i32(ret, 0);
|
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} else if (arg2 == 0xffffffff) { |
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tcg_gen_mov_i32(ret, arg1); |
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} else {
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tcg_gen_and_i32(ret, arg1, tcg_const_i32(arg2)); |
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} |
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} |
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|
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static inline void tcg_gen_or_i32(TCGv ret, TCGv arg1, TCGv arg2) |
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{
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tcg_gen_op3(INDEX_op_or_i32, ret, arg1, arg2); |
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} |
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|
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static inline void tcg_gen_ori_i32(TCGv ret, TCGv arg1, int32_t arg2) |
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{
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/* some cases can be optimized here */
|
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if (arg2 == 0xffffffff) { |
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tcg_gen_movi_i32(ret, 0xffffffff);
|
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} else if (arg2 == 0) { |
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tcg_gen_mov_i32(ret, arg1); |
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} else {
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tcg_gen_or_i32(ret, arg1, tcg_const_i32(arg2)); |
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} |
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} |
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|
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static inline void tcg_gen_xor_i32(TCGv ret, TCGv arg1, TCGv arg2) |
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{
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tcg_gen_op3(INDEX_op_xor_i32, ret, arg1, arg2); |
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} |
| 376 |
|
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static inline void tcg_gen_xori_i32(TCGv ret, TCGv arg1, int32_t arg2) |
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{
|
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/* some cases can be optimized here */
|
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if (arg2 == 0) { |
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tcg_gen_mov_i32(ret, arg1); |
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} else {
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tcg_gen_xor_i32(ret, arg1, tcg_const_i32(arg2)); |
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} |
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} |
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|
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static inline void tcg_gen_shl_i32(TCGv ret, TCGv arg1, TCGv arg2) |
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{
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tcg_gen_op3(INDEX_op_shl_i32, ret, arg1, arg2); |
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} |
| 391 |
|
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static inline void tcg_gen_shli_i32(TCGv ret, TCGv arg1, int32_t arg2) |
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{
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tcg_gen_shl_i32(ret, arg1, tcg_const_i32(arg2)); |
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} |
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|
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static inline void tcg_gen_shr_i32(TCGv ret, TCGv arg1, TCGv arg2) |
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{
|
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tcg_gen_op3(INDEX_op_shr_i32, ret, arg1, arg2); |
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} |
| 401 |
|
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static inline void tcg_gen_shri_i32(TCGv ret, TCGv arg1, int32_t arg2) |
| 403 |
{
|
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tcg_gen_shr_i32(ret, arg1, tcg_const_i32(arg2)); |
| 405 |
} |
| 406 |
|
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static inline void tcg_gen_sar_i32(TCGv ret, TCGv arg1, TCGv arg2) |
| 408 |
{
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tcg_gen_op3(INDEX_op_sar_i32, ret, arg1, arg2); |
| 410 |
} |
| 411 |
|
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static inline void tcg_gen_sari_i32(TCGv ret, TCGv arg1, int32_t arg2) |
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{
|
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tcg_gen_sar_i32(ret, arg1, tcg_const_i32(arg2)); |
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} |
| 416 |
|
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static inline void tcg_gen_brcond_i32(int cond, TCGv arg1, TCGv arg2, |
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int label_index)
|
| 419 |
{
|
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tcg_gen_op4ii(INDEX_op_brcond_i32, arg1, arg2, cond, label_index); |
| 421 |
} |
| 422 |
|
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static inline void tcg_gen_mul_i32(TCGv ret, TCGv arg1, TCGv arg2) |
| 424 |
{
|
| 425 |
tcg_gen_op3(INDEX_op_mul_i32, ret, arg1, arg2); |
| 426 |
} |
| 427 |
|
| 428 |
#ifdef TCG_TARGET_HAS_div_i32
|
| 429 |
static inline void tcg_gen_div_i32(TCGv ret, TCGv arg1, TCGv arg2) |
| 430 |
{
|
| 431 |
tcg_gen_op3(INDEX_op_div_i32, ret, arg1, arg2); |
| 432 |
} |
| 433 |
|
| 434 |
static inline void tcg_gen_rem_i32(TCGv ret, TCGv arg1, TCGv arg2) |
| 435 |
{
|
| 436 |
tcg_gen_op3(INDEX_op_rem_i32, ret, arg1, arg2); |
| 437 |
} |
| 438 |
|
| 439 |
static inline void tcg_gen_divu_i32(TCGv ret, TCGv arg1, TCGv arg2) |
| 440 |
{
|
| 441 |
tcg_gen_op3(INDEX_op_divu_i32, ret, arg1, arg2); |
| 442 |
} |
| 443 |
|
| 444 |
static inline void tcg_gen_remu_i32(TCGv ret, TCGv arg1, TCGv arg2) |
| 445 |
{
|
| 446 |
tcg_gen_op3(INDEX_op_remu_i32, ret, arg1, arg2); |
| 447 |
} |
| 448 |
#else
|
| 449 |
static inline void tcg_gen_div_i32(TCGv ret, TCGv arg1, TCGv arg2) |
| 450 |
{
|
| 451 |
TCGv t0; |
| 452 |
t0 = tcg_temp_new(TCG_TYPE_I32); |
| 453 |
tcg_gen_sari_i32(t0, arg1, 31);
|
| 454 |
tcg_gen_op5(INDEX_op_div2_i32, ret, t0, arg1, t0, arg2); |
| 455 |
} |
| 456 |
|
| 457 |
static inline void tcg_gen_rem_i32(TCGv ret, TCGv arg1, TCGv arg2) |
| 458 |
{
|
| 459 |
TCGv t0; |
| 460 |
t0 = tcg_temp_new(TCG_TYPE_I32); |
| 461 |
tcg_gen_sari_i32(t0, arg1, 31);
|
| 462 |
tcg_gen_op5(INDEX_op_div2_i32, t0, ret, arg1, t0, arg2); |
| 463 |
} |
| 464 |
|
| 465 |
static inline void tcg_gen_divu_i32(TCGv ret, TCGv arg1, TCGv arg2) |
| 466 |
{
|
| 467 |
TCGv t0; |
| 468 |
t0 = tcg_temp_new(TCG_TYPE_I32); |
| 469 |
tcg_gen_movi_i32(t0, 0);
|
| 470 |
tcg_gen_op5(INDEX_op_divu2_i32, ret, t0, arg1, t0, arg2); |
| 471 |
} |
| 472 |
|
| 473 |
static inline void tcg_gen_remu_i32(TCGv ret, TCGv arg1, TCGv arg2) |
| 474 |
{
|
| 475 |
TCGv t0; |
| 476 |
t0 = tcg_temp_new(TCG_TYPE_I32); |
| 477 |
tcg_gen_movi_i32(t0, 0);
|
| 478 |
tcg_gen_op5(INDEX_op_divu2_i32, t0, ret, arg1, t0, arg2); |
| 479 |
} |
| 480 |
#endif
|
| 481 |
|
| 482 |
#if TCG_TARGET_REG_BITS == 32 |
| 483 |
|
| 484 |
static inline void tcg_gen_mov_i64(TCGv ret, TCGv arg) |
| 485 |
{
|
| 486 |
tcg_gen_mov_i32(ret, arg); |
| 487 |
tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); |
| 488 |
} |
| 489 |
|
| 490 |
static inline void tcg_gen_movi_i64(TCGv ret, int64_t arg) |
| 491 |
{
|
| 492 |
tcg_gen_movi_i32(ret, arg); |
| 493 |
tcg_gen_movi_i32(TCGV_HIGH(ret), arg >> 32);
|
| 494 |
} |
| 495 |
|
| 496 |
static inline void tcg_gen_ld8u_i64(TCGv ret, TCGv arg2, tcg_target_long offset) |
| 497 |
{
|
| 498 |
tcg_gen_ld8u_i32(ret, arg2, offset); |
| 499 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
| 500 |
} |
| 501 |
|
| 502 |
static inline void tcg_gen_ld8s_i64(TCGv ret, TCGv arg2, tcg_target_long offset) |
| 503 |
{
|
| 504 |
tcg_gen_ld8s_i32(ret, arg2, offset); |
| 505 |
tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
|
| 506 |
} |
| 507 |
|
| 508 |
static inline void tcg_gen_ld16u_i64(TCGv ret, TCGv arg2, tcg_target_long offset) |
| 509 |
{
|
| 510 |
tcg_gen_ld16u_i32(ret, arg2, offset); |
| 511 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
| 512 |
} |
| 513 |
|
| 514 |
static inline void tcg_gen_ld16s_i64(TCGv ret, TCGv arg2, tcg_target_long offset) |
| 515 |
{
|
| 516 |
tcg_gen_ld16s_i32(ret, arg2, offset); |
| 517 |
tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
|
| 518 |
} |
| 519 |
|
| 520 |
static inline void tcg_gen_ld32u_i64(TCGv ret, TCGv arg2, tcg_target_long offset) |
| 521 |
{
|
| 522 |
tcg_gen_ld_i32(ret, arg2, offset); |
| 523 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
| 524 |
} |
| 525 |
|
| 526 |
static inline void tcg_gen_ld32s_i64(TCGv ret, TCGv arg2, tcg_target_long offset) |
| 527 |
{
|
| 528 |
tcg_gen_ld_i32(ret, arg2, offset); |
| 529 |
tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
|
| 530 |
} |
| 531 |
|
| 532 |
static inline void tcg_gen_ld_i64(TCGv ret, TCGv arg2, tcg_target_long offset) |
| 533 |
{
|
| 534 |
/* since arg2 and ret have different types, they cannot be the
|
| 535 |
same temporary */
|
| 536 |
#ifdef TCG_TARGET_WORDS_BIGENDIAN
|
| 537 |
tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset); |
| 538 |
tcg_gen_ld_i32(ret, arg2, offset + 4);
|
| 539 |
#else
|
| 540 |
tcg_gen_ld_i32(ret, arg2, offset); |
| 541 |
tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset + 4);
|
| 542 |
#endif
|
| 543 |
} |
| 544 |
|
| 545 |
static inline void tcg_gen_st8_i64(TCGv arg1, TCGv arg2, tcg_target_long offset) |
| 546 |
{
|
| 547 |
tcg_gen_st8_i32(arg1, arg2, offset); |
| 548 |
} |
| 549 |
|
| 550 |
static inline void tcg_gen_st16_i64(TCGv arg1, TCGv arg2, tcg_target_long offset) |
| 551 |
{
|
| 552 |
tcg_gen_st16_i32(arg1, arg2, offset); |
| 553 |
} |
| 554 |
|
| 555 |
static inline void tcg_gen_st32_i64(TCGv arg1, TCGv arg2, tcg_target_long offset) |
| 556 |
{
|
| 557 |
tcg_gen_st_i32(arg1, arg2, offset); |
| 558 |
} |
| 559 |
|
| 560 |
static inline void tcg_gen_st_i64(TCGv arg1, TCGv arg2, tcg_target_long offset) |
| 561 |
{
|
| 562 |
#ifdef TCG_TARGET_WORDS_BIGENDIAN
|
| 563 |
tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset); |
| 564 |
tcg_gen_st_i32(arg1, arg2, offset + 4);
|
| 565 |
#else
|
| 566 |
tcg_gen_st_i32(arg1, arg2, offset); |
| 567 |
tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset + 4);
|
| 568 |
#endif
|
| 569 |
} |
| 570 |
|
| 571 |
static inline void tcg_gen_add_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 572 |
{
|
| 573 |
tcg_gen_op6(INDEX_op_add2_i32, ret, TCGV_HIGH(ret), |
| 574 |
arg1, TCGV_HIGH(arg1), arg2, TCGV_HIGH(arg2)); |
| 575 |
} |
| 576 |
|
| 577 |
static inline void tcg_gen_addi_i64(TCGv ret, TCGv arg1, int64_t arg2) |
| 578 |
{
|
| 579 |
tcg_gen_add_i64(ret, arg1, tcg_const_i64(arg2)); |
| 580 |
} |
| 581 |
|
| 582 |
static inline void tcg_gen_sub_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 583 |
{
|
| 584 |
tcg_gen_op6(INDEX_op_sub2_i32, ret, TCGV_HIGH(ret), |
| 585 |
arg1, TCGV_HIGH(arg1), arg2, TCGV_HIGH(arg2)); |
| 586 |
} |
| 587 |
|
| 588 |
static inline void tcg_gen_subi_i64(TCGv ret, TCGv arg1, int64_t arg2) |
| 589 |
{
|
| 590 |
tcg_gen_sub_i64(ret, arg1, tcg_const_i64(arg2)); |
| 591 |
} |
| 592 |
|
| 593 |
static inline void tcg_gen_and_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 594 |
{
|
| 595 |
tcg_gen_and_i32(ret, arg1, arg2); |
| 596 |
tcg_gen_and_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
| 597 |
} |
| 598 |
|
| 599 |
static inline void tcg_gen_andi_i64(TCGv ret, TCGv arg1, int64_t arg2) |
| 600 |
{
|
| 601 |
tcg_gen_andi_i32(ret, arg1, arg2); |
| 602 |
tcg_gen_andi_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
|
| 603 |
} |
| 604 |
|
| 605 |
static inline void tcg_gen_or_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 606 |
{
|
| 607 |
tcg_gen_or_i32(ret, arg1, arg2); |
| 608 |
tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
| 609 |
} |
| 610 |
|
| 611 |
static inline void tcg_gen_ori_i64(TCGv ret, TCGv arg1, int64_t arg2) |
| 612 |
{
|
| 613 |
tcg_gen_ori_i32(ret, arg1, arg2); |
| 614 |
tcg_gen_ori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
|
| 615 |
} |
| 616 |
|
| 617 |
static inline void tcg_gen_xor_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 618 |
{
|
| 619 |
tcg_gen_xor_i32(ret, arg1, arg2); |
| 620 |
tcg_gen_xor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
| 621 |
} |
| 622 |
|
| 623 |
static inline void tcg_gen_xori_i64(TCGv ret, TCGv arg1, int64_t arg2) |
| 624 |
{
|
| 625 |
tcg_gen_xori_i32(ret, arg1, arg2); |
| 626 |
tcg_gen_xori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
|
| 627 |
} |
| 628 |
|
| 629 |
/* XXX: use generic code when basic block handling is OK or CPU
|
| 630 |
specific code (x86) */
|
| 631 |
static inline void tcg_gen_shl_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 632 |
{
|
| 633 |
tcg_gen_helper_1_2(tcg_helper_shl_i64, ret, arg1, arg2); |
| 634 |
} |
| 635 |
|
| 636 |
static inline void tcg_gen_shli_i64(TCGv ret, TCGv arg1, int64_t arg2) |
| 637 |
{
|
| 638 |
tcg_gen_shifti_i64(ret, arg1, arg2, 0, 0); |
| 639 |
} |
| 640 |
|
| 641 |
static inline void tcg_gen_shr_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 642 |
{
|
| 643 |
tcg_gen_helper_1_2(tcg_helper_shr_i64, ret, arg1, arg2); |
| 644 |
} |
| 645 |
|
| 646 |
static inline void tcg_gen_shri_i64(TCGv ret, TCGv arg1, int64_t arg2) |
| 647 |
{
|
| 648 |
tcg_gen_shifti_i64(ret, arg1, arg2, 1, 0); |
| 649 |
} |
| 650 |
|
| 651 |
static inline void tcg_gen_sar_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 652 |
{
|
| 653 |
tcg_gen_helper_1_2(tcg_helper_sar_i64, ret, arg1, arg2); |
| 654 |
} |
| 655 |
|
| 656 |
static inline void tcg_gen_sari_i64(TCGv ret, TCGv arg1, int64_t arg2) |
| 657 |
{
|
| 658 |
tcg_gen_shifti_i64(ret, arg1, arg2, 1, 1); |
| 659 |
} |
| 660 |
|
| 661 |
static inline void tcg_gen_brcond_i64(int cond, TCGv arg1, TCGv arg2, |
| 662 |
int label_index)
|
| 663 |
{
|
| 664 |
tcg_gen_op6ii(INDEX_op_brcond2_i32, |
| 665 |
arg1, TCGV_HIGH(arg1), arg2, TCGV_HIGH(arg2), |
| 666 |
cond, label_index); |
| 667 |
} |
| 668 |
|
| 669 |
static inline void tcg_gen_mul_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 670 |
{
|
| 671 |
TCGv t0, t1; |
| 672 |
|
| 673 |
t0 = tcg_temp_new(TCG_TYPE_I64); |
| 674 |
t1 = tcg_temp_new(TCG_TYPE_I32); |
| 675 |
|
| 676 |
tcg_gen_op4(INDEX_op_mulu2_i32, t0, TCGV_HIGH(t0), arg1, arg2); |
| 677 |
|
| 678 |
tcg_gen_mul_i32(t1, arg1, TCGV_HIGH(arg2)); |
| 679 |
tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1); |
| 680 |
tcg_gen_mul_i32(t1, TCGV_HIGH(arg1), arg2); |
| 681 |
tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1); |
| 682 |
|
| 683 |
tcg_gen_mov_i64(ret, t0); |
| 684 |
} |
| 685 |
|
| 686 |
static inline void tcg_gen_div_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 687 |
{
|
| 688 |
tcg_gen_helper_1_2(tcg_helper_div_i64, ret, arg1, arg2); |
| 689 |
} |
| 690 |
|
| 691 |
static inline void tcg_gen_rem_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 692 |
{
|
| 693 |
tcg_gen_helper_1_2(tcg_helper_rem_i64, ret, arg1, arg2); |
| 694 |
} |
| 695 |
|
| 696 |
static inline void tcg_gen_divu_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 697 |
{
|
| 698 |
tcg_gen_helper_1_2(tcg_helper_divu_i64, ret, arg1, arg2); |
| 699 |
} |
| 700 |
|
| 701 |
static inline void tcg_gen_remu_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 702 |
{
|
| 703 |
tcg_gen_helper_1_2(tcg_helper_remu_i64, ret, arg1, arg2); |
| 704 |
} |
| 705 |
|
| 706 |
#else
|
| 707 |
|
| 708 |
static inline void tcg_gen_mov_i64(TCGv ret, TCGv arg) |
| 709 |
{
|
| 710 |
tcg_gen_op2(INDEX_op_mov_i64, ret, arg); |
| 711 |
} |
| 712 |
|
| 713 |
static inline void tcg_gen_movi_i64(TCGv ret, int64_t arg) |
| 714 |
{
|
| 715 |
tcg_gen_op2i(INDEX_op_movi_i64, ret, arg); |
| 716 |
} |
| 717 |
|
| 718 |
static inline void tcg_gen_ld8u_i64(TCGv ret, TCGv arg2, |
| 719 |
tcg_target_long offset) |
| 720 |
{
|
| 721 |
tcg_gen_op3i(INDEX_op_ld8u_i64, ret, arg2, offset); |
| 722 |
} |
| 723 |
|
| 724 |
static inline void tcg_gen_ld8s_i64(TCGv ret, TCGv arg2, |
| 725 |
tcg_target_long offset) |
| 726 |
{
|
| 727 |
tcg_gen_op3i(INDEX_op_ld8s_i64, ret, arg2, offset); |
| 728 |
} |
| 729 |
|
| 730 |
static inline void tcg_gen_ld16u_i64(TCGv ret, TCGv arg2, |
| 731 |
tcg_target_long offset) |
| 732 |
{
|
| 733 |
tcg_gen_op3i(INDEX_op_ld16u_i64, ret, arg2, offset); |
| 734 |
} |
| 735 |
|
| 736 |
static inline void tcg_gen_ld16s_i64(TCGv ret, TCGv arg2, |
| 737 |
tcg_target_long offset) |
| 738 |
{
|
| 739 |
tcg_gen_op3i(INDEX_op_ld16s_i64, ret, arg2, offset); |
| 740 |
} |
| 741 |
|
| 742 |
static inline void tcg_gen_ld32u_i64(TCGv ret, TCGv arg2, |
| 743 |
tcg_target_long offset) |
| 744 |
{
|
| 745 |
tcg_gen_op3i(INDEX_op_ld32u_i64, ret, arg2, offset); |
| 746 |
} |
| 747 |
|
| 748 |
static inline void tcg_gen_ld32s_i64(TCGv ret, TCGv arg2, |
| 749 |
tcg_target_long offset) |
| 750 |
{
|
| 751 |
tcg_gen_op3i(INDEX_op_ld32s_i64, ret, arg2, offset); |
| 752 |
} |
| 753 |
|
| 754 |
static inline void tcg_gen_ld_i64(TCGv ret, TCGv arg2, tcg_target_long offset) |
| 755 |
{
|
| 756 |
tcg_gen_op3i(INDEX_op_ld_i64, ret, arg2, offset); |
| 757 |
} |
| 758 |
|
| 759 |
static inline void tcg_gen_st8_i64(TCGv arg1, TCGv arg2, |
| 760 |
tcg_target_long offset) |
| 761 |
{
|
| 762 |
tcg_gen_op3i(INDEX_op_st8_i64, arg1, arg2, offset); |
| 763 |
} |
| 764 |
|
| 765 |
static inline void tcg_gen_st16_i64(TCGv arg1, TCGv arg2, |
| 766 |
tcg_target_long offset) |
| 767 |
{
|
| 768 |
tcg_gen_op3i(INDEX_op_st16_i64, arg1, arg2, offset); |
| 769 |
} |
| 770 |
|
| 771 |
static inline void tcg_gen_st32_i64(TCGv arg1, TCGv arg2, |
| 772 |
tcg_target_long offset) |
| 773 |
{
|
| 774 |
tcg_gen_op3i(INDEX_op_st32_i64, arg1, arg2, offset); |
| 775 |
} |
| 776 |
|
| 777 |
static inline void tcg_gen_st_i64(TCGv arg1, TCGv arg2, tcg_target_long offset) |
| 778 |
{
|
| 779 |
tcg_gen_op3i(INDEX_op_st_i64, arg1, arg2, offset); |
| 780 |
} |
| 781 |
|
| 782 |
static inline void tcg_gen_add_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 783 |
{
|
| 784 |
tcg_gen_op3(INDEX_op_add_i64, ret, arg1, arg2); |
| 785 |
} |
| 786 |
|
| 787 |
static inline void tcg_gen_addi_i64(TCGv ret, TCGv arg1, int64_t arg2) |
| 788 |
{
|
| 789 |
tcg_gen_add_i64(ret, arg1, tcg_const_i64(arg2)); |
| 790 |
} |
| 791 |
|
| 792 |
static inline void tcg_gen_sub_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 793 |
{
|
| 794 |
tcg_gen_op3(INDEX_op_sub_i64, ret, arg1, arg2); |
| 795 |
} |
| 796 |
|
| 797 |
static inline void tcg_gen_subi_i64(TCGv ret, TCGv arg1, int64_t arg2) |
| 798 |
{
|
| 799 |
tcg_gen_sub_i64(ret, arg1, tcg_const_i64(arg2)); |
| 800 |
} |
| 801 |
|
| 802 |
static inline void tcg_gen_and_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 803 |
{
|
| 804 |
tcg_gen_op3(INDEX_op_and_i64, ret, arg1, arg2); |
| 805 |
} |
| 806 |
|
| 807 |
static inline void tcg_gen_andi_i64(TCGv ret, TCGv arg1, int64_t arg2) |
| 808 |
{
|
| 809 |
tcg_gen_and_i64(ret, arg1, tcg_const_i64(arg2)); |
| 810 |
} |
| 811 |
|
| 812 |
static inline void tcg_gen_or_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 813 |
{
|
| 814 |
tcg_gen_op3(INDEX_op_or_i64, ret, arg1, arg2); |
| 815 |
} |
| 816 |
|
| 817 |
static inline void tcg_gen_ori_i64(TCGv ret, TCGv arg1, int64_t arg2) |
| 818 |
{
|
| 819 |
tcg_gen_or_i64(ret, arg1, tcg_const_i64(arg2)); |
| 820 |
} |
| 821 |
|
| 822 |
static inline void tcg_gen_xor_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 823 |
{
|
| 824 |
tcg_gen_op3(INDEX_op_xor_i64, ret, arg1, arg2); |
| 825 |
} |
| 826 |
|
| 827 |
static inline void tcg_gen_xori_i64(TCGv ret, TCGv arg1, int64_t arg2) |
| 828 |
{
|
| 829 |
tcg_gen_xor_i64(ret, arg1, tcg_const_i64(arg2)); |
| 830 |
} |
| 831 |
|
| 832 |
static inline void tcg_gen_shl_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 833 |
{
|
| 834 |
tcg_gen_op3(INDEX_op_shl_i64, ret, arg1, arg2); |
| 835 |
} |
| 836 |
|
| 837 |
static inline void tcg_gen_shli_i64(TCGv ret, TCGv arg1, int64_t arg2) |
| 838 |
{
|
| 839 |
tcg_gen_shl_i64(ret, arg1, tcg_const_i64(arg2)); |
| 840 |
} |
| 841 |
|
| 842 |
static inline void tcg_gen_shr_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 843 |
{
|
| 844 |
tcg_gen_op3(INDEX_op_shr_i64, ret, arg1, arg2); |
| 845 |
} |
| 846 |
|
| 847 |
static inline void tcg_gen_shri_i64(TCGv ret, TCGv arg1, int64_t arg2) |
| 848 |
{
|
| 849 |
tcg_gen_shr_i64(ret, arg1, tcg_const_i64(arg2)); |
| 850 |
} |
| 851 |
|
| 852 |
static inline void tcg_gen_sar_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 853 |
{
|
| 854 |
tcg_gen_op3(INDEX_op_sar_i64, ret, arg1, arg2); |
| 855 |
} |
| 856 |
|
| 857 |
static inline void tcg_gen_sari_i64(TCGv ret, TCGv arg1, int64_t arg2) |
| 858 |
{
|
| 859 |
tcg_gen_sar_i64(ret, arg1, tcg_const_i64(arg2)); |
| 860 |
} |
| 861 |
|
| 862 |
static inline void tcg_gen_brcond_i64(int cond, TCGv arg1, TCGv arg2, |
| 863 |
int label_index)
|
| 864 |
{
|
| 865 |
tcg_gen_op4ii(INDEX_op_brcond_i64, arg1, arg2, cond, label_index); |
| 866 |
} |
| 867 |
|
| 868 |
static inline void tcg_gen_mul_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 869 |
{
|
| 870 |
tcg_gen_op3(INDEX_op_mul_i64, ret, arg1, arg2); |
| 871 |
} |
| 872 |
|
| 873 |
#ifdef TCG_TARGET_HAS_div_i64
|
| 874 |
static inline void tcg_gen_div_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 875 |
{
|
| 876 |
tcg_gen_op3(INDEX_op_div_i64, ret, arg1, arg2); |
| 877 |
} |
| 878 |
|
| 879 |
static inline void tcg_gen_rem_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 880 |
{
|
| 881 |
tcg_gen_op3(INDEX_op_rem_i64, ret, arg1, arg2); |
| 882 |
} |
| 883 |
|
| 884 |
static inline void tcg_gen_divu_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 885 |
{
|
| 886 |
tcg_gen_op3(INDEX_op_divu_i64, ret, arg1, arg2); |
| 887 |
} |
| 888 |
|
| 889 |
static inline void tcg_gen_remu_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 890 |
{
|
| 891 |
tcg_gen_op3(INDEX_op_remu_i64, ret, arg1, arg2); |
| 892 |
} |
| 893 |
#else
|
| 894 |
static inline void tcg_gen_div_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 895 |
{
|
| 896 |
TCGv t0; |
| 897 |
t0 = tcg_temp_new(TCG_TYPE_I64); |
| 898 |
tcg_gen_sari_i64(t0, arg1, 63);
|
| 899 |
tcg_gen_op5(INDEX_op_div2_i64, ret, t0, arg1, t0, arg2); |
| 900 |
} |
| 901 |
|
| 902 |
static inline void tcg_gen_rem_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 903 |
{
|
| 904 |
TCGv t0; |
| 905 |
t0 = tcg_temp_new(TCG_TYPE_I64); |
| 906 |
tcg_gen_sari_i64(t0, arg1, 63);
|
| 907 |
tcg_gen_op5(INDEX_op_div2_i64, t0, ret, arg1, t0, arg2); |
| 908 |
} |
| 909 |
|
| 910 |
static inline void tcg_gen_divu_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 911 |
{
|
| 912 |
TCGv t0; |
| 913 |
t0 = tcg_temp_new(TCG_TYPE_I64); |
| 914 |
tcg_gen_movi_i64(t0, 0);
|
| 915 |
tcg_gen_op5(INDEX_op_divu2_i64, ret, t0, arg1, t0, arg2); |
| 916 |
} |
| 917 |
|
| 918 |
static inline void tcg_gen_remu_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 919 |
{
|
| 920 |
TCGv t0; |
| 921 |
t0 = tcg_temp_new(TCG_TYPE_I64); |
| 922 |
tcg_gen_movi_i64(t0, 0);
|
| 923 |
tcg_gen_op5(INDEX_op_divu2_i64, t0, ret, arg1, t0, arg2); |
| 924 |
} |
| 925 |
#endif
|
| 926 |
|
| 927 |
#endif
|
| 928 |
|
| 929 |
/***************************************/
|
| 930 |
/* optional operations */
|
| 931 |
|
| 932 |
static inline void tcg_gen_ext8s_i32(TCGv ret, TCGv arg) |
| 933 |
{
|
| 934 |
#ifdef TCG_TARGET_HAS_ext8s_i32
|
| 935 |
tcg_gen_op2(INDEX_op_ext8s_i32, ret, arg); |
| 936 |
#else
|
| 937 |
tcg_gen_shli_i32(ret, arg, 24);
|
| 938 |
tcg_gen_sari_i32(ret, ret, 24);
|
| 939 |
#endif
|
| 940 |
} |
| 941 |
|
| 942 |
static inline void tcg_gen_ext16s_i32(TCGv ret, TCGv arg) |
| 943 |
{
|
| 944 |
#ifdef TCG_TARGET_HAS_ext16s_i32
|
| 945 |
tcg_gen_op2(INDEX_op_ext16s_i32, ret, arg); |
| 946 |
#else
|
| 947 |
tcg_gen_shli_i32(ret, arg, 16);
|
| 948 |
tcg_gen_sari_i32(ret, ret, 16);
|
| 949 |
#endif
|
| 950 |
} |
| 951 |
|
| 952 |
/* Note: we assume the two high bytes are set to zero */
|
| 953 |
static inline void tcg_gen_bswap16_i32(TCGv ret, TCGv arg) |
| 954 |
{
|
| 955 |
#ifdef TCG_TARGET_HAS_bswap16_i32
|
| 956 |
tcg_gen_op2(INDEX_op_bswap16_i32, ret, arg); |
| 957 |
#else
|
| 958 |
TCGv t0, t1; |
| 959 |
t0 = tcg_temp_new(TCG_TYPE_I32); |
| 960 |
t1 = tcg_temp_new(TCG_TYPE_I32); |
| 961 |
|
| 962 |
tcg_gen_shri_i32(t0, arg, 8);
|
| 963 |
tcg_gen_andi_i32(t1, arg, 0x000000ff);
|
| 964 |
tcg_gen_shli_i32(t1, t1, 8);
|
| 965 |
tcg_gen_or_i32(ret, t0, t1); |
| 966 |
#endif
|
| 967 |
} |
| 968 |
|
| 969 |
static inline void tcg_gen_bswap_i32(TCGv ret, TCGv arg) |
| 970 |
{
|
| 971 |
#ifdef TCG_TARGET_HAS_bswap_i32
|
| 972 |
tcg_gen_op2(INDEX_op_bswap_i32, ret, arg); |
| 973 |
#else
|
| 974 |
TCGv t0, t1; |
| 975 |
t0 = tcg_temp_new(TCG_TYPE_I32); |
| 976 |
t1 = tcg_temp_new(TCG_TYPE_I32); |
| 977 |
|
| 978 |
tcg_gen_shli_i32(t0, arg, 24);
|
| 979 |
|
| 980 |
tcg_gen_andi_i32(t1, arg, 0x0000ff00);
|
| 981 |
tcg_gen_shli_i32(t1, t1, 8);
|
| 982 |
tcg_gen_or_i32(t0, t0, t1); |
| 983 |
|
| 984 |
tcg_gen_shri_i32(t1, arg, 8);
|
| 985 |
tcg_gen_andi_i32(t1, t1, 0x0000ff00);
|
| 986 |
tcg_gen_or_i32(t0, t0, t1); |
| 987 |
|
| 988 |
tcg_gen_shri_i32(t1, arg, 24);
|
| 989 |
tcg_gen_or_i32(ret, t0, t1); |
| 990 |
#endif
|
| 991 |
} |
| 992 |
|
| 993 |
#if TCG_TARGET_REG_BITS == 32 |
| 994 |
static inline void tcg_gen_ext8s_i64(TCGv ret, TCGv arg) |
| 995 |
{
|
| 996 |
tcg_gen_ext8s_i32(ret, arg); |
| 997 |
tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
|
| 998 |
} |
| 999 |
|
| 1000 |
static inline void tcg_gen_ext16s_i64(TCGv ret, TCGv arg) |
| 1001 |
{
|
| 1002 |
tcg_gen_ext16s_i32(ret, arg); |
| 1003 |
tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
|
| 1004 |
} |
| 1005 |
|
| 1006 |
static inline void tcg_gen_ext32s_i64(TCGv ret, TCGv arg) |
| 1007 |
{
|
| 1008 |
tcg_gen_mov_i32(ret, arg); |
| 1009 |
tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
|
| 1010 |
} |
| 1011 |
|
| 1012 |
static inline void tcg_gen_trunc_i64_i32(TCGv ret, TCGv arg) |
| 1013 |
{
|
| 1014 |
tcg_gen_mov_i32(ret, arg); |
| 1015 |
} |
| 1016 |
|
| 1017 |
static inline void tcg_gen_extu_i32_i64(TCGv ret, TCGv arg) |
| 1018 |
{
|
| 1019 |
tcg_gen_mov_i32(ret, arg); |
| 1020 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
| 1021 |
} |
| 1022 |
|
| 1023 |
static inline void tcg_gen_ext_i32_i64(TCGv ret, TCGv arg) |
| 1024 |
{
|
| 1025 |
tcg_gen_mov_i32(ret, arg); |
| 1026 |
tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
|
| 1027 |
} |
| 1028 |
|
| 1029 |
static inline void tcg_gen_bswap_i64(TCGv ret, TCGv arg) |
| 1030 |
{
|
| 1031 |
TCGv t0, t1; |
| 1032 |
t0 = tcg_temp_new(TCG_TYPE_I32); |
| 1033 |
t1 = tcg_temp_new(TCG_TYPE_I32); |
| 1034 |
|
| 1035 |
tcg_gen_bswap_i32(t0, arg); |
| 1036 |
tcg_gen_bswap_i32(t1, TCGV_HIGH(arg)); |
| 1037 |
tcg_gen_mov_i32(ret, t1); |
| 1038 |
tcg_gen_mov_i32(TCGV_HIGH(ret), t0); |
| 1039 |
} |
| 1040 |
#else
|
| 1041 |
|
| 1042 |
static inline void tcg_gen_ext8s_i64(TCGv ret, TCGv arg) |
| 1043 |
{
|
| 1044 |
#ifdef TCG_TARGET_HAS_ext8s_i64
|
| 1045 |
tcg_gen_op2(INDEX_op_ext8s_i64, ret, arg); |
| 1046 |
#else
|
| 1047 |
tcg_gen_shli_i64(ret, arg, 56);
|
| 1048 |
tcg_gen_sari_i64(ret, ret, 56);
|
| 1049 |
#endif
|
| 1050 |
} |
| 1051 |
|
| 1052 |
static inline void tcg_gen_ext16s_i64(TCGv ret, TCGv arg) |
| 1053 |
{
|
| 1054 |
#ifdef TCG_TARGET_HAS_ext16s_i64
|
| 1055 |
tcg_gen_op2(INDEX_op_ext16s_i64, ret, arg); |
| 1056 |
#else
|
| 1057 |
tcg_gen_shli_i64(ret, arg, 48);
|
| 1058 |
tcg_gen_sari_i64(ret, ret, 48);
|
| 1059 |
#endif
|
| 1060 |
} |
| 1061 |
|
| 1062 |
static inline void tcg_gen_ext32s_i64(TCGv ret, TCGv arg) |
| 1063 |
{
|
| 1064 |
#ifdef TCG_TARGET_HAS_ext32s_i64
|
| 1065 |
tcg_gen_op2(INDEX_op_ext32s_i64, ret, arg); |
| 1066 |
#else
|
| 1067 |
tcg_gen_shli_i64(ret, arg, 32);
|
| 1068 |
tcg_gen_sari_i64(ret, ret, 32);
|
| 1069 |
#endif
|
| 1070 |
} |
| 1071 |
|
| 1072 |
/* Note: we assume the target supports move between 32 and 64 bit
|
| 1073 |
registers. This will probably break MIPS64 targets. */
|
| 1074 |
static inline void tcg_gen_trunc_i64_i32(TCGv ret, TCGv arg) |
| 1075 |
{
|
| 1076 |
tcg_gen_mov_i32(ret, arg); |
| 1077 |
} |
| 1078 |
|
| 1079 |
/* Note: we assume the target supports move between 32 and 64 bit
|
| 1080 |
registers */
|
| 1081 |
static inline void tcg_gen_extu_i32_i64(TCGv ret, TCGv arg) |
| 1082 |
{
|
| 1083 |
tcg_gen_andi_i64(ret, arg, 0xffffffff);
|
| 1084 |
} |
| 1085 |
|
| 1086 |
/* Note: we assume the target supports move between 32 and 64 bit
|
| 1087 |
registers */
|
| 1088 |
static inline void tcg_gen_ext_i32_i64(TCGv ret, TCGv arg) |
| 1089 |
{
|
| 1090 |
tcg_gen_ext32s_i64(ret, arg); |
| 1091 |
} |
| 1092 |
|
| 1093 |
static inline void tcg_gen_bswap_i64(TCGv ret, TCGv arg) |
| 1094 |
{
|
| 1095 |
#ifdef TCG_TARGET_HAS_bswap_i64
|
| 1096 |
tcg_gen_op2(INDEX_op_bswap_i64, ret, arg); |
| 1097 |
#else
|
| 1098 |
TCGv t0, t1; |
| 1099 |
t0 = tcg_temp_new(TCG_TYPE_I32); |
| 1100 |
t1 = tcg_temp_new(TCG_TYPE_I32); |
| 1101 |
|
| 1102 |
tcg_gen_shli_i64(t0, arg, 56);
|
| 1103 |
|
| 1104 |
tcg_gen_andi_i64(t1, arg, 0x0000ff00);
|
| 1105 |
tcg_gen_shli_i64(t1, t1, 40);
|
| 1106 |
tcg_gen_or_i64(t0, t0, t1); |
| 1107 |
|
| 1108 |
tcg_gen_andi_i64(t1, arg, 0x00ff0000);
|
| 1109 |
tcg_gen_shli_i64(t1, t1, 24);
|
| 1110 |
tcg_gen_or_i64(t0, t0, t1); |
| 1111 |
|
| 1112 |
tcg_gen_andi_i64(t1, arg, 0xff000000);
|
| 1113 |
tcg_gen_shli_i64(t1, t1, 8);
|
| 1114 |
tcg_gen_or_i64(t0, t0, t1); |
| 1115 |
|
| 1116 |
tcg_gen_shri_i64(t1, arg, 8);
|
| 1117 |
tcg_gen_andi_i64(t1, t1, 0xff000000);
|
| 1118 |
tcg_gen_or_i64(t0, t0, t1); |
| 1119 |
|
| 1120 |
tcg_gen_shri_i64(t1, arg, 24);
|
| 1121 |
tcg_gen_andi_i64(t1, t1, 0x00ff0000);
|
| 1122 |
tcg_gen_or_i64(t0, t0, t1); |
| 1123 |
|
| 1124 |
tcg_gen_shri_i64(t1, arg, 40);
|
| 1125 |
tcg_gen_andi_i64(t1, t1, 0x0000ff00);
|
| 1126 |
tcg_gen_or_i64(t0, t0, t1); |
| 1127 |
|
| 1128 |
tcg_gen_shri_i64(t1, arg, 56);
|
| 1129 |
tcg_gen_or_i64(ret, t0, t1); |
| 1130 |
#endif
|
| 1131 |
} |
| 1132 |
|
| 1133 |
#endif
|
| 1134 |
|
| 1135 |
|
| 1136 |
static inline void tcg_gen_discard_i32(TCGv arg) |
| 1137 |
{
|
| 1138 |
tcg_gen_op1(INDEX_op_discard, arg); |
| 1139 |
} |
| 1140 |
|
| 1141 |
#if TCG_TARGET_REG_BITS == 32 |
| 1142 |
static inline void tcg_gen_discard_i64(TCGv arg) |
| 1143 |
{
|
| 1144 |
tcg_gen_discard_i32(arg); |
| 1145 |
tcg_gen_discard_i32(TCGV_HIGH(arg)); |
| 1146 |
} |
| 1147 |
#else
|
| 1148 |
static inline void tcg_gen_discard_i64(TCGv arg) |
| 1149 |
{
|
| 1150 |
tcg_gen_op1(INDEX_op_discard, arg); |
| 1151 |
} |
| 1152 |
#endif
|
| 1153 |
|
| 1154 |
/***************************************/
|
| 1155 |
static inline void tcg_gen_macro_2(TCGv ret0, TCGv ret1, int macro_id) |
| 1156 |
{
|
| 1157 |
tcg_gen_op3i(INDEX_op_macro_2, ret0, ret1, macro_id); |
| 1158 |
} |
| 1159 |
|
| 1160 |
/***************************************/
|
| 1161 |
/* QEMU specific operations. Their type depend on the QEMU CPU
|
| 1162 |
type. */
|
| 1163 |
#ifndef TARGET_LONG_BITS
|
| 1164 |
#error must include QEMU headers
|
| 1165 |
#endif
|
| 1166 |
|
| 1167 |
static inline void tcg_gen_exit_tb(tcg_target_long val) |
| 1168 |
{
|
| 1169 |
tcg_gen_op1i(INDEX_op_exit_tb, val); |
| 1170 |
} |
| 1171 |
|
| 1172 |
static inline void tcg_gen_goto_tb(int idx) |
| 1173 |
{
|
| 1174 |
tcg_gen_op1i(INDEX_op_goto_tb, idx); |
| 1175 |
} |
| 1176 |
|
| 1177 |
#if TCG_TARGET_REG_BITS == 32 |
| 1178 |
static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) |
| 1179 |
{
|
| 1180 |
#if TARGET_LONG_BITS == 32 |
| 1181 |
tcg_gen_op3i(INDEX_op_qemu_ld8u, ret, addr, mem_index); |
| 1182 |
#else
|
| 1183 |
tcg_gen_op4i(INDEX_op_qemu_ld8u, ret, addr, TCGV_HIGH(addr), mem_index); |
| 1184 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
| 1185 |
#endif
|
| 1186 |
} |
| 1187 |
|
| 1188 |
static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index) |
| 1189 |
{
|
| 1190 |
#if TARGET_LONG_BITS == 32 |
| 1191 |
tcg_gen_op3i(INDEX_op_qemu_ld8s, ret, addr, mem_index); |
| 1192 |
#else
|
| 1193 |
tcg_gen_op4i(INDEX_op_qemu_ld8s, ret, addr, TCGV_HIGH(addr), mem_index); |
| 1194 |
tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
|
| 1195 |
#endif
|
| 1196 |
} |
| 1197 |
|
| 1198 |
static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index) |
| 1199 |
{
|
| 1200 |
#if TARGET_LONG_BITS == 32 |
| 1201 |
tcg_gen_op3i(INDEX_op_qemu_ld16u, ret, addr, mem_index); |
| 1202 |
#else
|
| 1203 |
tcg_gen_op4i(INDEX_op_qemu_ld16u, ret, addr, TCGV_HIGH(addr), mem_index); |
| 1204 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
| 1205 |
#endif
|
| 1206 |
} |
| 1207 |
|
| 1208 |
static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index) |
| 1209 |
{
|
| 1210 |
#if TARGET_LONG_BITS == 32 |
| 1211 |
tcg_gen_op3i(INDEX_op_qemu_ld16s, ret, addr, mem_index); |
| 1212 |
#else
|
| 1213 |
tcg_gen_op4i(INDEX_op_qemu_ld16s, ret, addr, TCGV_HIGH(addr), mem_index); |
| 1214 |
tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
|
| 1215 |
#endif
|
| 1216 |
} |
| 1217 |
|
| 1218 |
static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index) |
| 1219 |
{
|
| 1220 |
#if TARGET_LONG_BITS == 32 |
| 1221 |
tcg_gen_op3i(INDEX_op_qemu_ld32u, ret, addr, mem_index); |
| 1222 |
#else
|
| 1223 |
tcg_gen_op4i(INDEX_op_qemu_ld32u, ret, addr, TCGV_HIGH(addr), mem_index); |
| 1224 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
| 1225 |
#endif
|
| 1226 |
} |
| 1227 |
|
| 1228 |
static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index) |
| 1229 |
{
|
| 1230 |
#if TARGET_LONG_BITS == 32 |
| 1231 |
tcg_gen_op3i(INDEX_op_qemu_ld32u, ret, addr, mem_index); |
| 1232 |
#else
|
| 1233 |
tcg_gen_op4i(INDEX_op_qemu_ld32u, ret, addr, TCGV_HIGH(addr), mem_index); |
| 1234 |
tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
|
| 1235 |
#endif
|
| 1236 |
} |
| 1237 |
|
| 1238 |
static inline void tcg_gen_qemu_ld64(TCGv ret, TCGv addr, int mem_index) |
| 1239 |
{
|
| 1240 |
#if TARGET_LONG_BITS == 32 |
| 1241 |
tcg_gen_op4i(INDEX_op_qemu_ld64, ret, TCGV_HIGH(ret), addr, mem_index); |
| 1242 |
#else
|
| 1243 |
tcg_gen_op5i(INDEX_op_qemu_ld64, ret, TCGV_HIGH(ret), |
| 1244 |
addr, TCGV_HIGH(addr), mem_index); |
| 1245 |
#endif
|
| 1246 |
} |
| 1247 |
|
| 1248 |
static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index) |
| 1249 |
{
|
| 1250 |
#if TARGET_LONG_BITS == 32 |
| 1251 |
tcg_gen_op3i(INDEX_op_qemu_st8, arg, addr, mem_index); |
| 1252 |
#else
|
| 1253 |
tcg_gen_op4i(INDEX_op_qemu_st8, arg, addr, TCGV_HIGH(addr), mem_index); |
| 1254 |
#endif
|
| 1255 |
} |
| 1256 |
|
| 1257 |
static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index) |
| 1258 |
{
|
| 1259 |
#if TARGET_LONG_BITS == 32 |
| 1260 |
tcg_gen_op3i(INDEX_op_qemu_st16, arg, addr, mem_index); |
| 1261 |
#else
|
| 1262 |
tcg_gen_op4i(INDEX_op_qemu_st16, arg, addr, TCGV_HIGH(addr), mem_index); |
| 1263 |
#endif
|
| 1264 |
} |
| 1265 |
|
| 1266 |
static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index) |
| 1267 |
{
|
| 1268 |
#if TARGET_LONG_BITS == 32 |
| 1269 |
tcg_gen_op3i(INDEX_op_qemu_st32, arg, addr, mem_index); |
| 1270 |
#else
|
| 1271 |
tcg_gen_op4i(INDEX_op_qemu_st32, arg, addr, TCGV_HIGH(addr), mem_index); |
| 1272 |
#endif
|
| 1273 |
} |
| 1274 |
|
| 1275 |
static inline void tcg_gen_qemu_st64(TCGv arg, TCGv addr, int mem_index) |
| 1276 |
{
|
| 1277 |
#if TARGET_LONG_BITS == 32 |
| 1278 |
tcg_gen_op4i(INDEX_op_qemu_st64, arg, TCGV_HIGH(arg), addr, mem_index); |
| 1279 |
#else
|
| 1280 |
tcg_gen_op5i(INDEX_op_qemu_st64, arg, TCGV_HIGH(arg), |
| 1281 |
addr, TCGV_HIGH(addr), mem_index); |
| 1282 |
#endif
|
| 1283 |
} |
| 1284 |
|
| 1285 |
#define tcg_gen_ld_ptr tcg_gen_ld_i32
|
| 1286 |
#define tcg_gen_discard_ptr tcg_gen_discard_i32
|
| 1287 |
|
| 1288 |
#else /* TCG_TARGET_REG_BITS == 32 */ |
| 1289 |
|
| 1290 |
static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) |
| 1291 |
{
|
| 1292 |
tcg_gen_op3i(INDEX_op_qemu_ld8u, ret, addr, mem_index); |
| 1293 |
} |
| 1294 |
|
| 1295 |
static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index) |
| 1296 |
{
|
| 1297 |
tcg_gen_op3i(INDEX_op_qemu_ld8s, ret, addr, mem_index); |
| 1298 |
} |
| 1299 |
|
| 1300 |
static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index) |
| 1301 |
{
|
| 1302 |
tcg_gen_op3i(INDEX_op_qemu_ld16u, ret, addr, mem_index); |
| 1303 |
} |
| 1304 |
|
| 1305 |
static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index) |
| 1306 |
{
|
| 1307 |
tcg_gen_op3i(INDEX_op_qemu_ld16s, ret, addr, mem_index); |
| 1308 |
} |
| 1309 |
|
| 1310 |
static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index) |
| 1311 |
{
|
| 1312 |
tcg_gen_op3i(INDEX_op_qemu_ld32u, ret, addr, mem_index); |
| 1313 |
} |
| 1314 |
|
| 1315 |
static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index) |
| 1316 |
{
|
| 1317 |
tcg_gen_op3i(INDEX_op_qemu_ld32s, ret, addr, mem_index); |
| 1318 |
} |
| 1319 |
|
| 1320 |
static inline void tcg_gen_qemu_ld64(TCGv ret, TCGv addr, int mem_index) |
| 1321 |
{
|
| 1322 |
tcg_gen_op3i(INDEX_op_qemu_ld64, ret, addr, mem_index); |
| 1323 |
} |
| 1324 |
|
| 1325 |
static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index) |
| 1326 |
{
|
| 1327 |
tcg_gen_op3i(INDEX_op_qemu_st8, arg, addr, mem_index); |
| 1328 |
} |
| 1329 |
|
| 1330 |
static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index) |
| 1331 |
{
|
| 1332 |
tcg_gen_op3i(INDEX_op_qemu_st16, arg, addr, mem_index); |
| 1333 |
} |
| 1334 |
|
| 1335 |
static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index) |
| 1336 |
{
|
| 1337 |
tcg_gen_op3i(INDEX_op_qemu_st32, arg, addr, mem_index); |
| 1338 |
} |
| 1339 |
|
| 1340 |
static inline void tcg_gen_qemu_st64(TCGv arg, TCGv addr, int mem_index) |
| 1341 |
{
|
| 1342 |
tcg_gen_op3i(INDEX_op_qemu_st64, arg, addr, mem_index); |
| 1343 |
} |
| 1344 |
|
| 1345 |
#define tcg_gen_ld_ptr tcg_gen_ld_i64
|
| 1346 |
#define tcg_gen_discard_ptr tcg_gen_discard_i64
|
| 1347 |
|
| 1348 |
#endif /* TCG_TARGET_REG_BITS != 32 */ |
| 1349 |
|
| 1350 |
#if TARGET_LONG_BITS == 64 |
| 1351 |
#define TCG_TYPE_TL TCG_TYPE_I64
|
| 1352 |
#define tcg_gen_movi_tl tcg_gen_movi_i64
|
| 1353 |
#define tcg_gen_mov_tl tcg_gen_mov_i64
|
| 1354 |
#define tcg_gen_ld8u_tl tcg_gen_ld8u_i64
|
| 1355 |
#define tcg_gen_ld8s_tl tcg_gen_ld8s_i64
|
| 1356 |
#define tcg_gen_ld16u_tl tcg_gen_ld16u_i64
|
| 1357 |
#define tcg_gen_ld16s_tl tcg_gen_ld16s_i64
|
| 1358 |
#define tcg_gen_ld32u_tl tcg_gen_ld32u_i64
|
| 1359 |
#define tcg_gen_ld32s_tl tcg_gen_ld32s_i64
|
| 1360 |
#define tcg_gen_ld_tl tcg_gen_ld_i64
|
| 1361 |
#define tcg_gen_st8_tl tcg_gen_st8_i64
|
| 1362 |
#define tcg_gen_st16_tl tcg_gen_st16_i64
|
| 1363 |
#define tcg_gen_st32_tl tcg_gen_st32_i64
|
| 1364 |
#define tcg_gen_st_tl tcg_gen_st_i64
|
| 1365 |
#define tcg_gen_add_tl tcg_gen_add_i64
|
| 1366 |
#define tcg_gen_addi_tl tcg_gen_addi_i64
|
| 1367 |
#define tcg_gen_sub_tl tcg_gen_sub_i64
|
| 1368 |
#define tcg_gen_subi_tl tcg_gen_subi_i64
|
| 1369 |
#define tcg_gen_and_tl tcg_gen_and_i64
|
| 1370 |
#define tcg_gen_andi_tl tcg_gen_andi_i64
|
| 1371 |
#define tcg_gen_or_tl tcg_gen_or_i64
|
| 1372 |
#define tcg_gen_ori_tl tcg_gen_ori_i64
|
| 1373 |
#define tcg_gen_xor_tl tcg_gen_xor_i64
|
| 1374 |
#define tcg_gen_xori_tl tcg_gen_xori_i64
|
| 1375 |
#define tcg_gen_shl_tl tcg_gen_shl_i64
|
| 1376 |
#define tcg_gen_shli_tl tcg_gen_shli_i64
|
| 1377 |
#define tcg_gen_shr_tl tcg_gen_shr_i64
|
| 1378 |
#define tcg_gen_shri_tl tcg_gen_shri_i64
|
| 1379 |
#define tcg_gen_sar_tl tcg_gen_sar_i64
|
| 1380 |
#define tcg_gen_sari_tl tcg_gen_sari_i64
|
| 1381 |
#define tcg_gen_brcond_tl tcg_gen_brcond_i64
|
| 1382 |
#define tcg_gen_discard_tl tcg_gen_discard_i64
|
| 1383 |
#define tcg_gen_trunc_tl_i32 tcg_gen_trunc_i64_i32
|
| 1384 |
#define tcg_gen_trunc_i64_tl tcg_gen_mov_i64
|
| 1385 |
#define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64
|
| 1386 |
#define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64
|
| 1387 |
#define tcg_gen_extu_tl_i64 tcg_gen_mov_i64
|
| 1388 |
#define tcg_gen_ext_tl_i64 tcg_gen_mov_i64
|
| 1389 |
#define tcg_const_tl tcg_const_i64
|
| 1390 |
#else
|
| 1391 |
#define TCG_TYPE_TL TCG_TYPE_I32
|
| 1392 |
#define tcg_gen_movi_tl tcg_gen_movi_i32
|
| 1393 |
#define tcg_gen_mov_tl tcg_gen_mov_i32
|
| 1394 |
#define tcg_gen_ld8u_tl tcg_gen_ld8u_i32
|
| 1395 |
#define tcg_gen_ld8s_tl tcg_gen_ld8s_i32
|
| 1396 |
#define tcg_gen_ld16u_tl tcg_gen_ld16u_i32
|
| 1397 |
#define tcg_gen_ld16s_tl tcg_gen_ld16s_i32
|
| 1398 |
#define tcg_gen_ld32u_tl tcg_gen_ld_i32
|
| 1399 |
#define tcg_gen_ld32s_tl tcg_gen_ld_i32
|
| 1400 |
#define tcg_gen_ld_tl tcg_gen_ld_i32
|
| 1401 |
#define tcg_gen_st8_tl tcg_gen_st8_i32
|
| 1402 |
#define tcg_gen_st16_tl tcg_gen_st16_i32
|
| 1403 |
#define tcg_gen_st32_tl tcg_gen_st_i32
|
| 1404 |
#define tcg_gen_st_tl tcg_gen_st_i32
|
| 1405 |
#define tcg_gen_add_tl tcg_gen_add_i32
|
| 1406 |
#define tcg_gen_addi_tl tcg_gen_addi_i32
|
| 1407 |
#define tcg_gen_sub_tl tcg_gen_sub_i32
|
| 1408 |
#define tcg_gen_subi_tl tcg_gen_subi_i32
|
| 1409 |
#define tcg_gen_and_tl tcg_gen_and_i32
|
| 1410 |
#define tcg_gen_andi_tl tcg_gen_andi_i32
|
| 1411 |
#define tcg_gen_or_tl tcg_gen_or_i32
|
| 1412 |
#define tcg_gen_ori_tl tcg_gen_ori_i32
|
| 1413 |
#define tcg_gen_xor_tl tcg_gen_xor_i32
|
| 1414 |
#define tcg_gen_xori_tl tcg_gen_xori_i32
|
| 1415 |
#define tcg_gen_shl_tl tcg_gen_shl_i32
|
| 1416 |
#define tcg_gen_shli_tl tcg_gen_shli_i32
|
| 1417 |
#define tcg_gen_shr_tl tcg_gen_shr_i32
|
| 1418 |
#define tcg_gen_shri_tl tcg_gen_shri_i32
|
| 1419 |
#define tcg_gen_sar_tl tcg_gen_sar_i32
|
| 1420 |
#define tcg_gen_sari_tl tcg_gen_sari_i32
|
| 1421 |
#define tcg_gen_brcond_tl tcg_gen_brcond_i32
|
| 1422 |
#define tcg_gen_discard_tl tcg_gen_discard_i32
|
| 1423 |
#define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32
|
| 1424 |
#define tcg_gen_trunc_i64_tl tcg_gen_trunc_i64_i32
|
| 1425 |
#define tcg_gen_extu_i32_tl tcg_gen_mov_i32
|
| 1426 |
#define tcg_gen_ext_i32_tl tcg_gen_mov_i32
|
| 1427 |
#define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64
|
| 1428 |
#define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64
|
| 1429 |
#define tcg_const_tl tcg_const_i32
|
| 1430 |
#endif
|
| 1431 |
|
| 1432 |
#if TCG_TARGET_REG_BITS == 32 |
| 1433 |
#define tcg_gen_addi_ptr tcg_gen_addi_i32
|
| 1434 |
#else /* TCG_TARGET_REG_BITS == 32 */ |
| 1435 |
#define tcg_gen_addi_ptr tcg_gen_addi_i64
|
| 1436 |
#endif /* TCG_TARGET_REG_BITS != 32 */ |
| 1437 |
|