Revision 6e0c0ed1 target-arm/translate.c

b/target-arm/translate.c
3071 3071 
                    /* Source and destination the same.  */
3072 3072 
                    gen_mov_F0_vreg(dp, rd);
3073 3073 
                    break;
3074 
                case 4:
3075 
                case 5:
3076 
                case 6:
3077 
                case 7:
3078 
                    /* VCVTB, VCVTT: only present with the halfprec extension,
3079 
                     * UNPREDICTABLE if bit 8 is set (we choose to UNDEF)
3080 
                     */
3081 
                    if (dp || !arm_feature(env, ARM_FEATURE_VFP_FP16)) {
3082 
                        return 1;
3083 
                    }
3084 
                    /* Otherwise fall through */
3074 3085 
                default:
3075 3086 
                    /* One source operand.  */
3076 3087 
                    gen_mov_F0_vreg(dp, rm);
......
3167 3178 
                        gen_vfp_sqrt(dp);
3168 3179 
                        break;
3169 3180 
                    case 4: /* vcvtb.f32.f16 */
3170 
                        if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3171 
                          return 1;
3172 3181 
                        tmp = gen_vfp_mrs();
3173 3182 
                        tcg_gen_ext16u_i32(tmp, tmp);
3174 3183 
                        gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp, cpu_env);
3175 3184 
                        tcg_temp_free_i32(tmp);
3176 3185 
                        break;
3177 3186 
                    case 5: /* vcvtt.f32.f16 */
3178 
                        if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3179 
                          return 1;
3180 3187 
                        tmp = gen_vfp_mrs();
3181 3188 
                        tcg_gen_shri_i32(tmp, tmp, 16);
3182 3189 
                        gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp, cpu_env);
3183 3190 
                        tcg_temp_free_i32(tmp);
3184 3191 
                        break;
3185 3192 
                    case 6: /* vcvtb.f16.f32 */
3186 
                        if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3187 
                          return 1;
3188 3193 
                        tmp = tcg_temp_new_i32();
3189 3194 
                        gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
3190 3195 
                        gen_mov_F0_vreg(0, rd);
......
3195 3200 
                        gen_vfp_msr(tmp);
3196 3201 
                        break;
3197 3202 
                    case 7: /* vcvtt.f16.f32 */
3198 
                        if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3199 
                          return 1;
3200 3203 
                        tmp = tcg_temp_new_i32();
3201 3204 
                        gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
3202 3205 
                        tcg_gen_shli_i32(tmp, tmp, 16);

Also available in: Unified diff