Revision 6ea83fed target-mips/mips-defs.h
b/target-mips/mips-defs.h | ||
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/* Uses MIPS R4Kc TLB model */ |
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#define MIPS_USES_R4K_TLB |
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#define MIPS_TLB_NB 16 |
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/* basic FPU register support */ |
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#define MIPS_USES_FPU 1 |
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/* Define a implementation number of 1. |
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* Define a major version 1, minor version 0. |
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*/ |
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#define MIPS_FCR0 ((0 << 16) | (1 << 8) | (1 << 4) | 0) |
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/* Have config1, runs in big-endian mode, uses TLB */ |
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#define MIPS_CONFIG0 \ |
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((1 << CP0C0_M) | (0x000 << CP0C0_K23) | (0x000 << CP0C0_KU) | \ |
... | ... | |
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/* 16 TLBs, 64 sets Icache, 16 bytes Icache line, 2-way Icache, |
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* 64 sets Dcache, 16 bytes Dcache line, 2-way Dcache, |
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* no performance counters, watch registers present, no code compression, |
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* EJTAG present, no FPU
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* EJTAG present, FPU enable bit depending on MIPS_USES_FPU
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*/ |
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#define MIPS_CONFIG1 \ |
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((15 << CP0C1_MMU) | \ |
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(0x000 << CP0C1_IS) | (0x3 << CP0C1_IL) | (0x01 << CP0C1_IA) | \ |
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(0x000 << CP0C1_DS) | (0x3 << CP0C1_DL) | (0x01 << CP0C1_DA) | \ |
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(0 << CP0C1_PC) | (1 << CP0C1_WR) | (0 << CP0C1_CA) | \ |
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(1 << CP0C1_EP) | (0 << CP0C1_FP))
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(1 << CP0C1_EP) | (MIPS_USES_FPU << CP0C1_FP))
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#elif defined (MIPS_CPU == MIPS_R4Kp) |
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/* 32 bits target */ |
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#define TARGET_LONG_BITS 32 |
... | ... | |
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#error "MIPS CPU not defined" |
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/* Remainder for other flags */ |
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//#define TARGET_MIPS64 |
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//define MIPS_USES_FPU |
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//#define MIPS_USES_FPU
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#endif |
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#endif /* !defined (__QEMU_MIPS_DEFS_H__) */ |
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