Revision 6ebbf390 exec-all.h
| b/exec-all.h | ||
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| 117 | 117 |
void tlb_flush(CPUState *env, int flush_global); |
| 118 | 118 |
int tlb_set_page_exec(CPUState *env, target_ulong vaddr, |
| 119 | 119 |
target_phys_addr_t paddr, int prot, |
| 120 |
int is_user, int is_softmmu);
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| 120 |
int mmu_idx, int is_softmmu);
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| 121 | 121 |
static inline int tlb_set_page(CPUState *env, target_ulong vaddr, |
| 122 | 122 |
target_phys_addr_t paddr, int prot, |
| 123 |
int is_user, int is_softmmu)
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| 123 |
int mmu_idx, int is_softmmu)
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| 124 | 124 |
{
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| 125 | 125 |
if (prot & PAGE_READ) |
| 126 | 126 |
prot |= PAGE_EXEC; |
| 127 |
return tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);
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| 127 |
return tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
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| 128 | 128 |
} |
| 129 | 129 |
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| 130 | 130 |
#define CODE_GEN_MAX_SIZE 65536 |
| ... | ... | |
| 562 | 562 |
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| 563 | 563 |
#if !defined(CONFIG_USER_ONLY) |
| 564 | 564 |
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| 565 |
void tlb_fill(target_ulong addr, int is_write, int is_user,
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void tlb_fill(target_ulong addr, int is_write, int mmu_idx,
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| 566 | 566 |
void *retaddr); |
| 567 | 567 |
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#define ACCESS_TYPE 3
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#define ACCESS_TYPE (NB_MMU_MODES + 1)
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| 569 | 569 |
#define MEMSUFFIX _code |
| 570 | 570 |
#define env cpu_single_env |
| 571 | 571 |
|
| ... | ... | |
| 598 | 598 |
is the offset relative to phys_ram_base */ |
| 599 | 599 |
static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr) |
| 600 | 600 |
{
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int is_user, index, pd;
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int mmu_idx, index, pd;
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| 602 | 602 |
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| 603 | 603 |
index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
| 604 |
#if defined(TARGET_I386) |
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is_user = ((env->hflags & HF_CPL_MASK) == 3); |
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| 606 |
#elif defined (TARGET_PPC) |
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is_user = msr_pr; |
|
| 608 |
#elif defined (TARGET_MIPS) |
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is_user = ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM); |
|
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#elif defined (TARGET_SPARC) |
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is_user = (env->psrs == 0); |
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#elif defined (TARGET_ARM) |
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is_user = ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR); |
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#elif defined (TARGET_SH4) |
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is_user = ((env->sr & SR_MD) == 0); |
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#elif defined (TARGET_ALPHA) |
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is_user = ((env->ps >> 3) & 3); |
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#elif defined (TARGET_M68K) |
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is_user = ((env->sr & SR_S) == 0); |
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#elif defined (TARGET_CRIS) |
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is_user = (0); |
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#else |
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#error unimplemented CPU |
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#endif |
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if (__builtin_expect(env->tlb_table[is_user][index].addr_code != |
|
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mmu_idx = cpu_mmu_index(env); |
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if (__builtin_expect(env->tlb_table[mmu_idx][index].addr_code != |
|
| 626 | 606 |
(addr & TARGET_PAGE_MASK), 0)) {
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| 627 | 607 |
ldub_code(addr); |
| 628 | 608 |
} |
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pd = env->tlb_table[is_user][index].addr_code & ~TARGET_PAGE_MASK;
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pd = env->tlb_table[mmu_idx][index].addr_code & ~TARGET_PAGE_MASK;
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| 630 | 610 |
if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
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| 631 | 611 |
#ifdef TARGET_SPARC |
| 632 | 612 |
do_unassigned_access(addr, 0, 1, 0); |
| ... | ... | |
| 634 | 614 |
cpu_abort(env, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr); |
| 635 | 615 |
#endif |
| 636 | 616 |
} |
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return addr + env->tlb_table[is_user][index].addend - (unsigned long)phys_ram_base;
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return addr + env->tlb_table[mmu_idx][index].addend - (unsigned long)phys_ram_base;
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| 638 | 618 |
} |
| 639 | 619 |
#endif |
| 640 | 620 |
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