Revision 6ebbf390 softmmu_header.h
| b/softmmu_header.h | ||
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| 39 | 39 |
#error unsupported data size |
| 40 | 40 |
#endif |
| 41 | 41 |
|
| 42 |
#if ACCESS_TYPE == 0
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|
| 42 |
#if ACCESS_TYPE < (NB_MMU_MODES)
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| 43 | 43 |
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#define CPU_MEM_INDEX 0
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#define CPU_MMU_INDEX ACCESS_TYPE
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| 45 | 45 |
#define MMUSUFFIX _mmu |
| 46 | 46 |
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| 47 |
#elif ACCESS_TYPE == 1
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| 47 |
#elif ACCESS_TYPE == (NB_MMU_MODES)
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| 48 | 48 |
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#define CPU_MEM_INDEX 1
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#define CPU_MMU_INDEX (cpu_mmu_index(env))
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| 50 | 50 |
#define MMUSUFFIX _mmu |
| 51 | 51 |
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#elif ACCESS_TYPE == 2 |
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#ifdef TARGET_I386 |
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#define CPU_MEM_INDEX ((env->hflags & HF_CPL_MASK) == 3) |
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#elif defined (TARGET_PPC) |
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#define CPU_MEM_INDEX (msr_pr) |
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#elif defined (TARGET_MIPS) |
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#define CPU_MEM_INDEX ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM) |
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#elif defined (TARGET_SPARC) |
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#define CPU_MEM_INDEX ((env->psrs) == 0) |
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#elif defined (TARGET_ARM) |
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#define CPU_MEM_INDEX ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR) |
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#elif defined (TARGET_SH4) |
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#define CPU_MEM_INDEX ((env->sr & SR_MD) == 0) |
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#elif defined (TARGET_ALPHA) |
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#define CPU_MEM_INDEX ((env->ps >> 3) & 3) |
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#elif defined (TARGET_M68K) |
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#define CPU_MEM_INDEX ((env->sr & SR_S) == 0) |
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#elif defined (TARGET_CRIS) |
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/* CRIS FIXME: I guess we want to validate supervisor mode acceses here. */ |
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#define CPU_MEM_INDEX (0) |
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#else |
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#error unsupported CPU |
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#endif |
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#define MMUSUFFIX _mmu |
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#elif ACCESS_TYPE == (NB_MMU_MODES + 1) |
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| 77 | 53 |
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#elif ACCESS_TYPE == 3 |
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#ifdef TARGET_I386 |
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#define CPU_MEM_INDEX ((env->hflags & HF_CPL_MASK) == 3) |
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#elif defined (TARGET_PPC) |
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#define CPU_MEM_INDEX (msr_pr) |
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#elif defined (TARGET_MIPS) |
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#define CPU_MEM_INDEX ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM) |
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#elif defined (TARGET_SPARC) |
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#define CPU_MEM_INDEX ((env->psrs) == 0) |
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#elif defined (TARGET_ARM) |
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#define CPU_MEM_INDEX ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR) |
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#elif defined (TARGET_SH4) |
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#define CPU_MEM_INDEX ((env->sr & SR_MD) == 0) |
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#elif defined (TARGET_ALPHA) |
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#define CPU_MEM_INDEX ((env->ps >> 3) & 3) |
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#elif defined (TARGET_M68K) |
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#define CPU_MEM_INDEX ((env->sr & SR_S) == 0) |
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#elif defined (TARGET_CRIS) |
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/* CRIS FIXME: I guess we want to validate supervisor mode acceses here. */ |
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#define CPU_MEM_INDEX (0) |
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#else |
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#error unsupported CPU |
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#endif |
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#define CPU_MMU_INDEX (cpu_mmu_index(env)) |
|
| 102 | 55 |
#define MMUSUFFIX _cmmu |
| 103 | 56 |
|
| 104 | 57 |
#else |
| ... | ... | |
| 111 | 64 |
#define RES_TYPE int |
| 112 | 65 |
#endif |
| 113 | 66 |
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#if ACCESS_TYPE == 3
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#if ACCESS_TYPE == (NB_MMU_MODES + 1)
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| 115 | 68 |
#define ADDR_READ addr_code |
| 116 | 69 |
#else |
| 117 | 70 |
#define ADDR_READ addr_read |
| 118 | 71 |
#endif |
| 119 | 72 |
|
| 120 | 73 |
DATA_TYPE REGPARM(1) glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr, |
| 121 |
int is_user);
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void REGPARM(2) glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr, DATA_TYPE v, int is_user);
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int mmu_idx);
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void REGPARM(2) glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr, DATA_TYPE v, int mmu_idx);
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#if (DATA_SIZE <= 4) && (TARGET_LONG_BITS == 32) && defined(__i386__) && \ |
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(ACCESS_TYPE <= 1) && defined(ASM_SOFTMMU)
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(ACCESS_TYPE < NB_MMU_MODES) && defined(ASM_SOFTMMU)
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#define CPU_TLB_ENTRY_BITS 4 |
| 128 | 81 |
|
| ... | ... | |
| 161 | 114 |
"i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS), |
| 162 | 115 |
"i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS), |
| 163 | 116 |
"i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)), |
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"m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MEM_INDEX][0].addr_read)),
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"i" (CPU_MEM_INDEX),
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"m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MMU_INDEX][0].addr_read)),
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"i" (CPU_MMU_INDEX),
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"m" (*(uint8_t *)&glue(glue(__ld, SUFFIX), MMUSUFFIX)) |
| 167 | 120 |
: "%eax", "%ecx", "%edx", "memory", "cc"); |
| 168 | 121 |
return res; |
| ... | ... | |
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"i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS), |
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"i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS), |
| 210 | 163 |
"i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)), |
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"m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MEM_INDEX][0].addr_read)),
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"i" (CPU_MEM_INDEX),
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"m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MMU_INDEX][0].addr_read)),
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"i" (CPU_MMU_INDEX),
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"m" (*(uint8_t *)&glue(glue(__ld, SUFFIX), MMUSUFFIX)) |
| 214 | 167 |
: "%eax", "%ecx", "%edx", "memory", "cc"); |
| 215 | 168 |
return res; |
| ... | ... | |
| 260 | 213 |
"i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS), |
| 261 | 214 |
"i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS), |
| 262 | 215 |
"i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)), |
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"m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MEM_INDEX][0].addr_write)),
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"i" (CPU_MEM_INDEX),
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"m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MMU_INDEX][0].addr_write)),
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"i" (CPU_MMU_INDEX),
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| 265 | 218 |
"m" (*(uint8_t *)&glue(glue(__st, SUFFIX), MMUSUFFIX)) |
| 266 | 219 |
: "%eax", "%ecx", "%edx", "memory", "cc"); |
| 267 | 220 |
} |
| ... | ... | |
| 276 | 229 |
RES_TYPE res; |
| 277 | 230 |
target_ulong addr; |
| 278 | 231 |
unsigned long physaddr; |
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int is_user;
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int mmu_idx;
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| 280 | 233 |
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addr = ptr; |
| 282 | 235 |
index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
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is_user = CPU_MEM_INDEX;
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if (__builtin_expect(env->tlb_table[is_user][index].ADDR_READ !=
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mmu_idx = CPU_MMU_INDEX;
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if (__builtin_expect(env->tlb_table[mmu_idx][index].ADDR_READ !=
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| 285 | 238 |
(addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
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res = glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, is_user);
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res = glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, mmu_idx);
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| 287 | 240 |
} else {
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physaddr = addr + env->tlb_table[is_user][index].addend;
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physaddr = addr + env->tlb_table[mmu_idx][index].addend;
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res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)physaddr); |
| 290 | 243 |
} |
| 291 | 244 |
return res; |
| ... | ... | |
| 297 | 250 |
int res, index; |
| 298 | 251 |
target_ulong addr; |
| 299 | 252 |
unsigned long physaddr; |
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int is_user;
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int mmu_idx;
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| 301 | 254 |
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addr = ptr; |
| 303 | 256 |
index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
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is_user = CPU_MEM_INDEX;
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if (__builtin_expect(env->tlb_table[is_user][index].ADDR_READ !=
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mmu_idx = CPU_MMU_INDEX;
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if (__builtin_expect(env->tlb_table[mmu_idx][index].ADDR_READ !=
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(addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
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res = (DATA_STYPE)glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, is_user);
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res = (DATA_STYPE)glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, mmu_idx);
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} else {
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physaddr = addr + env->tlb_table[is_user][index].addend;
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physaddr = addr + env->tlb_table[mmu_idx][index].addend;
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res = glue(glue(lds, SUFFIX), _raw)((uint8_t *)physaddr); |
| 311 | 264 |
} |
| 312 | 265 |
return res; |
| 313 | 266 |
} |
| 314 | 267 |
#endif |
| 315 | 268 |
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#if ACCESS_TYPE != 3
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#if ACCESS_TYPE != (NB_MMU_MODES + 1)
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| 317 | 270 |
|
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/* generic store macro */ |
| 319 | 272 |
|
| ... | ... | |
| 322 | 275 |
int index; |
| 323 | 276 |
target_ulong addr; |
| 324 | 277 |
unsigned long physaddr; |
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int is_user;
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int mmu_idx;
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| 326 | 279 |
|
| 327 | 280 |
addr = ptr; |
| 328 | 281 |
index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
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is_user = CPU_MEM_INDEX;
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if (__builtin_expect(env->tlb_table[is_user][index].addr_write !=
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mmu_idx = CPU_MMU_INDEX;
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if (__builtin_expect(env->tlb_table[mmu_idx][index].addr_write !=
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| 331 | 284 |
(addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
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glue(glue(__st, SUFFIX), MMUSUFFIX)(addr, v, is_user);
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glue(glue(__st, SUFFIX), MMUSUFFIX)(addr, v, mmu_idx);
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| 333 | 286 |
} else {
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physaddr = addr + env->tlb_table[is_user][index].addend;
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physaddr = addr + env->tlb_table[mmu_idx][index].addend;
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| 335 | 288 |
glue(glue(st, SUFFIX), _raw)((uint8_t *)physaddr, v); |
| 336 | 289 |
} |
| 337 | 290 |
} |
| 338 | 291 |
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#endif /* ACCESS_TYPE != 3 */
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#endif /* ACCESS_TYPE != (NB_MMU_MODES + 1) */
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| 340 | 293 |
|
| 341 | 294 |
#endif /* !asm */ |
| 342 | 295 |
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#if ACCESS_TYPE != 3
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#if ACCESS_TYPE != (NB_MMU_MODES + 1)
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| 344 | 297 |
|
| 345 | 298 |
#if DATA_SIZE == 8 |
| 346 | 299 |
static inline float64 glue(ldfq, MEMSUFFIX)(target_ulong ptr) |
| ... | ... | |
| 386 | 339 |
} |
| 387 | 340 |
#endif /* DATA_SIZE == 4 */ |
| 388 | 341 |
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#endif /* ACCESS_TYPE != 3 */
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#endif /* ACCESS_TYPE != (NB_MMU_MODES + 1) */
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| 390 | 343 |
|
| 391 | 344 |
#undef RES_TYPE |
| 392 | 345 |
#undef DATA_TYPE |
| ... | ... | |
| 394 | 347 |
#undef SUFFIX |
| 395 | 348 |
#undef USUFFIX |
| 396 | 349 |
#undef DATA_SIZE |
| 397 |
#undef CPU_MEM_INDEX
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#undef CPU_MMU_INDEX
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| 398 | 351 |
#undef MMUSUFFIX |
| 399 | 352 |
#undef ADDR_READ |
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