root / hw / unin_pci.c @ 6ebf5905
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/*
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* QEMU Uninorth PCI host (for all Mac99 and newer machines)
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*
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* Copyright (c) 2006 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "ppc_mac.h" |
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#include "pci.h" |
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#include "pci_host.h" |
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/* debug UniNorth */
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//#define DEBUG_UNIN
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#ifdef DEBUG_UNIN
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#define UNIN_DPRINTF(fmt, ...) \
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do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0) |
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#else
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#define UNIN_DPRINTF(fmt, ...)
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#endif
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static const int unin_irq_line[] = { 0x1b, 0x1c, 0x1d, 0x1e }; |
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typedef struct UNINState { |
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SysBusDevice busdev; |
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PCIHostState host_state; |
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ReadWriteHandler data_handler; |
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} UNINState; |
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static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num) |
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{ |
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int retval;
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int devfn = pci_dev->devfn & 0x00FFFFFF; |
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retval = (((devfn >> 11) & 0x1F) + irq_num) & 3; |
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return retval;
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} |
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static void pci_unin_set_irq(void *opaque, int irq_num, int level) |
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{ |
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qemu_irq *pic = opaque; |
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UNIN_DPRINTF("%s: setting INT %d = %d\n", __func__,
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unin_irq_line[irq_num], level); |
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qemu_set_irq(pic[unin_irq_line[irq_num]], level); |
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} |
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static void pci_unin_save(QEMUFile* f, void *opaque) |
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{ |
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PCIDevice *d = opaque; |
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pci_device_save(d, f); |
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} |
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static int pci_unin_load(QEMUFile* f, void *opaque, int version_id) |
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{ |
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PCIDevice *d = opaque; |
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if (version_id != 1) |
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return -EINVAL;
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return pci_device_load(d, f);
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} |
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static void pci_unin_reset(void *opaque) |
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{ |
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} |
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static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr)
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{ |
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uint32_t retval; |
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if (reg & (1u << 31)) { |
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/* XXX OpenBIOS compatibility hack */
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retval = reg | (addr & 3);
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} else if (reg & 1) { |
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/* CFA1 style */
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retval = (reg & ~7u) | (addr & 7); |
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} else {
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uint32_t slot, func; |
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/* Grab CFA0 style values */
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slot = ffs(reg & 0xfffff800) - 1; |
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func = (reg >> 8) & 7; |
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/* ... and then convert them to x86 format */
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/* config pointer */
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retval = (reg & (0xff - 7)) | (addr & 7); |
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/* slot */
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retval |= slot << 11;
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/* fn */
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retval |= func << 8;
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} |
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UNIN_DPRINTF("Converted config space accessor %08x/%08x -> %08x\n",
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reg, addr, retval); |
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return retval;
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} |
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static void unin_data_write(ReadWriteHandler *handler, |
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pcibus_t addr, uint32_t val, int len)
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{ |
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UNINState *s = container_of(handler, UNINState, data_handler); |
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val = qemu_bswap_len(val, len); |
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UNIN_DPRINTF("write addr %" FMT_PCIBUS " len %d val %x\n", addr, len, val); |
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pci_data_write(s->host_state.bus, |
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unin_get_config_reg(s->host_state.config_reg, addr), |
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val, len); |
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} |
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static uint32_t unin_data_read(ReadWriteHandler *handler,
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pcibus_t addr, int len)
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{ |
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UNINState *s = container_of(handler, UNINState, data_handler); |
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uint32_t val; |
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val = pci_data_read(s->host_state.bus, |
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unin_get_config_reg(s->host_state.config_reg, addr), |
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len); |
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UNIN_DPRINTF("read addr %" FMT_PCIBUS " len %d val %x\n", addr, len, val); |
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val = qemu_bswap_len(val, len); |
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return val;
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} |
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static int pci_unin_main_init_device(SysBusDevice *dev) |
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{ |
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UNINState *s; |
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int pci_mem_config, pci_mem_data;
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/* Use values found on a real PowerMac */
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/* Uninorth main bus */
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s = FROM_SYSBUS(UNINState, dev); |
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pci_mem_config = pci_host_conf_register_mmio(&s->host_state, |
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DEVICE_LITTLE_ENDIAN); |
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s->data_handler.read = unin_data_read; |
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s->data_handler.write = unin_data_write; |
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pci_mem_data = cpu_register_io_memory_simple(&s->data_handler, |
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DEVICE_NATIVE_ENDIAN); |
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sysbus_init_mmio(dev, 0x1000, pci_mem_config);
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sysbus_init_mmio(dev, 0x1000, pci_mem_data);
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register_savevm(&dev->qdev, "uninorth", 0, 1, |
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pci_unin_save, pci_unin_load, &s->host_state); |
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qemu_register_reset(pci_unin_reset, &s->host_state); |
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return 0; |
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} |
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static int pci_u3_agp_init_device(SysBusDevice *dev) |
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{ |
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UNINState *s; |
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int pci_mem_config, pci_mem_data;
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/* Uninorth U3 AGP bus */
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s = FROM_SYSBUS(UNINState, dev); |
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pci_mem_config = pci_host_conf_register_mmio(&s->host_state, |
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DEVICE_LITTLE_ENDIAN); |
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s->data_handler.read = unin_data_read; |
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s->data_handler.write = unin_data_write; |
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pci_mem_data = cpu_register_io_memory_simple(&s->data_handler, |
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DEVICE_NATIVE_ENDIAN); |
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sysbus_init_mmio(dev, 0x1000, pci_mem_config);
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sysbus_init_mmio(dev, 0x1000, pci_mem_data);
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register_savevm(&dev->qdev, "uninorth", 0, 1, |
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pci_unin_save, pci_unin_load, &s->host_state); |
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qemu_register_reset(pci_unin_reset, &s->host_state); |
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return 0; |
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} |
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static int pci_unin_agp_init_device(SysBusDevice *dev) |
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{ |
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UNINState *s; |
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int pci_mem_config, pci_mem_data;
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/* Uninorth AGP bus */
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s = FROM_SYSBUS(UNINState, dev); |
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pci_mem_config = pci_host_conf_register_mmio(&s->host_state, |
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DEVICE_LITTLE_ENDIAN); |
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pci_mem_data = pci_host_data_register_mmio(&s->host_state, |
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DEVICE_LITTLE_ENDIAN); |
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sysbus_init_mmio(dev, 0x1000, pci_mem_config);
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sysbus_init_mmio(dev, 0x1000, pci_mem_data);
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return 0; |
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} |
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static int pci_unin_internal_init_device(SysBusDevice *dev) |
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{ |
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UNINState *s; |
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int pci_mem_config, pci_mem_data;
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/* Uninorth internal bus */
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s = FROM_SYSBUS(UNINState, dev); |
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pci_mem_config = pci_host_conf_register_mmio(&s->host_state, |
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DEVICE_LITTLE_ENDIAN); |
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pci_mem_data = pci_host_data_register_mmio(&s->host_state, |
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DEVICE_LITTLE_ENDIAN); |
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sysbus_init_mmio(dev, 0x1000, pci_mem_config);
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sysbus_init_mmio(dev, 0x1000, pci_mem_data);
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return 0; |
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} |
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PCIBus *pci_pmac_init(qemu_irq *pic) |
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{ |
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DeviceState *dev; |
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SysBusDevice *s; |
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UNINState *d; |
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/* Use values found on a real PowerMac */
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/* Uninorth main bus */
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dev = qdev_create(NULL, "uni-north"); |
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qdev_init_nofail(dev); |
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s = sysbus_from_qdev(dev); |
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d = FROM_SYSBUS(UNINState, s); |
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d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
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pci_unin_set_irq, pci_unin_map_irq, |
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pic, PCI_DEVFN(11, 0), 4); |
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#if 0
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pci_create_simple(d->host_state.bus, PCI_DEVFN(11, 0), "uni-north");
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#endif
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sysbus_mmio_map(s, 0, 0xf2800000); |
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sysbus_mmio_map(s, 1, 0xf2c00000); |
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/* DEC 21154 bridge */
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#if 0
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/* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */
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pci_create_simple(d->host_state.bus, PCI_DEVFN(12, 0), "dec-21154");
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#endif
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/* Uninorth AGP bus */
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pci_create_simple(d->host_state.bus, PCI_DEVFN(11, 0), "uni-north-agp"); |
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dev = qdev_create(NULL, "uni-north-agp"); |
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qdev_init_nofail(dev); |
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s = sysbus_from_qdev(dev); |
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sysbus_mmio_map(s, 0, 0xf0800000); |
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sysbus_mmio_map(s, 1, 0xf0c00000); |
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/* Uninorth internal bus */
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#if 0
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/* XXX: not needed for now */
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pci_create_simple(d->host_state.bus, PCI_DEVFN(14, 0), "uni-north-pci");
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dev = qdev_create(NULL, "uni-north-pci");
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qdev_init_nofail(dev);
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s = sysbus_from_qdev(dev);
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sysbus_mmio_map(s, 0, 0xf4800000);
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sysbus_mmio_map(s, 1, 0xf4c00000);
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#endif
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return d->host_state.bus;
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} |
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PCIBus *pci_pmac_u3_init(qemu_irq *pic) |
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{ |
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DeviceState *dev; |
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SysBusDevice *s; |
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UNINState *d; |
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/* Uninorth AGP bus */
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dev = qdev_create(NULL, "u3-agp"); |
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qdev_init_nofail(dev); |
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s = sysbus_from_qdev(dev); |
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d = FROM_SYSBUS(UNINState, s); |
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d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
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pci_unin_set_irq, pci_unin_map_irq, |
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pic, PCI_DEVFN(11, 0), 4); |
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sysbus_mmio_map(s, 0, 0xf0800000); |
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sysbus_mmio_map(s, 1, 0xf0c00000); |
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pci_create_simple(d->host_state.bus, 11 << 3, "u3-agp"); |
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return d->host_state.bus;
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} |
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static int unin_main_pci_host_init(PCIDevice *d) |
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{ |
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pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE); |
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pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_PCI); |
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d->config[0x08] = 0x00; // revision |
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pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST); |
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d->config[0x0C] = 0x08; // cache_line_size |
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d->config[0x0D] = 0x10; // latency_timer |
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d->config[0x34] = 0x00; // capabilities_pointer |
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return 0; |
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} |
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static int unin_agp_pci_host_init(PCIDevice *d) |
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{ |
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pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE); |
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pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_AGP); |
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d->config[0x08] = 0x00; // revision |
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pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST); |
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d->config[0x0C] = 0x08; // cache_line_size |
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d->config[0x0D] = 0x10; // latency_timer |
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// d->config[0x34] = 0x80; // capabilities_pointer
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return 0; |
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} |
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static int u3_agp_pci_host_init(PCIDevice *d) |
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{ |
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pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE); |
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pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_U3_AGP); |
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/* revision */
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d->config[0x08] = 0x00; |
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pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST); |
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/* cache line size */
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d->config[0x0C] = 0x08; |
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/* latency timer */
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d->config[0x0D] = 0x10; |
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return 0; |
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} |
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static int unin_internal_pci_host_init(PCIDevice *d) |
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{ |
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pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE); |
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pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_I_PCI); |
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d->config[0x08] = 0x00; // revision |
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pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST); |
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d->config[0x0C] = 0x08; // cache_line_size |
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d->config[0x0D] = 0x10; // latency_timer |
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d->config[0x34] = 0x00; // capabilities_pointer |
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return 0; |
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} |
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static PCIDeviceInfo unin_main_pci_host_info = {
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.qdev.name = "uni-north",
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.qdev.size = sizeof(PCIDevice),
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.init = unin_main_pci_host_init, |
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}; |
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static PCIDeviceInfo u3_agp_pci_host_info = {
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.qdev.name = "u3-agp",
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.qdev.size = sizeof(PCIDevice),
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.init = u3_agp_pci_host_init, |
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}; |
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static PCIDeviceInfo unin_agp_pci_host_info = {
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.qdev.name = "uni-north-agp",
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.qdev.size = sizeof(PCIDevice),
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.init = unin_agp_pci_host_init, |
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}; |
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static PCIDeviceInfo unin_internal_pci_host_info = {
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.qdev.name = "uni-north-pci",
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.qdev.size = sizeof(PCIDevice),
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.init = unin_internal_pci_host_init, |
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}; |
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static void unin_register_devices(void) |
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{ |
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sysbus_register_dev("uni-north", sizeof(UNINState), |
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pci_unin_main_init_device); |
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pci_qdev_register(&unin_main_pci_host_info); |
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sysbus_register_dev("u3-agp", sizeof(UNINState), |
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pci_u3_agp_init_device); |
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pci_qdev_register(&u3_agp_pci_host_info); |
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sysbus_register_dev("uni-north-agp", sizeof(UNINState), |
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pci_unin_agp_init_device); |
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pci_qdev_register(&unin_agp_pci_host_info); |
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sysbus_register_dev("uni-north-pci", sizeof(UNINState), |
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pci_unin_internal_init_device); |
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pci_qdev_register(&unin_internal_pci_host_info); |
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} |
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device_init(unin_register_devices) |