Revision 6ed221b6
| b/hw/arm_boot.c | ||
|---|---|---|
| 175 | 175 |
} |
| 176 | 176 |
} |
| 177 | 177 |
|
| 178 |
static void main_cpu_reset(void *opaque)
|
|
| 178 |
static void do_cpu_reset(void *opaque)
|
|
| 179 | 179 |
{
|
| 180 | 180 |
CPUState *env = opaque; |
| 181 | 181 |
struct arm_boot_info *info = env->boot_info; |
| ... | ... | |
| 187 | 187 |
env->regs[15] = info->entry & 0xfffffffe; |
| 188 | 188 |
env->thumb = info->entry & 1; |
| 189 | 189 |
} else {
|
| 190 |
env->regs[15] = info->loader_start; |
|
| 191 |
if (old_param) {
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|
| 192 |
set_kernel_args_old(info, info->initrd_size, |
|
| 190 |
if (env == first_cpu) {
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|
| 191 |
env->regs[15] = info->loader_start; |
|
| 192 |
if (old_param) {
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|
| 193 |
set_kernel_args_old(info, info->initrd_size, |
|
| 194 |
info->loader_start); |
|
| 195 |
} else {
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| 196 |
set_kernel_args(info, info->initrd_size, |
|
| 193 | 197 |
info->loader_start); |
| 198 |
} |
|
| 194 | 199 |
} else {
|
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set_kernel_args(info, info->initrd_size, info->loader_start);
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| 200 |
env->regs[15] = info->smp_loader_start;
|
|
| 196 | 201 |
} |
| 197 | 202 |
} |
| 198 | 203 |
} |
| 199 |
/* TODO: Reset secondary CPUs. */ |
|
| 200 | 204 |
} |
| 201 | 205 |
|
| 202 | 206 |
void arm_load_kernel(CPUState *env, struct arm_boot_info *info) |
| ... | ... | |
| 217 | 221 |
|
| 218 | 222 |
if (info->nb_cpus == 0) |
| 219 | 223 |
info->nb_cpus = 1; |
| 220 |
env->boot_info = info; |
|
| 221 | 224 |
|
| 222 | 225 |
#ifdef TARGET_WORDS_BIGENDIAN |
| 223 | 226 |
big_endian = 1; |
| ... | ... | |
| 279 | 282 |
info->initrd_size = initrd_size; |
| 280 | 283 |
} |
| 281 | 284 |
info->is_linux = is_linux; |
| 282 |
qemu_register_reset(main_cpu_reset, env); |
|
| 285 |
|
|
| 286 |
for (; env; env = env->next_cpu) {
|
|
| 287 |
env->boot_info = info; |
|
| 288 |
qemu_register_reset(do_cpu_reset, env); |
|
| 289 |
} |
|
| 283 | 290 |
} |
| b/hw/realview.c | ||
|---|---|---|
| 104 | 104 |
.smp_loader_start = SMP_BOOT_ADDR, |
| 105 | 105 |
}; |
| 106 | 106 |
|
| 107 |
static void secondary_cpu_reset(void *opaque) |
|
| 108 |
{
|
|
| 109 |
CPUState *env = opaque; |
|
| 110 |
|
|
| 111 |
cpu_reset(env); |
|
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/* Set entry point for secondary CPUs. This assumes we're using |
|
| 113 |
the init code from arm_boot.c. Real hardware resets all CPUs |
|
| 114 |
the same. */ |
|
| 115 |
env->regs[15] = SMP_BOOT_ADDR; |
|
| 116 |
} |
|
| 117 |
|
|
| 118 | 107 |
/* The following two lists must be consistent. */ |
| 119 | 108 |
enum realview_board_type {
|
| 120 | 109 |
BOARD_EB, |
| ... | ... | |
| 177 | 166 |
} |
| 178 | 167 |
irqp = arm_pic_init_cpu(env); |
| 179 | 168 |
cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ]; |
| 180 |
if (n > 0) {
|
|
| 181 |
qemu_register_reset(secondary_cpu_reset, env); |
|
| 182 |
} |
|
| 183 | 169 |
} |
| 184 | 170 |
if (arm_feature(env, ARM_FEATURE_V7)) {
|
| 185 | 171 |
if (is_mpcore) {
|
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