Archipelago » qemu

        }

        conf.period.ticks = 1;

    } else {

    }

    e = qemu_add_vm_change_state_handler (audio_vm_change_state_handler, s);

    now = qemu_get_clock (vm_clock);

    ticks = now - no->old_ticks;

    bytes = audio_MIN (bytes, INT_MAX);

    samples = bytes >> hw->info.shift;

    if (dead) {

        int64_t now = qemu_get_clock (vm_clock);

        int64_t ticks = now - no->old_ticks;

        no->old_ticks = now;

        bytes = audio_MIN (bytes, INT_MAX);

    struct st_sample *src;

    int64_t now = qemu_get_clock (vm_clock);

    int64_t ticks = now - wav->old_ticks;

    if (bytes > INT_MAX) {

        samples = INT_MAX >> hw->info.shift;

static uint32_t get_pmtmr(PIIX4PMState *s)

{

    uint32_t d;

    return d & 0xffffff;

}

    int64_t d;

    int pmsts;

    pmsts = s->pmsts;

    if (d >= s->tmr_overflow_time)

        s->pmsts |= TMROF_EN;

    return s->pmsts;

    qemu_set_irq(s->irq, sci_level);

    /* schedule a timer interruption if needed */

    if ((s->pmen & TMROF_EN) && !(pmsts & TMROF_EN)) {

        qemu_mod_timer(s->tmr_timer, expire_time);

    } else {

        qemu_del_timer(s->tmr_timer);

            pmsts = get_pmsts(s);

            if (pmsts & val & TMROF_EN) {

                /* if TMRSTS is reset, then compute the new overflow time */

                s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;

            }

            s->pmsts &= ~val;

    s->ticking[n] = 1;

#ifdef DEBUG

    exp = qemu_get_clock (vm_clock) + interval;

    s->exp[n] = exp;

#endif

        int i;

        /* Allow 100ms to complete the DisplayData packet */

        for (i = 0; i < baum->x * baum->y ; i++) {

            EAT(c);

            cells[i] = c;

    switch (cmd) {

    case CHR_IOCTL_SERIAL_SET_PARAMS:

        ssp = (QEMUSerialSetParams *) arg;

        /* Moments later... (but shorter than 100ms) */

        s->modem_state |= CHR_TIOCM_CTS;

        break;

    s->out_len = 0;

    s->out_size = FIFO_LEN;

    s->in_len = 0;

    s->enable = 0;

    s->in_hdr = INT_MAX;

    s->in_data = INT_MAX;

static void bt_hci_mod_timer_1280ms(QEMUTimer *timer, int period)

{

    qemu_mod_timer(timer, qemu_get_clock(vm_clock) +

}

static void bt_hci_inquiry_start(struct bt_hci_s *hci, int length)

    bt_hci_event_status(hci, HCI_SUCCESS);

    qemu_mod_timer(link->acl_mode_timer, qemu_get_clock(vm_clock) +

    bt_hci_lmp_mode_change_master(hci, link->link, mode, interval);

    return 0;

    unsigned int counter;

    d = muldiv64(qemu_get_clock(vm_clock) - s->load_time,

    if (s->index == 0) {

        /* the timer goes down from latch to -1 (period of latch + 2) */

        if (d <= (s->counter_value + 1)) {

    /* current counter value */

    d = muldiv64(current_time - s->load_time,

    /* the timer goes down from latch to -1 (period of latch + 2) */

    if (d <= (s->counter_value + 1)) {

        counter = (s->counter_value - d) & 0xffff;

    }

    CUDA_DPRINTF("latch=%d counter=%" PRId64 " delta_next=%" PRId64 "\n",

                 s->latch, d, next_time - d);

        s->load_time;

    if (next_time <= current_time)

        next_time = current_time + 1;

    }

    qemu_mod_timer(s->adb_poll_timer,

                   qemu_get_clock(vm_clock) +

}

static void cuda_receive_packet(CUDAState *s,

            if (autopoll) {

                qemu_mod_timer(s->adb_poll_timer,

                               qemu_get_clock(vm_clock) +

            } else {

                qemu_del_timer(s->adb_poll_timer);

            }

        break;

    case CUDA_SET_TIME:

        ti = (((uint32_t)data[1]) << 24) + (((uint32_t)data[2]) << 16) + (((uint32_t)data[3]) << 8) + data[4];

        obuf[0] = CUDA_PACKET;

        obuf[1] = 0;

        obuf[2] = 0;

        cuda_send_packet_to_host(s, obuf, 3);

        break;

    case CUDA_GET_TIME:

        obuf[0] = CUDA_PACKET;

        obuf[1] = 0;

        obuf[2] = 0;

    ticks = s->regs[SONIC_WT1] << 16 | s->regs[SONIC_WT0];

    s->wt_last_update = qemu_get_clock(vm_clock);

    qemu_mod_timer(s->watchdog, s->wt_last_update + delay);

}

    /* XXX: should set main status register to busy */

    cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;

    qemu_mod_timer(fdctrl->result_timer,

}

static void fdctrl_handle_format_track (fdctrl_t *fdctrl, int direction)

    uint64_t d;

    int counter;

    switch(s->mode) {

    case 0:

    case 1:

    uint64_t d;

    int out;

    switch(s->mode) {

    default:

    case 0:

    uint64_t d, next_time, base;

    int period2;

    switch(s->mode) {

    default:

    case 0:

        break;

    }

    /* convert to timer units */

    /* fix potential rounding problems */

    /* XXX: better solution: use a clock at PIT_FREQ Hz */

    if (next_time <= current_time)

#ifdef DEBUG_PIT

    printf("irq_level=%d next_delay=%f\n",

           irq_level,

#endif

    s->next_transition_time = expire_time;

    if (expire_time != -1)

#ifdef DEBUG_IRQ_LATENCY

    printf("IRQ%d latency=%0.3fus\n",

           irq,

#endif

#if defined(DEBUG_PIC)

    printf("pic_interrupt: irq=%d\n", irq);

           option _only_ to install Windows 2000. You must disable it

           for normal use. */

        qemu_mod_timer(s->sector_write_timer, 

    } else 

#endif

    {

        /* divide each RTC interval to 2 - 8 smaller intervals */

        int c = MIN(s->irq_coalesced, 7) + 1; 

        int64_t next_clock = qemu_get_clock(vm_clock) +

        qemu_mod_timer(s->coalesced_timer, next_clock);

    }

}

        s->period = period;

#endif

        /* compute 32 khz clock */

        next_irq_clock = (cur_clock & ~(period - 1)) + period;

        qemu_mod_timer(s->periodic_timer, s->next_periodic_time);

    } else {

#ifdef TARGET_I386

    /* if the oscillator is not in normal operation, we do not update */

    if ((s->cmos_data[RTC_REG_A] & 0x70) != 0x20) {

        qemu_mod_timer(s->second_timer, s->next_second_time);

    } else {

        rtc_next_second(&s->current_tm);

        }

        /* should be 244 us = 8 / 32768 seconds, but currently the

           timers do not have the necessary resolution. */

        if (delay < 1)

            delay = 1;

        qemu_mod_timer(s->second_timer2,

    /* clear update in progress bit */

    s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;

    qemu_mod_timer(s->second_timer, s->next_second_time);

}

    s->second_timer2 = qemu_new_timer(vm_clock,

                                      rtc_update_second2, s);

    qemu_mod_timer(s->second_timer2, s->next_second_time);

    register_ioport_write(base, 2, 1, cmos_ioport_write, s);

    s->second_timer2 = qemu_new_timer(vm_clock,

                                      rtc_update_second2, s);

    qemu_mod_timer(s->second_timer2, s->next_second_time);

    io_memory = cpu_register_io_memory(rtc_mm_read, rtc_mm_write, s);

    else

        return env->CP0_Count +

            (uint32_t)muldiv64(qemu_get_clock(vm_clock),

}

static void cpu_mips_timer_update(CPUState *env)

    now = qemu_get_clock(vm_clock);

    wait = env->CP0_Compare - env->CP0_Count -

    qemu_mod_timer(env->timer, next);

}

        /* Store new count register */

        env->CP0_Count =

            count - (uint32_t)muldiv64(qemu_get_clock(vm_clock),

        /* Update timer timer */

        cpu_mips_timer_update(env);

    }

{

    /* Store the current value */

    env->CP0_Count += (uint32_t)muldiv64(qemu_get_clock(vm_clock),

}

static void mips_timer_cb (void *opaque)

    if (timer->st && timer->enable && timer->rate)

        return timer->val - muldiv64(distance >> (timer->ptv + 1),

    else

        return timer->val;

}

    if (timer->enable && timer->st && timer->rate) {

        timer->val = timer->reset_val;	/* Should skip this on clk enable */

        expires = muldiv64((uint64_t) timer->val << (timer->ptv + 1),

        /* If timer expiry would be sooner than in about 1 ms and

         * auto-reload isn't set, then fire immediately.  This is a hack

         * sets the interval to a very low value and polls the status bit

         * in a busy loop when it wants to sleep just a couple of CPU

         * ticks.  */

            qemu_mod_timer(timer->timer, timer->time + expires);

        else

            qemu_bh_schedule(timer->tick);

                now -= s->ulpd_gauge_start;

                /* 32-kHz ticks */

                s->ulpd_pm_regs[0x00 >> 2] = (ticks >>  0) & 0xffff;

                s->ulpd_pm_regs[0x04 >> 2] = (ticks >> 16) & 0xffff;

                if (ticks >> 32)	/* OVERFLOW_32K */

                    s->ulpd_pm_regs[0x14 >> 2] |= 1 << 2;

                /* High frequency ticks */

                s->ulpd_pm_regs[0x08 >> 2] = (ticks >>  0) & 0xffff;

                s->ulpd_pm_regs[0x0c >> 2] = (ticks >> 16) & 0xffff;

                if (ticks >> 32)	/* OVERFLOW_HI_FREQ */

    s->rx_req = s->rx_rate << bps[(s->rcr[0] >> 5) & 7];

    omap_mcbsp_rx_newdata(s);

}

static void omap_mcbsp_rx_start(struct omap_mcbsp_s *s)

    s->tx_req = s->tx_rate << bps[(s->xcr[0] >> 5) & 7];

    omap_mcbsp_tx_newdata(s);

}

static void omap_mcbsp_tx_start(struct omap_mcbsp_s *s)

        if (s->trigger == gpt_trigger_none)

            omap_gp_timer_out(s, s->scpwm);

        /* TODO: make sure this doesn't overflow 32-bits */

        omap_gp_timer_update(s);

        break;

/* 32-kHz Sync Timer of the OMAP2 */

static uint32_t omap_synctimer_read(struct omap_synctimer_s *s) {

}

static void omap_synctimer_reset(struct omap_synctimer_s *s)

{

    int64_t next_time = current_time +

        muldiv64(65536 - (CSR_SPND(s) ? 0 : CSR_POLL(s)),

    if (next_time <= current_time)

        next_time = current_time + 1;

    return next_time;

            pflash_update(pfl, 0, pfl->chip_len);

            /* Let's wait 5 seconds before chip erase is done */

            qemu_mod_timer(pfl->timer,

            break;

        case 0x30:

            /* Sector erase */

            pfl->status = 0x00;

            /* Let's wait 1/2 second before sector erase is done */

            qemu_mod_timer(pfl->timer,

            break;

        default:

            DPRINTF("%s: invalid command %02x (wc 5)\n", __func__, cmd);

{

    /* This assumes qemu_get_clock returns the time since the machine was

       created.  */

}

static void pl031_set_alarm(pl031_state *s)

    uint32_t ticks;

    now = qemu_get_clock(vm_clock);

    /* The timer wraps around.  This subtraction also wraps in the same way,

       and gives correct results when alarm < now_ticks.  */

        qemu_del_timer(s->timer);

        pl031_interrupt(s);

    } else {

    }

}

                                      int64_t tb_offset)

{

    /* TB time in tb periods */

}

uint32_t cpu_ppc_load_tbl (CPUState *env)

static inline void cpu_ppc_store_tb(ppc_tb_t *tb_env, uint64_t vmclk,

                                    int64_t *tb_offsetp, uint64_t value)

{

    LOG_TB("%s: tb %016" PRIx64 " offset %08" PRIx64 "\n",

                __func__, value, *tb_offsetp);

}

    diff = next - qemu_get_clock(vm_clock);

    if (diff >= 0)

    else

    LOG_TB("%s: %08" PRIx32 "\n", __func__, decr);

    return decr;

    diff = qemu_get_clock(vm_clock) - tb_env->purr_start;

}

/* When decrementer expires,

    LOG_TB("%s: %08" PRIx32 " => %08" PRIx32 "\n", __func__,

                decr, value);

    now = qemu_get_clock(vm_clock);

    if (is_excp)

        next += *nextp - now;

    if (next == now)

        /* Cannot occur, but makes gcc happy */

        return;

    }

    if (next == now)

        next++;

    qemu_mod_timer(ppcemb_timer->fit_timer, next);

                    __func__, ppcemb_timer->pit_reload);

        now = qemu_get_clock(vm_clock);

        next = now + muldiv64(ppcemb_timer->pit_reload,

        if (is_excp)

            next += tb_env->decr_next - now;

        if (next == now)

        /* Cannot occur, but makes gcc happy */

        return;

    }

    if (next == now)

        next++;

    LOG_TB("%s: TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__,

    case 0x00:

        /* Time base counter */

        ret = muldiv64(qemu_get_clock(vm_clock) + gpt->tb_offset,

        break;

    case 0x10:

        /* Output enable */

    switch (addr) {

    case 0x00:

        /* Time base counter */

            - qemu_get_clock(vm_clock);

        ppc4xx_gpt_compute_timer(gpt);

        break;

    uint64_t new_qemu;

    now_vm = s->clock +

    for (i = 0; i < 4; i ++) {

        new_qemu = now_qemu + muldiv64((uint32_t) (s->timer[i].value - now_vm),

        qemu_mod_timer(s->timer[i].qtimer, new_qemu);

    }

}

    now_vm = s->tm4[counter].clock + muldiv64(now_qemu -

                    s->tm4[counter].lastload,

    new_qemu = now_qemu + muldiv64((uint32_t) (s->tm4[n].tm.value - now_vm),

    qemu_mod_timer(s->tm4[n].tm.qtimer, new_qemu);

}

        return s->tm4[tm].tm.value;

    case OSCR:

        return s->clock + muldiv64(qemu_get_clock(vm_clock) -

    case OSCR11: tm ++;

    case OSCR10: tm ++;

    case OSCR9:  tm ++;

                s->snapshot = s->tm4[tm - 1].clock + muldiv64(

                                qemu_get_clock(vm_clock) -

                                s->tm4[tm - 1].lastload,

            else

                s->snapshot = s->tm4[tm - 1].clock;

        }

        if (!s->tm4[tm].freq)

            return s->tm4[tm].clock;

        return s->tm4[tm].clock + muldiv64(qemu_get_clock(vm_clock) -

    case OIER:

        return s->irq_enabled;

    case OSSR:	/* Status register */

    tm_hz = 1000 / (s->itr + 1);

}

/* called for accesses to rc4030 */

static inline int64_t rtl8139_get_next_tctr_time(RTL8139State *s, int64_t current_time)

{

    int64_t next_time = current_time +

    if (next_time <= current_time)

        next_time = current_time + 1;

    return next_time;

    curr_time = qemu_get_clock(vm_clock);

    if (s->TimerInt && curr_tick >= s->TimerInt)

    {

                freq = s->freq > 0 ? s->freq : 11025;

                samples = dsp_get_lohi (s) + 1;

                bytes = samples << s->fmt_stereo << (s->fmt_bits == 16);

                    qemu_irq_raise (s->pic);

                }

                else {

    ssp.parity = parity;

    ssp.data_bits = data_bits;

    ssp.stop_bits = stop_bits;

    qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);

#if 0

    printf("speed=%d parity=%c data=%d stop=%d\n",

       We'll be lazy and poll only every 10ms, and only poll it at all if MSI interrupts are turned on */

    if (s->poll_msl)

}

static void serial_xmit(void *opaque)

    s->mcr = UART_MCR_OUT2;

    s->scr = 0;

    s->tsr_retry = 0;

    s->poll_msl = 0;

    fifo_clear(s,RECV_FIFO);

            s->fifopos = 0;

    }

}

static void spitz_keyboard_pre_map(SpitzKeyboardState *s)

        tick += (int64_t)count * system_clock_scale;

    } else if (s->config == 1) {

        /* 32-bit RTC.  1Hz tick.  */

    } else if (s->mode[n] == 0xa) {

        /* PWM mode.  Not implemented.  */

    } else {

    s->precision = s->nextprecision;

    s->function = s->nextfunction;

    s->pdst = !s->pnd0;	/* Synchronised on internal clock */

    qemu_mod_timer(s->timer, expires);

}

    s->busy = 1;

    s->precision = s->nextprecision;

    s->function = s->nextfunction;

    qemu_mod_timer(s->timer, expires);

}

        if (value & TUSB_DEV_OTG_TIMER_ENABLE)

            qemu_mod_timer(s->otg_timer, qemu_get_clock(vm_clock) +

                            muldiv64(TUSB_DEV_OTG_TIMER_VAL(value),

        else

            qemu_del_timer(s->otg_timer);

        break;

        s->intr_ok = 0;

        tusb_intr_update(s);

        qemu_mod_timer(s->pwr_timer,

    }

}

        ep->intv_timer[dir] = qemu_new_timer(vm_clock, musb_cb_tick, opaque);

    qemu_mod_timer(ep->intv_timer[dir], qemu_get_clock(vm_clock) +

}

static void musb_schedule0_cb(USBPacket *packey, void *opaque)

    if (usb_frame_time == 0) {

#ifdef OHCI_TIME_WARP

#else

        } else {

            usb_bit_time = 1;

        }

    /* prepare the timer for the next frame */

    expire_time = qemu_get_clock(vm_clock) +

    qemu_mod_timer(s->frame_timer, expire_time);

}

    r->total_chars = vtotal_lines * htotal_chars;

    if (r->freq) {

    } else {

    }

    r->vstart = vretr_start_line;

        "dots = %d\n"

        "ticks/char = %lld\n"

        "\n",

        htotal_chars,

        hretr_start_char,

        hretr_skew_chars,

        timeout <<= 5;

    /* Get the timeout in units of ticks_per_sec. */

    i6300esb_debug("stage %d, timeout %" PRIi64 "\n", d->stage, timeout);

    ib700_debug("addr = %x, data = %x\n", addr, data);

    qemu_mod_timer(timer, qemu_get_clock (vm_clock) + timeout);

}

    }

    /* delayed key up events */

    qemu_mod_timer(key_timer, qemu_get_clock(vm_clock) +

}

static int mouse_button_state;

    if (total == 0)

        total = 1;

    monitor_printf(mon, "async time  %" PRId64 " (%0.3f)\n",

    monitor_printf(mon, "qemu time   %" PRId64 " (%0.3f)\n",

    qemu_time = 0;

    dev_time = 0;

}

        return size;

    }

    caplen = size > s->pcap_caplen ? s->pcap_caplen : size;

    hdr.ts.tv_sec = ts / 1000000;

int qemu_timer_pending(QEMUTimer *ts);

int qemu_timer_expired(QEMUTimer *timer_head, int64_t current_time);

void qemu_get_timer(QEMUFile *f, QEMUTimer *ts);

void qemu_put_timer(QEMUFile *f, QEMUTimer *ts);

     * an idle guest does no IO, qemu's device model will never get a chance to

     * run. So, until Qemu gains IO threads, we create this timer to ensure

     * that the device model gets a chance to run. */

    kvmppc_timer = qemu_new_timer(vm_clock, &kvmppc_timer_hack, NULL);

    qemu_mod_timer(kvmppc_timer, qemu_get_clock(vm_clock) + kvmppc_timer_rate);

}

static DisplayState *display_state;

DisplayType display_type = DT_DEFAULT;

const char* keyboard_layout = NULL;

ram_addr_t ram_size;

int nb_nics;

NICInfo nd_table[MAX_NICS];

    }

}

static void init_timers(void)

{

    init_get_clock();

            delta_cum += delta;

            if (++count == DISP_FREQ) {

                printf("timer: min=%" PRId64 " us max=%" PRId64 " us avg=%" PRId64 " us avg_freq=%0.3f Hz\n",

                count = 0;

                delta_min = INT64_MAX;

                delta_max = 0;