Revision 6ee093c9 hw/ppc405_uc.c

b/hw/ppc405_uc.c
1379 1379 
    case 0x00:
1380 1380 
        /* Time base counter */
1381 1381 
        ret = muldiv64(qemu_get_clock(vm_clock) + gpt->tb_offset,
1382 
                       gpt->tb_freq, ticks_per_sec);
1382 
                       gpt->tb_freq, get_ticks_per_sec());
1383 1383 
        break;
1384 1384 
    case 0x10:
1385 1385 
        /* Output enable */
......
1434 1434 
    switch (addr) {
1435 1435 
    case 0x00:
1436 1436 
        /* Time base counter */
1437 
        gpt->tb_offset = muldiv64(value, ticks_per_sec, gpt->tb_freq)
1437 
        gpt->tb_offset = muldiv64(value, get_ticks_per_sec(), gpt->tb_freq)
1438 1438 
            - qemu_get_clock(vm_clock);
1439 1439 
        ppc4xx_gpt_compute_timer(gpt);
1440 1440 
        break;

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