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/*
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SPARC translation
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Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
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Copyright (C) 2003-2005 Fabrice Bellard
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This library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2 of the License, or (at your option) any later version.
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This library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with this library; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/*
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TODO-list:
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Rest of V9 instructions, VIS instructions
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NPC/PC static optimisations (use JUMP_TB when possible)
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Optimize synthetic instructions
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128-bit float
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*/
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#include <stdarg.h> |
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#include <stdlib.h> |
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#include <stdio.h> |
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#include <string.h> |
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#include <inttypes.h> |
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#include "cpu.h" |
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#include "exec-all.h" |
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#include "disas.h" |
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#define DEBUG_DISAS
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#define DYNAMIC_PC 1 /* dynamic pc value */ |
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#define JUMP_PC 2 /* dynamic pc value which takes only two values |
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according to jump_pc[T2] */
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typedef struct DisasContext { |
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target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
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target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
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target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */ |
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int is_br;
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int mem_idx;
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int fpu_enabled;
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struct TranslationBlock *tb;
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} DisasContext; |
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struct sparc_def_t {
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const unsigned char *name; |
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target_ulong iu_version; |
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uint32_t fpu_version; |
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uint32_t mmu_version; |
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}; |
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static uint16_t *gen_opc_ptr;
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static uint32_t *gen_opparam_ptr;
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extern FILE *logfile;
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extern int loglevel; |
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enum {
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#define DEF(s,n,copy_size) INDEX_op_ ## s, |
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#include "opc.h" |
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#undef DEF
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NB_OPS |
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}; |
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#include "gen-op.h" |
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// This function uses non-native bit order
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#define GET_FIELD(X, FROM, TO) \
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((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1)) |
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// This function uses the order in the manuals, i.e. bit 0 is 2^0
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#define GET_FIELD_SP(X, FROM, TO) \
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GET_FIELD(X, 31 - (TO), 31 - (FROM)) |
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#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1) |
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#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1)) |
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#ifdef TARGET_SPARC64
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#define DFPREG(r) (((r & 1) << 6) | (r & 0x1e)) |
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#else
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#define DFPREG(r) (r & 0x1e) |
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#endif
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#ifdef USE_DIRECT_JUMP
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#define TBPARAM(x)
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#else
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#define TBPARAM(x) (long)(x) |
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#endif
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static int sign_extend(int x, int len) |
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{ |
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len = 32 - len;
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return (x << len) >> len;
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} |
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#define IS_IMM (insn & (1<<13)) |
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static void disas_sparc_insn(DisasContext * dc); |
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static GenOpFunc * const gen_op_movl_TN_reg[2][32] = { |
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{ |
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gen_op_movl_g0_T0, |
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gen_op_movl_g1_T0, |
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gen_op_movl_g2_T0, |
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gen_op_movl_g3_T0, |
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gen_op_movl_g4_T0, |
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gen_op_movl_g5_T0, |
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gen_op_movl_g6_T0, |
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gen_op_movl_g7_T0, |
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gen_op_movl_o0_T0, |
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gen_op_movl_o1_T0, |
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gen_op_movl_o2_T0, |
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gen_op_movl_o3_T0, |
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gen_op_movl_o4_T0, |
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gen_op_movl_o5_T0, |
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gen_op_movl_o6_T0, |
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gen_op_movl_o7_T0, |
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gen_op_movl_l0_T0, |
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gen_op_movl_l1_T0, |
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gen_op_movl_l2_T0, |
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gen_op_movl_l3_T0, |
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gen_op_movl_l4_T0, |
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gen_op_movl_l5_T0, |
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gen_op_movl_l6_T0, |
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gen_op_movl_l7_T0, |
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gen_op_movl_i0_T0, |
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gen_op_movl_i1_T0, |
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gen_op_movl_i2_T0, |
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gen_op_movl_i3_T0, |
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gen_op_movl_i4_T0, |
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gen_op_movl_i5_T0, |
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gen_op_movl_i6_T0, |
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gen_op_movl_i7_T0, |
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}, |
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{ |
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gen_op_movl_g0_T1, |
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gen_op_movl_g1_T1, |
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gen_op_movl_g2_T1, |
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gen_op_movl_g3_T1, |
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gen_op_movl_g4_T1, |
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gen_op_movl_g5_T1, |
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gen_op_movl_g6_T1, |
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gen_op_movl_g7_T1, |
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gen_op_movl_o0_T1, |
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gen_op_movl_o1_T1, |
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gen_op_movl_o2_T1, |
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gen_op_movl_o3_T1, |
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gen_op_movl_o4_T1, |
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gen_op_movl_o5_T1, |
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gen_op_movl_o6_T1, |
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gen_op_movl_o7_T1, |
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gen_op_movl_l0_T1, |
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gen_op_movl_l1_T1, |
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gen_op_movl_l2_T1, |
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gen_op_movl_l3_T1, |
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gen_op_movl_l4_T1, |
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gen_op_movl_l5_T1, |
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gen_op_movl_l6_T1, |
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gen_op_movl_l7_T1, |
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gen_op_movl_i0_T1, |
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gen_op_movl_i1_T1, |
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gen_op_movl_i2_T1, |
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gen_op_movl_i3_T1, |
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gen_op_movl_i4_T1, |
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gen_op_movl_i5_T1, |
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gen_op_movl_i6_T1, |
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gen_op_movl_i7_T1, |
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} |
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}; |
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static GenOpFunc * const gen_op_movl_reg_TN[3][32] = { |
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{ |
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gen_op_movl_T0_g0, |
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gen_op_movl_T0_g1, |
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gen_op_movl_T0_g2, |
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gen_op_movl_T0_g3, |
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gen_op_movl_T0_g4, |
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gen_op_movl_T0_g5, |
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gen_op_movl_T0_g6, |
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gen_op_movl_T0_g7, |
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gen_op_movl_T0_o0, |
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gen_op_movl_T0_o1, |
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gen_op_movl_T0_o2, |
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gen_op_movl_T0_o3, |
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gen_op_movl_T0_o4, |
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gen_op_movl_T0_o5, |
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gen_op_movl_T0_o6, |
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gen_op_movl_T0_o7, |
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gen_op_movl_T0_l0, |
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gen_op_movl_T0_l1, |
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gen_op_movl_T0_l2, |
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gen_op_movl_T0_l3, |
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gen_op_movl_T0_l4, |
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gen_op_movl_T0_l5, |
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gen_op_movl_T0_l6, |
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gen_op_movl_T0_l7, |
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gen_op_movl_T0_i0, |
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gen_op_movl_T0_i1, |
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gen_op_movl_T0_i2, |
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gen_op_movl_T0_i3, |
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gen_op_movl_T0_i4, |
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gen_op_movl_T0_i5, |
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gen_op_movl_T0_i6, |
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gen_op_movl_T0_i7, |
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}, |
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{ |
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gen_op_movl_T1_g0, |
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gen_op_movl_T1_g1, |
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gen_op_movl_T1_g2, |
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gen_op_movl_T1_g3, |
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gen_op_movl_T1_g4, |
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gen_op_movl_T1_g5, |
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gen_op_movl_T1_g6, |
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gen_op_movl_T1_g7, |
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gen_op_movl_T1_o0, |
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gen_op_movl_T1_o1, |
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gen_op_movl_T1_o2, |
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gen_op_movl_T1_o3, |
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gen_op_movl_T1_o4, |
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gen_op_movl_T1_o5, |
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gen_op_movl_T1_o6, |
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gen_op_movl_T1_o7, |
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gen_op_movl_T1_l0, |
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gen_op_movl_T1_l1, |
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gen_op_movl_T1_l2, |
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gen_op_movl_T1_l3, |
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gen_op_movl_T1_l4, |
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gen_op_movl_T1_l5, |
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gen_op_movl_T1_l6, |
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gen_op_movl_T1_l7, |
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gen_op_movl_T1_i0, |
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gen_op_movl_T1_i1, |
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gen_op_movl_T1_i2, |
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gen_op_movl_T1_i3, |
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gen_op_movl_T1_i4, |
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gen_op_movl_T1_i5, |
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gen_op_movl_T1_i6, |
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gen_op_movl_T1_i7, |
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}, |
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{ |
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gen_op_movl_T2_g0, |
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gen_op_movl_T2_g1, |
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gen_op_movl_T2_g2, |
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gen_op_movl_T2_g3, |
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gen_op_movl_T2_g4, |
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gen_op_movl_T2_g5, |
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gen_op_movl_T2_g6, |
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gen_op_movl_T2_g7, |
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gen_op_movl_T2_o0, |
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gen_op_movl_T2_o1, |
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gen_op_movl_T2_o2, |
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gen_op_movl_T2_o3, |
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gen_op_movl_T2_o4, |
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gen_op_movl_T2_o5, |
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gen_op_movl_T2_o6, |
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gen_op_movl_T2_o7, |
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gen_op_movl_T2_l0, |
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gen_op_movl_T2_l1, |
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gen_op_movl_T2_l2, |
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gen_op_movl_T2_l3, |
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gen_op_movl_T2_l4, |
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gen_op_movl_T2_l5, |
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gen_op_movl_T2_l6, |
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gen_op_movl_T2_l7, |
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gen_op_movl_T2_i0, |
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gen_op_movl_T2_i1, |
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gen_op_movl_T2_i2, |
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gen_op_movl_T2_i3, |
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gen_op_movl_T2_i4, |
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gen_op_movl_T2_i5, |
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gen_op_movl_T2_i6, |
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gen_op_movl_T2_i7, |
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} |
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}; |
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static GenOpFunc1 * const gen_op_movl_TN_im[3] = { |
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gen_op_movl_T0_im, |
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gen_op_movl_T1_im, |
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gen_op_movl_T2_im |
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}; |
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// Sign extending version
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static GenOpFunc1 * const gen_op_movl_TN_sim[3] = { |
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gen_op_movl_T0_sim, |
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gen_op_movl_T1_sim, |
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gen_op_movl_T2_sim |
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}; |
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#ifdef TARGET_SPARC64
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#define GEN32(func, NAME) \
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static GenOpFunc * const NAME ## _table [64] = { \ |
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NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \ |
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NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \ |
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NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \ |
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NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \ |
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NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \ |
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NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \ |
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NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \ |
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NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \ |
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NAME ## 32, 0, NAME ## 34, 0, NAME ## 36, 0, NAME ## 38, 0, \ |
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NAME ## 40, 0, NAME ## 42, 0, NAME ## 44, 0, NAME ## 46, 0, \ |
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NAME ## 48, 0, NAME ## 50, 0, NAME ## 52, 0, NAME ## 54, 0, \ |
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NAME ## 56, 0, NAME ## 58, 0, NAME ## 60, 0, NAME ## 62, 0, \ |
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}; \ |
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static inline void func(int n) \ |
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{ \ |
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NAME ## _table[n](); \ |
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} |
320 |
#else
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#define GEN32(func, NAME) \
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static GenOpFunc *const NAME ## _table [32] = { \ |
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NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \ |
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NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \ |
325 |
NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \ |
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NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \ |
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NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \ |
328 |
NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \ |
329 |
NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \ |
330 |
NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \ |
331 |
}; \ |
332 |
static inline void func(int n) \ |
333 |
{ \ |
334 |
NAME ## _table[n](); \ |
335 |
} |
336 |
#endif
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337 |
|
338 |
/* floating point registers moves */
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GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fprf); |
340 |
GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fprf); |
341 |
GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fprf); |
342 |
GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fprf); |
343 |
|
344 |
GEN32(gen_op_load_fpr_DT0, gen_op_load_fpr_DT0_fprf); |
345 |
GEN32(gen_op_load_fpr_DT1, gen_op_load_fpr_DT1_fprf); |
346 |
GEN32(gen_op_store_DT0_fpr, gen_op_store_DT0_fpr_fprf); |
347 |
GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf); |
348 |
|
349 |
#ifdef TARGET_SPARC64
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350 |
// 'a' versions allowed to user depending on asi
|
351 |
#if defined(CONFIG_USER_ONLY)
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352 |
#define supervisor(dc) 0 |
353 |
#define hypervisor(dc) 0 |
354 |
#define gen_op_ldst(name) gen_op_##name##_raw() |
355 |
#define OP_LD_TABLE(width) \
|
356 |
static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \ |
357 |
{ \ |
358 |
int asi, offset; \
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359 |
\ |
360 |
if (IS_IMM) { \
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361 |
offset = GET_FIELD(insn, 25, 31); \ |
362 |
if (is_ld) \
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363 |
gen_op_ld_asi_reg(offset, size, sign); \ |
364 |
else \
|
365 |
gen_op_st_asi_reg(offset, size, sign); \ |
366 |
return; \
|
367 |
} \ |
368 |
asi = GET_FIELD(insn, 19, 26); \ |
369 |
switch (asi) { \
|
370 |
case 0x80: /* Primary address space */ \ |
371 |
gen_op_##width##_raw(); \ |
372 |
break; \
|
373 |
case 0x82: /* Primary address space, non-faulting load */ \ |
374 |
gen_op_##width##_raw(); \ |
375 |
break; \
|
376 |
default: \
|
377 |
break; \
|
378 |
} \ |
379 |
} |
380 |
|
381 |
#else
|
382 |
#define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])() |
383 |
#define OP_LD_TABLE(width) \
|
384 |
static GenOpFunc * const gen_op_##width[] = { \ |
385 |
&gen_op_##width##_user, \ |
386 |
&gen_op_##width##_kernel, \ |
387 |
}; \ |
388 |
\ |
389 |
static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \ |
390 |
{ \ |
391 |
int asi, offset; \
|
392 |
\ |
393 |
if (IS_IMM) { \
|
394 |
offset = GET_FIELD(insn, 25, 31); \ |
395 |
if (is_ld) \
|
396 |
gen_op_ld_asi_reg(offset, size, sign); \ |
397 |
else \
|
398 |
gen_op_st_asi_reg(offset, size, sign); \ |
399 |
return; \
|
400 |
} \ |
401 |
asi = GET_FIELD(insn, 19, 26); \ |
402 |
if (is_ld) \
|
403 |
gen_op_ld_asi(asi, size, sign); \ |
404 |
else \
|
405 |
gen_op_st_asi(asi, size, sign); \ |
406 |
} |
407 |
|
408 |
#define supervisor(dc) (dc->mem_idx == 1) |
409 |
#define hypervisor(dc) (dc->mem_idx == 2) |
410 |
#endif
|
411 |
#else
|
412 |
#if defined(CONFIG_USER_ONLY)
|
413 |
#define gen_op_ldst(name) gen_op_##name##_raw() |
414 |
#define OP_LD_TABLE(width)
|
415 |
#define supervisor(dc) 0 |
416 |
#else
|
417 |
#define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])() |
418 |
#define OP_LD_TABLE(width) \
|
419 |
static GenOpFunc * const gen_op_##width[] = { \ |
420 |
&gen_op_##width##_user, \ |
421 |
&gen_op_##width##_kernel, \ |
422 |
}; \ |
423 |
\ |
424 |
static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \ |
425 |
{ \ |
426 |
int asi; \
|
427 |
\ |
428 |
asi = GET_FIELD(insn, 19, 26); \ |
429 |
switch (asi) { \
|
430 |
case 10: /* User data access */ \ |
431 |
gen_op_##width##_user(); \ |
432 |
break; \
|
433 |
case 11: /* Supervisor data access */ \ |
434 |
gen_op_##width##_kernel(); \ |
435 |
break; \
|
436 |
case 0x20 ... 0x2f: /* MMU passthrough */ \ |
437 |
if (is_ld) \
|
438 |
gen_op_ld_asi(asi, size, sign); \ |
439 |
else \
|
440 |
gen_op_st_asi(asi, size, sign); \ |
441 |
break; \
|
442 |
default: \
|
443 |
if (is_ld) \
|
444 |
gen_op_ld_asi(asi, size, sign); \ |
445 |
else \
|
446 |
gen_op_st_asi(asi, size, sign); \ |
447 |
break; \
|
448 |
} \ |
449 |
} |
450 |
|
451 |
#define supervisor(dc) (dc->mem_idx == 1) |
452 |
#endif
|
453 |
#endif
|
454 |
|
455 |
OP_LD_TABLE(ld); |
456 |
OP_LD_TABLE(st); |
457 |
OP_LD_TABLE(ldub); |
458 |
OP_LD_TABLE(lduh); |
459 |
OP_LD_TABLE(ldsb); |
460 |
OP_LD_TABLE(ldsh); |
461 |
OP_LD_TABLE(stb); |
462 |
OP_LD_TABLE(sth); |
463 |
OP_LD_TABLE(std); |
464 |
OP_LD_TABLE(ldstub); |
465 |
OP_LD_TABLE(swap); |
466 |
OP_LD_TABLE(ldd); |
467 |
OP_LD_TABLE(stf); |
468 |
OP_LD_TABLE(stdf); |
469 |
OP_LD_TABLE(ldf); |
470 |
OP_LD_TABLE(lddf); |
471 |
|
472 |
#ifdef TARGET_SPARC64
|
473 |
OP_LD_TABLE(ldsw); |
474 |
OP_LD_TABLE(ldx); |
475 |
OP_LD_TABLE(stx); |
476 |
OP_LD_TABLE(cas); |
477 |
OP_LD_TABLE(casx); |
478 |
#endif
|
479 |
|
480 |
static inline void gen_movl_imm_TN(int reg, uint32_t imm) |
481 |
{ |
482 |
gen_op_movl_TN_im[reg](imm); |
483 |
} |
484 |
|
485 |
static inline void gen_movl_imm_T1(uint32_t val) |
486 |
{ |
487 |
gen_movl_imm_TN(1, val);
|
488 |
} |
489 |
|
490 |
static inline void gen_movl_imm_T0(uint32_t val) |
491 |
{ |
492 |
gen_movl_imm_TN(0, val);
|
493 |
} |
494 |
|
495 |
static inline void gen_movl_simm_TN(int reg, int32_t imm) |
496 |
{ |
497 |
gen_op_movl_TN_sim[reg](imm); |
498 |
} |
499 |
|
500 |
static inline void gen_movl_simm_T1(int32_t val) |
501 |
{ |
502 |
gen_movl_simm_TN(1, val);
|
503 |
} |
504 |
|
505 |
static inline void gen_movl_simm_T0(int32_t val) |
506 |
{ |
507 |
gen_movl_simm_TN(0, val);
|
508 |
} |
509 |
|
510 |
static inline void gen_movl_reg_TN(int reg, int t) |
511 |
{ |
512 |
if (reg)
|
513 |
gen_op_movl_reg_TN[t][reg] (); |
514 |
else
|
515 |
gen_movl_imm_TN(t, 0);
|
516 |
} |
517 |
|
518 |
static inline void gen_movl_reg_T0(int reg) |
519 |
{ |
520 |
gen_movl_reg_TN(reg, 0);
|
521 |
} |
522 |
|
523 |
static inline void gen_movl_reg_T1(int reg) |
524 |
{ |
525 |
gen_movl_reg_TN(reg, 1);
|
526 |
} |
527 |
|
528 |
static inline void gen_movl_reg_T2(int reg) |
529 |
{ |
530 |
gen_movl_reg_TN(reg, 2);
|
531 |
} |
532 |
|
533 |
static inline void gen_movl_TN_reg(int reg, int t) |
534 |
{ |
535 |
if (reg)
|
536 |
gen_op_movl_TN_reg[t][reg] (); |
537 |
} |
538 |
|
539 |
static inline void gen_movl_T0_reg(int reg) |
540 |
{ |
541 |
gen_movl_TN_reg(reg, 0);
|
542 |
} |
543 |
|
544 |
static inline void gen_movl_T1_reg(int reg) |
545 |
{ |
546 |
gen_movl_TN_reg(reg, 1);
|
547 |
} |
548 |
|
549 |
static inline void gen_jmp_im(target_ulong pc) |
550 |
{ |
551 |
#ifdef TARGET_SPARC64
|
552 |
if (pc == (uint32_t)pc) {
|
553 |
gen_op_jmp_im(pc); |
554 |
} else {
|
555 |
gen_op_jmp_im64(pc >> 32, pc);
|
556 |
} |
557 |
#else
|
558 |
gen_op_jmp_im(pc); |
559 |
#endif
|
560 |
} |
561 |
|
562 |
static inline void gen_movl_npc_im(target_ulong npc) |
563 |
{ |
564 |
#ifdef TARGET_SPARC64
|
565 |
if (npc == (uint32_t)npc) {
|
566 |
gen_op_movl_npc_im(npc); |
567 |
} else {
|
568 |
gen_op_movq_npc_im64(npc >> 32, npc);
|
569 |
} |
570 |
#else
|
571 |
gen_op_movl_npc_im(npc); |
572 |
#endif
|
573 |
} |
574 |
|
575 |
static inline void gen_goto_tb(DisasContext *s, int tb_num, |
576 |
target_ulong pc, target_ulong npc) |
577 |
{ |
578 |
TranslationBlock *tb; |
579 |
|
580 |
tb = s->tb; |
581 |
if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
|
582 |
(npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK)) { |
583 |
/* jump to same page: we can use a direct jump */
|
584 |
if (tb_num == 0) |
585 |
gen_op_goto_tb0(TBPARAM(tb)); |
586 |
else
|
587 |
gen_op_goto_tb1(TBPARAM(tb)); |
588 |
gen_jmp_im(pc); |
589 |
gen_movl_npc_im(npc); |
590 |
gen_op_movl_T0_im((long)tb + tb_num);
|
591 |
gen_op_exit_tb(); |
592 |
} else {
|
593 |
/* jump to another page: currently not optimized */
|
594 |
gen_jmp_im(pc); |
595 |
gen_movl_npc_im(npc); |
596 |
gen_op_movl_T0_0(); |
597 |
gen_op_exit_tb(); |
598 |
} |
599 |
} |
600 |
|
601 |
static inline void gen_branch2(DisasContext *dc, target_ulong pc1, |
602 |
target_ulong pc2) |
603 |
{ |
604 |
int l1;
|
605 |
|
606 |
l1 = gen_new_label(); |
607 |
|
608 |
gen_op_jz_T2_label(l1); |
609 |
|
610 |
gen_goto_tb(dc, 0, pc1, pc1 + 4); |
611 |
|
612 |
gen_set_label(l1); |
613 |
gen_goto_tb(dc, 1, pc2, pc2 + 4); |
614 |
} |
615 |
|
616 |
static inline void gen_branch_a(DisasContext *dc, target_ulong pc1, |
617 |
target_ulong pc2) |
618 |
{ |
619 |
int l1;
|
620 |
|
621 |
l1 = gen_new_label(); |
622 |
|
623 |
gen_op_jz_T2_label(l1); |
624 |
|
625 |
gen_goto_tb(dc, 0, pc2, pc1);
|
626 |
|
627 |
gen_set_label(l1); |
628 |
gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8); |
629 |
} |
630 |
|
631 |
static inline void gen_branch(DisasContext *dc, target_ulong pc, |
632 |
target_ulong npc) |
633 |
{ |
634 |
gen_goto_tb(dc, 0, pc, npc);
|
635 |
} |
636 |
|
637 |
static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2) |
638 |
{ |
639 |
int l1, l2;
|
640 |
|
641 |
l1 = gen_new_label(); |
642 |
l2 = gen_new_label(); |
643 |
gen_op_jz_T2_label(l1); |
644 |
|
645 |
gen_movl_npc_im(npc1); |
646 |
gen_op_jmp_label(l2); |
647 |
|
648 |
gen_set_label(l1); |
649 |
gen_movl_npc_im(npc2); |
650 |
gen_set_label(l2); |
651 |
} |
652 |
|
653 |
/* call this function before using T2 as it may have been set for a jump */
|
654 |
static inline void flush_T2(DisasContext * dc) |
655 |
{ |
656 |
if (dc->npc == JUMP_PC) {
|
657 |
gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1]); |
658 |
dc->npc = DYNAMIC_PC; |
659 |
} |
660 |
} |
661 |
|
662 |
static inline void save_npc(DisasContext * dc) |
663 |
{ |
664 |
if (dc->npc == JUMP_PC) {
|
665 |
gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1]); |
666 |
dc->npc = DYNAMIC_PC; |
667 |
} else if (dc->npc != DYNAMIC_PC) { |
668 |
gen_movl_npc_im(dc->npc); |
669 |
} |
670 |
} |
671 |
|
672 |
static inline void save_state(DisasContext * dc) |
673 |
{ |
674 |
gen_jmp_im(dc->pc); |
675 |
save_npc(dc); |
676 |
} |
677 |
|
678 |
static inline void gen_mov_pc_npc(DisasContext * dc) |
679 |
{ |
680 |
if (dc->npc == JUMP_PC) {
|
681 |
gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1]); |
682 |
gen_op_mov_pc_npc(); |
683 |
dc->pc = DYNAMIC_PC; |
684 |
} else if (dc->npc == DYNAMIC_PC) { |
685 |
gen_op_mov_pc_npc(); |
686 |
dc->pc = DYNAMIC_PC; |
687 |
} else {
|
688 |
dc->pc = dc->npc; |
689 |
} |
690 |
} |
691 |
|
692 |
static GenOpFunc * const gen_cond[2][16] = { |
693 |
{ |
694 |
gen_op_eval_bn, |
695 |
gen_op_eval_be, |
696 |
gen_op_eval_ble, |
697 |
gen_op_eval_bl, |
698 |
gen_op_eval_bleu, |
699 |
gen_op_eval_bcs, |
700 |
gen_op_eval_bneg, |
701 |
gen_op_eval_bvs, |
702 |
gen_op_eval_ba, |
703 |
gen_op_eval_bne, |
704 |
gen_op_eval_bg, |
705 |
gen_op_eval_bge, |
706 |
gen_op_eval_bgu, |
707 |
gen_op_eval_bcc, |
708 |
gen_op_eval_bpos, |
709 |
gen_op_eval_bvc, |
710 |
}, |
711 |
{ |
712 |
#ifdef TARGET_SPARC64
|
713 |
gen_op_eval_bn, |
714 |
gen_op_eval_xbe, |
715 |
gen_op_eval_xble, |
716 |
gen_op_eval_xbl, |
717 |
gen_op_eval_xbleu, |
718 |
gen_op_eval_xbcs, |
719 |
gen_op_eval_xbneg, |
720 |
gen_op_eval_xbvs, |
721 |
gen_op_eval_ba, |
722 |
gen_op_eval_xbne, |
723 |
gen_op_eval_xbg, |
724 |
gen_op_eval_xbge, |
725 |
gen_op_eval_xbgu, |
726 |
gen_op_eval_xbcc, |
727 |
gen_op_eval_xbpos, |
728 |
gen_op_eval_xbvc, |
729 |
#endif
|
730 |
}, |
731 |
}; |
732 |
|
733 |
static GenOpFunc * const gen_fcond[4][16] = { |
734 |
{ |
735 |
gen_op_eval_bn, |
736 |
gen_op_eval_fbne, |
737 |
gen_op_eval_fblg, |
738 |
gen_op_eval_fbul, |
739 |
gen_op_eval_fbl, |
740 |
gen_op_eval_fbug, |
741 |
gen_op_eval_fbg, |
742 |
gen_op_eval_fbu, |
743 |
gen_op_eval_ba, |
744 |
gen_op_eval_fbe, |
745 |
gen_op_eval_fbue, |
746 |
gen_op_eval_fbge, |
747 |
gen_op_eval_fbuge, |
748 |
gen_op_eval_fble, |
749 |
gen_op_eval_fbule, |
750 |
gen_op_eval_fbo, |
751 |
}, |
752 |
#ifdef TARGET_SPARC64
|
753 |
{ |
754 |
gen_op_eval_bn, |
755 |
gen_op_eval_fbne_fcc1, |
756 |
gen_op_eval_fblg_fcc1, |
757 |
gen_op_eval_fbul_fcc1, |
758 |
gen_op_eval_fbl_fcc1, |
759 |
gen_op_eval_fbug_fcc1, |
760 |
gen_op_eval_fbg_fcc1, |
761 |
gen_op_eval_fbu_fcc1, |
762 |
gen_op_eval_ba, |
763 |
gen_op_eval_fbe_fcc1, |
764 |
gen_op_eval_fbue_fcc1, |
765 |
gen_op_eval_fbge_fcc1, |
766 |
gen_op_eval_fbuge_fcc1, |
767 |
gen_op_eval_fble_fcc1, |
768 |
gen_op_eval_fbule_fcc1, |
769 |
gen_op_eval_fbo_fcc1, |
770 |
}, |
771 |
{ |
772 |
gen_op_eval_bn, |
773 |
gen_op_eval_fbne_fcc2, |
774 |
gen_op_eval_fblg_fcc2, |
775 |
gen_op_eval_fbul_fcc2, |
776 |
gen_op_eval_fbl_fcc2, |
777 |
gen_op_eval_fbug_fcc2, |
778 |
gen_op_eval_fbg_fcc2, |
779 |
gen_op_eval_fbu_fcc2, |
780 |
gen_op_eval_ba, |
781 |
gen_op_eval_fbe_fcc2, |
782 |
gen_op_eval_fbue_fcc2, |
783 |
gen_op_eval_fbge_fcc2, |
784 |
gen_op_eval_fbuge_fcc2, |
785 |
gen_op_eval_fble_fcc2, |
786 |
gen_op_eval_fbule_fcc2, |
787 |
gen_op_eval_fbo_fcc2, |
788 |
}, |
789 |
{ |
790 |
gen_op_eval_bn, |
791 |
gen_op_eval_fbne_fcc3, |
792 |
gen_op_eval_fblg_fcc3, |
793 |
gen_op_eval_fbul_fcc3, |
794 |
gen_op_eval_fbl_fcc3, |
795 |
gen_op_eval_fbug_fcc3, |
796 |
gen_op_eval_fbg_fcc3, |
797 |
gen_op_eval_fbu_fcc3, |
798 |
gen_op_eval_ba, |
799 |
gen_op_eval_fbe_fcc3, |
800 |
gen_op_eval_fbue_fcc3, |
801 |
gen_op_eval_fbge_fcc3, |
802 |
gen_op_eval_fbuge_fcc3, |
803 |
gen_op_eval_fble_fcc3, |
804 |
gen_op_eval_fbule_fcc3, |
805 |
gen_op_eval_fbo_fcc3, |
806 |
}, |
807 |
#else
|
808 |
{}, {}, {}, |
809 |
#endif
|
810 |
}; |
811 |
|
812 |
#ifdef TARGET_SPARC64
|
813 |
static void gen_cond_reg(int cond) |
814 |
{ |
815 |
switch (cond) {
|
816 |
case 0x1: |
817 |
gen_op_eval_brz(); |
818 |
break;
|
819 |
case 0x2: |
820 |
gen_op_eval_brlez(); |
821 |
break;
|
822 |
case 0x3: |
823 |
gen_op_eval_brlz(); |
824 |
break;
|
825 |
case 0x5: |
826 |
gen_op_eval_brnz(); |
827 |
break;
|
828 |
case 0x6: |
829 |
gen_op_eval_brgz(); |
830 |
break;
|
831 |
default:
|
832 |
case 0x7: |
833 |
gen_op_eval_brgez(); |
834 |
break;
|
835 |
} |
836 |
} |
837 |
#endif
|
838 |
|
839 |
/* XXX: potentially incorrect if dynamic npc */
|
840 |
static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn, int cc) |
841 |
{ |
842 |
unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); |
843 |
target_ulong target = dc->pc + offset; |
844 |
|
845 |
if (cond == 0x0) { |
846 |
/* unconditional not taken */
|
847 |
if (a) {
|
848 |
dc->pc = dc->npc + 4;
|
849 |
dc->npc = dc->pc + 4;
|
850 |
} else {
|
851 |
dc->pc = dc->npc; |
852 |
dc->npc = dc->pc + 4;
|
853 |
} |
854 |
} else if (cond == 0x8) { |
855 |
/* unconditional taken */
|
856 |
if (a) {
|
857 |
dc->pc = target; |
858 |
dc->npc = dc->pc + 4;
|
859 |
} else {
|
860 |
dc->pc = dc->npc; |
861 |
dc->npc = target; |
862 |
} |
863 |
} else {
|
864 |
flush_T2(dc); |
865 |
gen_cond[cc][cond](); |
866 |
if (a) {
|
867 |
gen_branch_a(dc, target, dc->npc); |
868 |
dc->is_br = 1;
|
869 |
} else {
|
870 |
dc->pc = dc->npc; |
871 |
dc->jump_pc[0] = target;
|
872 |
dc->jump_pc[1] = dc->npc + 4; |
873 |
dc->npc = JUMP_PC; |
874 |
} |
875 |
} |
876 |
} |
877 |
|
878 |
/* XXX: potentially incorrect if dynamic npc */
|
879 |
static void do_fbranch(DisasContext * dc, int32_t offset, uint32_t insn, int cc) |
880 |
{ |
881 |
unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); |
882 |
target_ulong target = dc->pc + offset; |
883 |
|
884 |
if (cond == 0x0) { |
885 |
/* unconditional not taken */
|
886 |
if (a) {
|
887 |
dc->pc = dc->npc + 4;
|
888 |
dc->npc = dc->pc + 4;
|
889 |
} else {
|
890 |
dc->pc = dc->npc; |
891 |
dc->npc = dc->pc + 4;
|
892 |
} |
893 |
} else if (cond == 0x8) { |
894 |
/* unconditional taken */
|
895 |
if (a) {
|
896 |
dc->pc = target; |
897 |
dc->npc = dc->pc + 4;
|
898 |
} else {
|
899 |
dc->pc = dc->npc; |
900 |
dc->npc = target; |
901 |
} |
902 |
} else {
|
903 |
flush_T2(dc); |
904 |
gen_fcond[cc][cond](); |
905 |
if (a) {
|
906 |
gen_branch_a(dc, target, dc->npc); |
907 |
dc->is_br = 1;
|
908 |
} else {
|
909 |
dc->pc = dc->npc; |
910 |
dc->jump_pc[0] = target;
|
911 |
dc->jump_pc[1] = dc->npc + 4; |
912 |
dc->npc = JUMP_PC; |
913 |
} |
914 |
} |
915 |
} |
916 |
|
917 |
#ifdef TARGET_SPARC64
|
918 |
/* XXX: potentially incorrect if dynamic npc */
|
919 |
static void do_branch_reg(DisasContext * dc, int32_t offset, uint32_t insn) |
920 |
{ |
921 |
unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29)); |
922 |
target_ulong target = dc->pc + offset; |
923 |
|
924 |
flush_T2(dc); |
925 |
gen_cond_reg(cond); |
926 |
if (a) {
|
927 |
gen_branch_a(dc, target, dc->npc); |
928 |
dc->is_br = 1;
|
929 |
} else {
|
930 |
dc->pc = dc->npc; |
931 |
dc->jump_pc[0] = target;
|
932 |
dc->jump_pc[1] = dc->npc + 4; |
933 |
dc->npc = JUMP_PC; |
934 |
} |
935 |
} |
936 |
|
937 |
static GenOpFunc * const gen_fcmps[4] = { |
938 |
gen_op_fcmps, |
939 |
gen_op_fcmps_fcc1, |
940 |
gen_op_fcmps_fcc2, |
941 |
gen_op_fcmps_fcc3, |
942 |
}; |
943 |
|
944 |
static GenOpFunc * const gen_fcmpd[4] = { |
945 |
gen_op_fcmpd, |
946 |
gen_op_fcmpd_fcc1, |
947 |
gen_op_fcmpd_fcc2, |
948 |
gen_op_fcmpd_fcc3, |
949 |
}; |
950 |
|
951 |
static GenOpFunc * const gen_fcmpes[4] = { |
952 |
gen_op_fcmpes, |
953 |
gen_op_fcmpes_fcc1, |
954 |
gen_op_fcmpes_fcc2, |
955 |
gen_op_fcmpes_fcc3, |
956 |
}; |
957 |
|
958 |
static GenOpFunc * const gen_fcmped[4] = { |
959 |
gen_op_fcmped, |
960 |
gen_op_fcmped_fcc1, |
961 |
gen_op_fcmped_fcc2, |
962 |
gen_op_fcmped_fcc3, |
963 |
}; |
964 |
|
965 |
#endif
|
966 |
|
967 |
static int gen_trap_ifnofpu(DisasContext * dc) |
968 |
{ |
969 |
#if !defined(CONFIG_USER_ONLY)
|
970 |
if (!dc->fpu_enabled) {
|
971 |
save_state(dc); |
972 |
gen_op_exception(TT_NFPU_INSN); |
973 |
dc->is_br = 1;
|
974 |
return 1; |
975 |
} |
976 |
#endif
|
977 |
return 0; |
978 |
} |
979 |
|
980 |
/* before an instruction, dc->pc must be static */
|
981 |
static void disas_sparc_insn(DisasContext * dc) |
982 |
{ |
983 |
unsigned int insn, opc, rs1, rs2, rd; |
984 |
|
985 |
insn = ldl_code(dc->pc); |
986 |
opc = GET_FIELD(insn, 0, 1); |
987 |
|
988 |
rd = GET_FIELD(insn, 2, 6); |
989 |
switch (opc) {
|
990 |
case 0: /* branches/sethi */ |
991 |
{ |
992 |
unsigned int xop = GET_FIELD(insn, 7, 9); |
993 |
int32_t target; |
994 |
switch (xop) {
|
995 |
#ifdef TARGET_SPARC64
|
996 |
case 0x1: /* V9 BPcc */ |
997 |
{ |
998 |
int cc;
|
999 |
|
1000 |
target = GET_FIELD_SP(insn, 0, 18); |
1001 |
target = sign_extend(target, 18);
|
1002 |
target <<= 2;
|
1003 |
cc = GET_FIELD_SP(insn, 20, 21); |
1004 |
if (cc == 0) |
1005 |
do_branch(dc, target, insn, 0);
|
1006 |
else if (cc == 2) |
1007 |
do_branch(dc, target, insn, 1);
|
1008 |
else
|
1009 |
goto illegal_insn;
|
1010 |
goto jmp_insn;
|
1011 |
} |
1012 |
case 0x3: /* V9 BPr */ |
1013 |
{ |
1014 |
target = GET_FIELD_SP(insn, 0, 13) | |
1015 |
(GET_FIELD_SP(insn, 20, 21) << 14); |
1016 |
target = sign_extend(target, 16);
|
1017 |
target <<= 2;
|
1018 |
rs1 = GET_FIELD(insn, 13, 17); |
1019 |
gen_movl_reg_T0(rs1); |
1020 |
do_branch_reg(dc, target, insn); |
1021 |
goto jmp_insn;
|
1022 |
} |
1023 |
case 0x5: /* V9 FBPcc */ |
1024 |
{ |
1025 |
int cc = GET_FIELD_SP(insn, 20, 21); |
1026 |
if (gen_trap_ifnofpu(dc))
|
1027 |
goto jmp_insn;
|
1028 |
target = GET_FIELD_SP(insn, 0, 18); |
1029 |
target = sign_extend(target, 19);
|
1030 |
target <<= 2;
|
1031 |
do_fbranch(dc, target, insn, cc); |
1032 |
goto jmp_insn;
|
1033 |
} |
1034 |
#else
|
1035 |
case 0x7: /* CBN+x */ |
1036 |
{ |
1037 |
goto ncp_insn;
|
1038 |
} |
1039 |
#endif
|
1040 |
case 0x2: /* BN+x */ |
1041 |
{ |
1042 |
target = GET_FIELD(insn, 10, 31); |
1043 |
target = sign_extend(target, 22);
|
1044 |
target <<= 2;
|
1045 |
do_branch(dc, target, insn, 0);
|
1046 |
goto jmp_insn;
|
1047 |
} |
1048 |
case 0x6: /* FBN+x */ |
1049 |
{ |
1050 |
if (gen_trap_ifnofpu(dc))
|
1051 |
goto jmp_insn;
|
1052 |
target = GET_FIELD(insn, 10, 31); |
1053 |
target = sign_extend(target, 22);
|
1054 |
target <<= 2;
|
1055 |
do_fbranch(dc, target, insn, 0);
|
1056 |
goto jmp_insn;
|
1057 |
} |
1058 |
case 0x4: /* SETHI */ |
1059 |
#define OPTIM
|
1060 |
#if defined(OPTIM)
|
1061 |
if (rd) { // nop |
1062 |
#endif
|
1063 |
uint32_t value = GET_FIELD(insn, 10, 31); |
1064 |
gen_movl_imm_T0(value << 10);
|
1065 |
gen_movl_T0_reg(rd); |
1066 |
#if defined(OPTIM)
|
1067 |
} |
1068 |
#endif
|
1069 |
break;
|
1070 |
case 0x0: /* UNIMPL */ |
1071 |
default:
|
1072 |
goto illegal_insn;
|
1073 |
} |
1074 |
break;
|
1075 |
} |
1076 |
break;
|
1077 |
case 1: |
1078 |
/*CALL*/ {
|
1079 |
target_long target = GET_FIELDs(insn, 2, 31) << 2; |
1080 |
|
1081 |
#ifdef TARGET_SPARC64
|
1082 |
if (dc->pc == (uint32_t)dc->pc) {
|
1083 |
gen_op_movl_T0_im(dc->pc); |
1084 |
} else {
|
1085 |
gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
|
1086 |
} |
1087 |
#else
|
1088 |
gen_op_movl_T0_im(dc->pc); |
1089 |
#endif
|
1090 |
gen_movl_T0_reg(15);
|
1091 |
target += dc->pc; |
1092 |
gen_mov_pc_npc(dc); |
1093 |
dc->npc = target; |
1094 |
} |
1095 |
goto jmp_insn;
|
1096 |
case 2: /* FPU & Logical Operations */ |
1097 |
{ |
1098 |
unsigned int xop = GET_FIELD(insn, 7, 12); |
1099 |
if (xop == 0x3a) { /* generate trap */ |
1100 |
int cond;
|
1101 |
|
1102 |
rs1 = GET_FIELD(insn, 13, 17); |
1103 |
gen_movl_reg_T0(rs1); |
1104 |
if (IS_IMM) {
|
1105 |
rs2 = GET_FIELD(insn, 25, 31); |
1106 |
#if defined(OPTIM)
|
1107 |
if (rs2 != 0) { |
1108 |
#endif
|
1109 |
gen_movl_simm_T1(rs2); |
1110 |
gen_op_add_T1_T0(); |
1111 |
#if defined(OPTIM)
|
1112 |
} |
1113 |
#endif
|
1114 |
} else {
|
1115 |
rs2 = GET_FIELD(insn, 27, 31); |
1116 |
#if defined(OPTIM)
|
1117 |
if (rs2 != 0) { |
1118 |
#endif
|
1119 |
gen_movl_reg_T1(rs2); |
1120 |
gen_op_add_T1_T0(); |
1121 |
#if defined(OPTIM)
|
1122 |
} |
1123 |
#endif
|
1124 |
} |
1125 |
cond = GET_FIELD(insn, 3, 6); |
1126 |
if (cond == 0x8) { |
1127 |
save_state(dc); |
1128 |
gen_op_trap_T0(); |
1129 |
} else if (cond != 0) { |
1130 |
#ifdef TARGET_SPARC64
|
1131 |
/* V9 icc/xcc */
|
1132 |
int cc = GET_FIELD_SP(insn, 11, 12); |
1133 |
flush_T2(dc); |
1134 |
save_state(dc); |
1135 |
if (cc == 0) |
1136 |
gen_cond[0][cond]();
|
1137 |
else if (cc == 2) |
1138 |
gen_cond[1][cond]();
|
1139 |
else
|
1140 |
goto illegal_insn;
|
1141 |
#else
|
1142 |
flush_T2(dc); |
1143 |
save_state(dc); |
1144 |
gen_cond[0][cond]();
|
1145 |
#endif
|
1146 |
gen_op_trapcc_T0(); |
1147 |
} |
1148 |
gen_op_next_insn(); |
1149 |
gen_op_movl_T0_0(); |
1150 |
gen_op_exit_tb(); |
1151 |
dc->is_br = 1;
|
1152 |
goto jmp_insn;
|
1153 |
} else if (xop == 0x28) { |
1154 |
rs1 = GET_FIELD(insn, 13, 17); |
1155 |
switch(rs1) {
|
1156 |
case 0: /* rdy */ |
1157 |
#ifndef TARGET_SPARC64
|
1158 |
case 0x01 ... 0x0e: /* undefined in the SPARCv8 |
1159 |
manual, rdy on the microSPARC
|
1160 |
II */
|
1161 |
case 0x0f: /* stbar in the SPARCv8 manual, |
1162 |
rdy on the microSPARC II */
|
1163 |
case 0x10 ... 0x1f: /* implementation-dependent in the |
1164 |
SPARCv8 manual, rdy on the
|
1165 |
microSPARC II */
|
1166 |
#endif
|
1167 |
gen_op_movtl_T0_env(offsetof(CPUSPARCState, y)); |
1168 |
gen_movl_T0_reg(rd); |
1169 |
break;
|
1170 |
#ifdef TARGET_SPARC64
|
1171 |
case 0x2: /* V9 rdccr */ |
1172 |
gen_op_rdccr(); |
1173 |
gen_movl_T0_reg(rd); |
1174 |
break;
|
1175 |
case 0x3: /* V9 rdasi */ |
1176 |
gen_op_movl_T0_env(offsetof(CPUSPARCState, asi)); |
1177 |
gen_movl_T0_reg(rd); |
1178 |
break;
|
1179 |
case 0x4: /* V9 rdtick */ |
1180 |
gen_op_rdtick(); |
1181 |
gen_movl_T0_reg(rd); |
1182 |
break;
|
1183 |
case 0x5: /* V9 rdpc */ |
1184 |
if (dc->pc == (uint32_t)dc->pc) {
|
1185 |
gen_op_movl_T0_im(dc->pc); |
1186 |
} else {
|
1187 |
gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
|
1188 |
} |
1189 |
gen_movl_T0_reg(rd); |
1190 |
break;
|
1191 |
case 0x6: /* V9 rdfprs */ |
1192 |
gen_op_movl_T0_env(offsetof(CPUSPARCState, fprs)); |
1193 |
gen_movl_T0_reg(rd); |
1194 |
break;
|
1195 |
case 0xf: /* V9 membar */ |
1196 |
break; /* no effect */ |
1197 |
case 0x13: /* Graphics Status */ |
1198 |
if (gen_trap_ifnofpu(dc))
|
1199 |
goto jmp_insn;
|
1200 |
gen_op_movtl_T0_env(offsetof(CPUSPARCState, gsr)); |
1201 |
gen_movl_T0_reg(rd); |
1202 |
break;
|
1203 |
case 0x17: /* Tick compare */ |
1204 |
gen_op_movtl_T0_env(offsetof(CPUSPARCState, tick_cmpr)); |
1205 |
gen_movl_T0_reg(rd); |
1206 |
break;
|
1207 |
case 0x18: /* System tick */ |
1208 |
gen_op_rdstick(); |
1209 |
gen_movl_T0_reg(rd); |
1210 |
break;
|
1211 |
case 0x19: /* System tick compare */ |
1212 |
gen_op_movtl_T0_env(offsetof(CPUSPARCState, stick_cmpr)); |
1213 |
gen_movl_T0_reg(rd); |
1214 |
break;
|
1215 |
case 0x10: /* Performance Control */ |
1216 |
case 0x11: /* Performance Instrumentation Counter */ |
1217 |
case 0x12: /* Dispatch Control */ |
1218 |
case 0x14: /* Softint set, WO */ |
1219 |
case 0x15: /* Softint clear, WO */ |
1220 |
case 0x16: /* Softint write */ |
1221 |
#endif
|
1222 |
default:
|
1223 |
goto illegal_insn;
|
1224 |
} |
1225 |
#if !defined(CONFIG_USER_ONLY)
|
1226 |
} else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */ |
1227 |
#ifndef TARGET_SPARC64
|
1228 |
if (!supervisor(dc))
|
1229 |
goto priv_insn;
|
1230 |
gen_op_rdpsr(); |
1231 |
#else
|
1232 |
if (!hypervisor(dc))
|
1233 |
goto priv_insn;
|
1234 |
rs1 = GET_FIELD(insn, 13, 17); |
1235 |
switch (rs1) {
|
1236 |
case 0: // hpstate |
1237 |
// gen_op_rdhpstate();
|
1238 |
break;
|
1239 |
case 1: // htstate |
1240 |
// gen_op_rdhtstate();
|
1241 |
break;
|
1242 |
case 3: // hintp |
1243 |
gen_op_movl_T0_env(offsetof(CPUSPARCState, hintp)); |
1244 |
break;
|
1245 |
case 5: // htba |
1246 |
gen_op_movl_T0_env(offsetof(CPUSPARCState, htba)); |
1247 |
break;
|
1248 |
case 6: // hver |
1249 |
gen_op_movl_T0_env(offsetof(CPUSPARCState, hver)); |
1250 |
break;
|
1251 |
case 31: // hstick_cmpr |
1252 |
gen_op_movl_env_T0(offsetof(CPUSPARCState, hstick_cmpr)); |
1253 |
break;
|
1254 |
default:
|
1255 |
goto illegal_insn;
|
1256 |
} |
1257 |
#endif
|
1258 |
gen_movl_T0_reg(rd); |
1259 |
break;
|
1260 |
} else if (xop == 0x2a) { /* rdwim / V9 rdpr */ |
1261 |
if (!supervisor(dc))
|
1262 |
goto priv_insn;
|
1263 |
#ifdef TARGET_SPARC64
|
1264 |
rs1 = GET_FIELD(insn, 13, 17); |
1265 |
switch (rs1) {
|
1266 |
case 0: // tpc |
1267 |
gen_op_rdtpc(); |
1268 |
break;
|
1269 |
case 1: // tnpc |
1270 |
gen_op_rdtnpc(); |
1271 |
break;
|
1272 |
case 2: // tstate |
1273 |
gen_op_rdtstate(); |
1274 |
break;
|
1275 |
case 3: // tt |
1276 |
gen_op_rdtt(); |
1277 |
break;
|
1278 |
case 4: // tick |
1279 |
gen_op_rdtick(); |
1280 |
break;
|
1281 |
case 5: // tba |
1282 |
gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr)); |
1283 |
break;
|
1284 |
case 6: // pstate |
1285 |
gen_op_rdpstate(); |
1286 |
break;
|
1287 |
case 7: // tl |
1288 |
gen_op_movl_T0_env(offsetof(CPUSPARCState, tl)); |
1289 |
break;
|
1290 |
case 8: // pil |
1291 |
gen_op_movl_T0_env(offsetof(CPUSPARCState, psrpil)); |
1292 |
break;
|
1293 |
case 9: // cwp |
1294 |
gen_op_rdcwp(); |
1295 |
break;
|
1296 |
case 10: // cansave |
1297 |
gen_op_movl_T0_env(offsetof(CPUSPARCState, cansave)); |
1298 |
break;
|
1299 |
case 11: // canrestore |
1300 |
gen_op_movl_T0_env(offsetof(CPUSPARCState, canrestore)); |
1301 |
break;
|
1302 |
case 12: // cleanwin |
1303 |
gen_op_movl_T0_env(offsetof(CPUSPARCState, cleanwin)); |
1304 |
break;
|
1305 |
case 13: // otherwin |
1306 |
gen_op_movl_T0_env(offsetof(CPUSPARCState, otherwin)); |
1307 |
break;
|
1308 |
case 14: // wstate |
1309 |
gen_op_movl_T0_env(offsetof(CPUSPARCState, wstate)); |
1310 |
break;
|
1311 |
case 16: // UA2005 gl |
1312 |
gen_op_movl_T0_env(offsetof(CPUSPARCState, gl)); |
1313 |
break;
|
1314 |
case 26: // UA2005 strand status |
1315 |
if (!hypervisor(dc))
|
1316 |
goto priv_insn;
|
1317 |
gen_op_movl_T0_env(offsetof(CPUSPARCState, ssr)); |
1318 |
break;
|
1319 |
case 31: // ver |
1320 |
gen_op_movtl_T0_env(offsetof(CPUSPARCState, version)); |
1321 |
break;
|
1322 |
case 15: // fq |
1323 |
default:
|
1324 |
goto illegal_insn;
|
1325 |
} |
1326 |
#else
|
1327 |
gen_op_movl_T0_env(offsetof(CPUSPARCState, wim)); |
1328 |
#endif
|
1329 |
gen_movl_T0_reg(rd); |
1330 |
break;
|
1331 |
} else if (xop == 0x2b) { /* rdtbr / V9 flushw */ |
1332 |
#ifdef TARGET_SPARC64
|
1333 |
gen_op_flushw(); |
1334 |
#else
|
1335 |
if (!supervisor(dc))
|
1336 |
goto priv_insn;
|
1337 |
gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr)); |
1338 |
gen_movl_T0_reg(rd); |
1339 |
#endif
|
1340 |
break;
|
1341 |
#endif
|
1342 |
} else if (xop == 0x34) { /* FPU Operations */ |
1343 |
if (gen_trap_ifnofpu(dc))
|
1344 |
goto jmp_insn;
|
1345 |
gen_op_clear_ieee_excp_and_FTT(); |
1346 |
rs1 = GET_FIELD(insn, 13, 17); |
1347 |
rs2 = GET_FIELD(insn, 27, 31); |
1348 |
xop = GET_FIELD(insn, 18, 26); |
1349 |
switch (xop) {
|
1350 |
case 0x1: /* fmovs */ |
1351 |
gen_op_load_fpr_FT0(rs2); |
1352 |
gen_op_store_FT0_fpr(rd); |
1353 |
break;
|
1354 |
case 0x5: /* fnegs */ |
1355 |
gen_op_load_fpr_FT1(rs2); |
1356 |
gen_op_fnegs(); |
1357 |
gen_op_store_FT0_fpr(rd); |
1358 |
break;
|
1359 |
case 0x9: /* fabss */ |
1360 |
gen_op_load_fpr_FT1(rs2); |
1361 |
gen_op_fabss(); |
1362 |
gen_op_store_FT0_fpr(rd); |
1363 |
break;
|
1364 |
case 0x29: /* fsqrts */ |
1365 |
gen_op_load_fpr_FT1(rs2); |
1366 |
gen_op_fsqrts(); |
1367 |
gen_op_store_FT0_fpr(rd); |
1368 |
break;
|
1369 |
case 0x2a: /* fsqrtd */ |
1370 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
1371 |
gen_op_fsqrtd(); |
1372 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
1373 |
break;
|
1374 |
case 0x2b: /* fsqrtq */ |
1375 |
goto nfpu_insn;
|
1376 |
case 0x41: |
1377 |
gen_op_load_fpr_FT0(rs1); |
1378 |
gen_op_load_fpr_FT1(rs2); |
1379 |
gen_op_fadds(); |
1380 |
gen_op_store_FT0_fpr(rd); |
1381 |
break;
|
1382 |
case 0x42: |
1383 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
1384 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
1385 |
gen_op_faddd(); |
1386 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
1387 |
break;
|
1388 |
case 0x43: /* faddq */ |
1389 |
goto nfpu_insn;
|
1390 |
case 0x45: |
1391 |
gen_op_load_fpr_FT0(rs1); |
1392 |
gen_op_load_fpr_FT1(rs2); |
1393 |
gen_op_fsubs(); |
1394 |
gen_op_store_FT0_fpr(rd); |
1395 |
break;
|
1396 |
case 0x46: |
1397 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
1398 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
1399 |
gen_op_fsubd(); |
1400 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
1401 |
break;
|
1402 |
case 0x47: /* fsubq */ |
1403 |
goto nfpu_insn;
|
1404 |
case 0x49: |
1405 |
gen_op_load_fpr_FT0(rs1); |
1406 |
gen_op_load_fpr_FT1(rs2); |
1407 |
gen_op_fmuls(); |
1408 |
gen_op_store_FT0_fpr(rd); |
1409 |
break;
|
1410 |
case 0x4a: |
1411 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
1412 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
1413 |
gen_op_fmuld(); |
1414 |
gen_op_store_DT0_fpr(rd); |
1415 |
break;
|
1416 |
case 0x4b: /* fmulq */ |
1417 |
goto nfpu_insn;
|
1418 |
case 0x4d: |
1419 |
gen_op_load_fpr_FT0(rs1); |
1420 |
gen_op_load_fpr_FT1(rs2); |
1421 |
gen_op_fdivs(); |
1422 |
gen_op_store_FT0_fpr(rd); |
1423 |
break;
|
1424 |
case 0x4e: |
1425 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
1426 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
1427 |
gen_op_fdivd(); |
1428 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
1429 |
break;
|
1430 |
case 0x4f: /* fdivq */ |
1431 |
goto nfpu_insn;
|
1432 |
case 0x69: |
1433 |
gen_op_load_fpr_FT0(rs1); |
1434 |
gen_op_load_fpr_FT1(rs2); |
1435 |
gen_op_fsmuld(); |
1436 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
1437 |
break;
|
1438 |
case 0x6e: /* fdmulq */ |
1439 |
goto nfpu_insn;
|
1440 |
case 0xc4: |
1441 |
gen_op_load_fpr_FT1(rs2); |
1442 |
gen_op_fitos(); |
1443 |
gen_op_store_FT0_fpr(rd); |
1444 |
break;
|
1445 |
case 0xc6: |
1446 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
1447 |
gen_op_fdtos(); |
1448 |
gen_op_store_FT0_fpr(rd); |
1449 |
break;
|
1450 |
case 0xc7: /* fqtos */ |
1451 |
goto nfpu_insn;
|
1452 |
case 0xc8: |
1453 |
gen_op_load_fpr_FT1(rs2); |
1454 |
gen_op_fitod(); |
1455 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
1456 |
break;
|
1457 |
case 0xc9: |
1458 |
gen_op_load_fpr_FT1(rs2); |
1459 |
gen_op_fstod(); |
1460 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
1461 |
break;
|
1462 |
case 0xcb: /* fqtod */ |
1463 |
goto nfpu_insn;
|
1464 |
case 0xcc: /* fitoq */ |
1465 |
goto nfpu_insn;
|
1466 |
case 0xcd: /* fstoq */ |
1467 |
goto nfpu_insn;
|
1468 |
case 0xce: /* fdtoq */ |
1469 |
goto nfpu_insn;
|
1470 |
case 0xd1: |
1471 |
gen_op_load_fpr_FT1(rs2); |
1472 |
gen_op_fstoi(); |
1473 |
gen_op_store_FT0_fpr(rd); |
1474 |
break;
|
1475 |
case 0xd2: |
1476 |
gen_op_load_fpr_DT1(rs2); |
1477 |
gen_op_fdtoi(); |
1478 |
gen_op_store_FT0_fpr(rd); |
1479 |
break;
|
1480 |
case 0xd3: /* fqtoi */ |
1481 |
goto nfpu_insn;
|
1482 |
#ifdef TARGET_SPARC64
|
1483 |
case 0x2: /* V9 fmovd */ |
1484 |
gen_op_load_fpr_DT0(DFPREG(rs2)); |
1485 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
1486 |
break;
|
1487 |
case 0x6: /* V9 fnegd */ |
1488 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
1489 |
gen_op_fnegd(); |
1490 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
1491 |
break;
|
1492 |
case 0xa: /* V9 fabsd */ |
1493 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
1494 |
gen_op_fabsd(); |
1495 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
1496 |
break;
|
1497 |
case 0x81: /* V9 fstox */ |
1498 |
gen_op_load_fpr_FT1(rs2); |
1499 |
gen_op_fstox(); |
1500 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
1501 |
break;
|
1502 |
case 0x82: /* V9 fdtox */ |
1503 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
1504 |
gen_op_fdtox(); |
1505 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
1506 |
break;
|
1507 |
case 0x84: /* V9 fxtos */ |
1508 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
1509 |
gen_op_fxtos(); |
1510 |
gen_op_store_FT0_fpr(rd); |
1511 |
break;
|
1512 |
case 0x88: /* V9 fxtod */ |
1513 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
1514 |
gen_op_fxtod(); |
1515 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
1516 |
break;
|
1517 |
case 0x3: /* V9 fmovq */ |
1518 |
case 0x7: /* V9 fnegq */ |
1519 |
case 0xb: /* V9 fabsq */ |
1520 |
case 0x83: /* V9 fqtox */ |
1521 |
case 0x8c: /* V9 fxtoq */ |
1522 |
goto nfpu_insn;
|
1523 |
#endif
|
1524 |
default:
|
1525 |
goto illegal_insn;
|
1526 |
} |
1527 |
} else if (xop == 0x35) { /* FPU Operations */ |
1528 |
#ifdef TARGET_SPARC64
|
1529 |
int cond;
|
1530 |
#endif
|
1531 |
if (gen_trap_ifnofpu(dc))
|
1532 |
goto jmp_insn;
|
1533 |
gen_op_clear_ieee_excp_and_FTT(); |
1534 |
rs1 = GET_FIELD(insn, 13, 17); |
1535 |
rs2 = GET_FIELD(insn, 27, 31); |
1536 |
xop = GET_FIELD(insn, 18, 26); |
1537 |
#ifdef TARGET_SPARC64
|
1538 |
if ((xop & 0x11f) == 0x005) { // V9 fmovsr |
1539 |
cond = GET_FIELD_SP(insn, 14, 17); |
1540 |
gen_op_load_fpr_FT0(rd); |
1541 |
gen_op_load_fpr_FT1(rs2); |
1542 |
rs1 = GET_FIELD(insn, 13, 17); |
1543 |
gen_movl_reg_T0(rs1); |
1544 |
flush_T2(dc); |
1545 |
gen_cond_reg(cond); |
1546 |
gen_op_fmovs_cc(); |
1547 |
gen_op_store_FT0_fpr(rd); |
1548 |
break;
|
1549 |
} else if ((xop & 0x11f) == 0x006) { // V9 fmovdr |
1550 |
cond = GET_FIELD_SP(insn, 14, 17); |
1551 |
gen_op_load_fpr_DT0(rd); |
1552 |
gen_op_load_fpr_DT1(rs2); |
1553 |
flush_T2(dc); |
1554 |
rs1 = GET_FIELD(insn, 13, 17); |
1555 |
gen_movl_reg_T0(rs1); |
1556 |
gen_cond_reg(cond); |
1557 |
gen_op_fmovs_cc(); |
1558 |
gen_op_store_DT0_fpr(rd); |
1559 |
break;
|
1560 |
} else if ((xop & 0x11f) == 0x007) { // V9 fmovqr |
1561 |
goto nfpu_insn;
|
1562 |
} |
1563 |
#endif
|
1564 |
switch (xop) {
|
1565 |
#ifdef TARGET_SPARC64
|
1566 |
case 0x001: /* V9 fmovscc %fcc0 */ |
1567 |
cond = GET_FIELD_SP(insn, 14, 17); |
1568 |
gen_op_load_fpr_FT0(rd); |
1569 |
gen_op_load_fpr_FT1(rs2); |
1570 |
flush_T2(dc); |
1571 |
gen_fcond[0][cond]();
|
1572 |
gen_op_fmovs_cc(); |
1573 |
gen_op_store_FT0_fpr(rd); |
1574 |
break;
|
1575 |
case 0x002: /* V9 fmovdcc %fcc0 */ |
1576 |
cond = GET_FIELD_SP(insn, 14, 17); |
1577 |
gen_op_load_fpr_DT0(rd); |
1578 |
gen_op_load_fpr_DT1(rs2); |
1579 |
flush_T2(dc); |
1580 |
gen_fcond[0][cond]();
|
1581 |
gen_op_fmovd_cc(); |
1582 |
gen_op_store_DT0_fpr(rd); |
1583 |
break;
|
1584 |
case 0x003: /* V9 fmovqcc %fcc0 */ |
1585 |
goto nfpu_insn;
|
1586 |
case 0x041: /* V9 fmovscc %fcc1 */ |
1587 |
cond = GET_FIELD_SP(insn, 14, 17); |
1588 |
gen_op_load_fpr_FT0(rd); |
1589 |
gen_op_load_fpr_FT1(rs2); |
1590 |
flush_T2(dc); |
1591 |
gen_fcond[1][cond]();
|
1592 |
gen_op_fmovs_cc(); |
1593 |
gen_op_store_FT0_fpr(rd); |
1594 |
break;
|
1595 |
case 0x042: /* V9 fmovdcc %fcc1 */ |
1596 |
cond = GET_FIELD_SP(insn, 14, 17); |
1597 |
gen_op_load_fpr_DT0(rd); |
1598 |
gen_op_load_fpr_DT1(rs2); |
1599 |
flush_T2(dc); |
1600 |
gen_fcond[1][cond]();
|
1601 |
gen_op_fmovd_cc(); |
1602 |
gen_op_store_DT0_fpr(rd); |
1603 |
break;
|
1604 |
case 0x043: /* V9 fmovqcc %fcc1 */ |
1605 |
goto nfpu_insn;
|
1606 |
case 0x081: /* V9 fmovscc %fcc2 */ |
1607 |
cond = GET_FIELD_SP(insn, 14, 17); |
1608 |
gen_op_load_fpr_FT0(rd); |
1609 |
gen_op_load_fpr_FT1(rs2); |
1610 |
flush_T2(dc); |
1611 |
gen_fcond[2][cond]();
|
1612 |
gen_op_fmovs_cc(); |
1613 |
gen_op_store_FT0_fpr(rd); |
1614 |
break;
|
1615 |
case 0x082: /* V9 fmovdcc %fcc2 */ |
1616 |
cond = GET_FIELD_SP(insn, 14, 17); |
1617 |
gen_op_load_fpr_DT0(rd); |
1618 |
gen_op_load_fpr_DT1(rs2); |
1619 |
flush_T2(dc); |
1620 |
gen_fcond[2][cond]();
|
1621 |
gen_op_fmovd_cc(); |
1622 |
gen_op_store_DT0_fpr(rd); |
1623 |
break;
|
1624 |
case 0x083: /* V9 fmovqcc %fcc2 */ |
1625 |
goto nfpu_insn;
|
1626 |
case 0x0c1: /* V9 fmovscc %fcc3 */ |
1627 |
cond = GET_FIELD_SP(insn, 14, 17); |
1628 |
gen_op_load_fpr_FT0(rd); |
1629 |
gen_op_load_fpr_FT1(rs2); |
1630 |
flush_T2(dc); |
1631 |
gen_fcond[3][cond]();
|
1632 |
gen_op_fmovs_cc(); |
1633 |
gen_op_store_FT0_fpr(rd); |
1634 |
break;
|
1635 |
case 0x0c2: /* V9 fmovdcc %fcc3 */ |
1636 |
cond = GET_FIELD_SP(insn, 14, 17); |
1637 |
gen_op_load_fpr_DT0(rd); |
1638 |
gen_op_load_fpr_DT1(rs2); |
1639 |
flush_T2(dc); |
1640 |
gen_fcond[3][cond]();
|
1641 |
gen_op_fmovd_cc(); |
1642 |
gen_op_store_DT0_fpr(rd); |
1643 |
break;
|
1644 |
case 0x0c3: /* V9 fmovqcc %fcc3 */ |
1645 |
goto nfpu_insn;
|
1646 |
case 0x101: /* V9 fmovscc %icc */ |
1647 |
cond = GET_FIELD_SP(insn, 14, 17); |
1648 |
gen_op_load_fpr_FT0(rd); |
1649 |
gen_op_load_fpr_FT1(rs2); |
1650 |
flush_T2(dc); |
1651 |
gen_cond[0][cond]();
|
1652 |
gen_op_fmovs_cc(); |
1653 |
gen_op_store_FT0_fpr(rd); |
1654 |
break;
|
1655 |
case 0x102: /* V9 fmovdcc %icc */ |
1656 |
cond = GET_FIELD_SP(insn, 14, 17); |
1657 |
gen_op_load_fpr_DT0(rd); |
1658 |
gen_op_load_fpr_DT1(rs2); |
1659 |
flush_T2(dc); |
1660 |
gen_cond[0][cond]();
|
1661 |
gen_op_fmovd_cc(); |
1662 |
gen_op_store_DT0_fpr(rd); |
1663 |
break;
|
1664 |
case 0x103: /* V9 fmovqcc %icc */ |
1665 |
goto nfpu_insn;
|
1666 |
case 0x181: /* V9 fmovscc %xcc */ |
1667 |
cond = GET_FIELD_SP(insn, 14, 17); |
1668 |
gen_op_load_fpr_FT0(rd); |
1669 |
gen_op_load_fpr_FT1(rs2); |
1670 |
flush_T2(dc); |
1671 |
gen_cond[1][cond]();
|
1672 |
gen_op_fmovs_cc(); |
1673 |
gen_op_store_FT0_fpr(rd); |
1674 |
break;
|
1675 |
case 0x182: /* V9 fmovdcc %xcc */ |
1676 |
cond = GET_FIELD_SP(insn, 14, 17); |
1677 |
gen_op_load_fpr_DT0(rd); |
1678 |
gen_op_load_fpr_DT1(rs2); |
1679 |
flush_T2(dc); |
1680 |
gen_cond[1][cond]();
|
1681 |
gen_op_fmovd_cc(); |
1682 |
gen_op_store_DT0_fpr(rd); |
1683 |
break;
|
1684 |
case 0x183: /* V9 fmovqcc %xcc */ |
1685 |
goto nfpu_insn;
|
1686 |
#endif
|
1687 |
case 0x51: /* V9 %fcc */ |
1688 |
gen_op_load_fpr_FT0(rs1); |
1689 |
gen_op_load_fpr_FT1(rs2); |
1690 |
#ifdef TARGET_SPARC64
|
1691 |
gen_fcmps[rd & 3]();
|
1692 |
#else
|
1693 |
gen_op_fcmps(); |
1694 |
#endif
|
1695 |
break;
|
1696 |
case 0x52: /* V9 %fcc */ |
1697 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
1698 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
1699 |
#ifdef TARGET_SPARC64
|
1700 |
gen_fcmpd[rd & 3]();
|
1701 |
#else
|
1702 |
gen_op_fcmpd(); |
1703 |
#endif
|
1704 |
break;
|
1705 |
case 0x53: /* fcmpq */ |
1706 |
goto nfpu_insn;
|
1707 |
case 0x55: /* fcmpes, V9 %fcc */ |
1708 |
gen_op_load_fpr_FT0(rs1); |
1709 |
gen_op_load_fpr_FT1(rs2); |
1710 |
#ifdef TARGET_SPARC64
|
1711 |
gen_fcmpes[rd & 3]();
|
1712 |
#else
|
1713 |
gen_op_fcmpes(); |
1714 |
#endif
|
1715 |
break;
|
1716 |
case 0x56: /* fcmped, V9 %fcc */ |
1717 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
1718 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
1719 |
#ifdef TARGET_SPARC64
|
1720 |
gen_fcmped[rd & 3]();
|
1721 |
#else
|
1722 |
gen_op_fcmped(); |
1723 |
#endif
|
1724 |
break;
|
1725 |
case 0x57: /* fcmpeq */ |
1726 |
goto nfpu_insn;
|
1727 |
default:
|
1728 |
goto illegal_insn;
|
1729 |
} |
1730 |
#if defined(OPTIM)
|
1731 |
} else if (xop == 0x2) { |
1732 |
// clr/mov shortcut
|
1733 |
|
1734 |
rs1 = GET_FIELD(insn, 13, 17); |
1735 |
if (rs1 == 0) { |
1736 |
// or %g0, x, y -> mov T1, x; mov y, T1
|
1737 |
if (IS_IMM) { /* immediate */ |
1738 |
rs2 = GET_FIELDs(insn, 19, 31); |
1739 |
gen_movl_simm_T1(rs2); |
1740 |
} else { /* register */ |
1741 |
rs2 = GET_FIELD(insn, 27, 31); |
1742 |
gen_movl_reg_T1(rs2); |
1743 |
} |
1744 |
gen_movl_T1_reg(rd); |
1745 |
} else {
|
1746 |
gen_movl_reg_T0(rs1); |
1747 |
if (IS_IMM) { /* immediate */ |
1748 |
// or x, #0, y -> mov T1, x; mov y, T1
|
1749 |
rs2 = GET_FIELDs(insn, 19, 31); |
1750 |
if (rs2 != 0) { |
1751 |
gen_movl_simm_T1(rs2); |
1752 |
gen_op_or_T1_T0(); |
1753 |
} |
1754 |
} else { /* register */ |
1755 |
// or x, %g0, y -> mov T1, x; mov y, T1
|
1756 |
rs2 = GET_FIELD(insn, 27, 31); |
1757 |
if (rs2 != 0) { |
1758 |
gen_movl_reg_T1(rs2); |
1759 |
gen_op_or_T1_T0(); |
1760 |
} |
1761 |
} |
1762 |
gen_movl_T0_reg(rd); |
1763 |
} |
1764 |
#endif
|
1765 |
#ifdef TARGET_SPARC64
|
1766 |
} else if (xop == 0x25) { /* sll, V9 sllx */ |
1767 |
rs1 = GET_FIELD(insn, 13, 17); |
1768 |
gen_movl_reg_T0(rs1); |
1769 |
if (IS_IMM) { /* immediate */ |
1770 |
rs2 = GET_FIELDs(insn, 20, 31); |
1771 |
gen_movl_simm_T1(rs2); |
1772 |
} else { /* register */ |
1773 |
rs2 = GET_FIELD(insn, 27, 31); |
1774 |
gen_movl_reg_T1(rs2); |
1775 |
} |
1776 |
if (insn & (1 << 12)) |
1777 |
gen_op_sllx(); |
1778 |
else
|
1779 |
gen_op_sll(); |
1780 |
gen_movl_T0_reg(rd); |
1781 |
} else if (xop == 0x26) { /* srl, V9 srlx */ |
1782 |
rs1 = GET_FIELD(insn, 13, 17); |
1783 |
gen_movl_reg_T0(rs1); |
1784 |
if (IS_IMM) { /* immediate */ |
1785 |
rs2 = GET_FIELDs(insn, 20, 31); |
1786 |
gen_movl_simm_T1(rs2); |
1787 |
} else { /* register */ |
1788 |
rs2 = GET_FIELD(insn, 27, 31); |
1789 |
gen_movl_reg_T1(rs2); |
1790 |
} |
1791 |
if (insn & (1 << 12)) |
1792 |
gen_op_srlx(); |
1793 |
else
|
1794 |
gen_op_srl(); |
1795 |
gen_movl_T0_reg(rd); |
1796 |
} else if (xop == 0x27) { /* sra, V9 srax */ |
1797 |
rs1 = GET_FIELD(insn, 13, 17); |
1798 |
gen_movl_reg_T0(rs1); |
1799 |
if (IS_IMM) { /* immediate */ |
1800 |
rs2 = GET_FIELDs(insn, 20, 31); |
1801 |
gen_movl_simm_T1(rs2); |
1802 |
} else { /* register */ |
1803 |
rs2 = GET_FIELD(insn, 27, 31); |
1804 |
gen_movl_reg_T1(rs2); |
1805 |
} |
1806 |
if (insn & (1 << 12)) |
1807 |
gen_op_srax(); |
1808 |
else
|
1809 |
gen_op_sra(); |
1810 |
gen_movl_T0_reg(rd); |
1811 |
#endif
|
1812 |
} else if (xop < 0x36) { |
1813 |
rs1 = GET_FIELD(insn, 13, 17); |
1814 |
gen_movl_reg_T0(rs1); |
1815 |
if (IS_IMM) { /* immediate */ |
1816 |
rs2 = GET_FIELDs(insn, 19, 31); |
1817 |
gen_movl_simm_T1(rs2); |
1818 |
} else { /* register */ |
1819 |
rs2 = GET_FIELD(insn, 27, 31); |
1820 |
gen_movl_reg_T1(rs2); |
1821 |
} |
1822 |
if (xop < 0x20) { |
1823 |
switch (xop & ~0x10) { |
1824 |
case 0x0: |
1825 |
if (xop & 0x10) |
1826 |
gen_op_add_T1_T0_cc(); |
1827 |
else
|
1828 |
gen_op_add_T1_T0(); |
1829 |
break;
|
1830 |
case 0x1: |
1831 |
gen_op_and_T1_T0(); |
1832 |
if (xop & 0x10) |
1833 |
gen_op_logic_T0_cc(); |
1834 |
break;
|
1835 |
case 0x2: |
1836 |
gen_op_or_T1_T0(); |
1837 |
if (xop & 0x10) |
1838 |
gen_op_logic_T0_cc(); |
1839 |
break;
|
1840 |
case 0x3: |
1841 |
gen_op_xor_T1_T0(); |
1842 |
if (xop & 0x10) |
1843 |
gen_op_logic_T0_cc(); |
1844 |
break;
|
1845 |
case 0x4: |
1846 |
if (xop & 0x10) |
1847 |
gen_op_sub_T1_T0_cc(); |
1848 |
else
|
1849 |
gen_op_sub_T1_T0(); |
1850 |
break;
|
1851 |
case 0x5: |
1852 |
gen_op_andn_T1_T0(); |
1853 |
if (xop & 0x10) |
1854 |
gen_op_logic_T0_cc(); |
1855 |
break;
|
1856 |
case 0x6: |
1857 |
gen_op_orn_T1_T0(); |
1858 |
if (xop & 0x10) |
1859 |
gen_op_logic_T0_cc(); |
1860 |
break;
|
1861 |
case 0x7: |
1862 |
gen_op_xnor_T1_T0(); |
1863 |
if (xop & 0x10) |
1864 |
gen_op_logic_T0_cc(); |
1865 |
break;
|
1866 |
case 0x8: |
1867 |
if (xop & 0x10) |
1868 |
gen_op_addx_T1_T0_cc(); |
1869 |
else
|
1870 |
gen_op_addx_T1_T0(); |
1871 |
break;
|
1872 |
#ifdef TARGET_SPARC64
|
1873 |
case 0x9: /* V9 mulx */ |
1874 |
gen_op_mulx_T1_T0(); |
1875 |
break;
|
1876 |
#endif
|
1877 |
case 0xa: |
1878 |
gen_op_umul_T1_T0(); |
1879 |
if (xop & 0x10) |
1880 |
gen_op_logic_T0_cc(); |
1881 |
break;
|
1882 |
case 0xb: |
1883 |
gen_op_smul_T1_T0(); |
1884 |
if (xop & 0x10) |
1885 |
gen_op_logic_T0_cc(); |
1886 |
break;
|
1887 |
case 0xc: |
1888 |
if (xop & 0x10) |
1889 |
gen_op_subx_T1_T0_cc(); |
1890 |
else
|
1891 |
gen_op_subx_T1_T0(); |
1892 |
break;
|
1893 |
#ifdef TARGET_SPARC64
|
1894 |
case 0xd: /* V9 udivx */ |
1895 |
gen_op_udivx_T1_T0(); |
1896 |
break;
|
1897 |
#endif
|
1898 |
case 0xe: |
1899 |
gen_op_udiv_T1_T0(); |
1900 |
if (xop & 0x10) |
1901 |
gen_op_div_cc(); |
1902 |
break;
|
1903 |
case 0xf: |
1904 |
gen_op_sdiv_T1_T0(); |
1905 |
if (xop & 0x10) |
1906 |
gen_op_div_cc(); |
1907 |
break;
|
1908 |
default:
|
1909 |
goto illegal_insn;
|
1910 |
} |
1911 |
gen_movl_T0_reg(rd); |
1912 |
} else {
|
1913 |
switch (xop) {
|
1914 |
case 0x20: /* taddcc */ |
1915 |
gen_op_tadd_T1_T0_cc(); |
1916 |
gen_movl_T0_reg(rd); |
1917 |
break;
|
1918 |
case 0x21: /* tsubcc */ |
1919 |
gen_op_tsub_T1_T0_cc(); |
1920 |
gen_movl_T0_reg(rd); |
1921 |
break;
|
1922 |
case 0x22: /* taddcctv */ |
1923 |
gen_op_tadd_T1_T0_ccTV(); |
1924 |
gen_movl_T0_reg(rd); |
1925 |
break;
|
1926 |
case 0x23: /* tsubcctv */ |
1927 |
gen_op_tsub_T1_T0_ccTV(); |
1928 |
gen_movl_T0_reg(rd); |
1929 |
break;
|
1930 |
case 0x24: /* mulscc */ |
1931 |
gen_op_mulscc_T1_T0(); |
1932 |
gen_movl_T0_reg(rd); |
1933 |
break;
|
1934 |
#ifndef TARGET_SPARC64
|
1935 |
case 0x25: /* sll */ |
1936 |
gen_op_sll(); |
1937 |
gen_movl_T0_reg(rd); |
1938 |
break;
|
1939 |
case 0x26: /* srl */ |
1940 |
gen_op_srl(); |
1941 |
gen_movl_T0_reg(rd); |
1942 |
break;
|
1943 |
case 0x27: /* sra */ |
1944 |
gen_op_sra(); |
1945 |
gen_movl_T0_reg(rd); |
1946 |
break;
|
1947 |
#endif
|
1948 |
case 0x30: |
1949 |
{ |
1950 |
switch(rd) {
|
1951 |
case 0: /* wry */ |
1952 |
gen_op_xor_T1_T0(); |
1953 |
gen_op_movtl_env_T0(offsetof(CPUSPARCState, y)); |
1954 |
break;
|
1955 |
#ifndef TARGET_SPARC64
|
1956 |
case 0x01 ... 0x0f: /* undefined in the |
1957 |
SPARCv8 manual, nop
|
1958 |
on the microSPARC
|
1959 |
II */
|
1960 |
case 0x10 ... 0x1f: /* implementation-dependent |
1961 |
in the SPARCv8
|
1962 |
manual, nop on the
|
1963 |
microSPARC II */
|
1964 |
break;
|
1965 |
#else
|
1966 |
case 0x2: /* V9 wrccr */ |
1967 |
gen_op_wrccr(); |
1968 |
break;
|
1969 |
case 0x3: /* V9 wrasi */ |
1970 |
gen_op_movl_env_T0(offsetof(CPUSPARCState, asi)); |
1971 |
break;
|
1972 |
case 0x6: /* V9 wrfprs */ |
1973 |
gen_op_xor_T1_T0(); |
1974 |
gen_op_movl_env_T0(offsetof(CPUSPARCState, fprs)); |
1975 |
save_state(dc); |
1976 |
gen_op_next_insn(); |
1977 |
gen_op_movl_T0_0(); |
1978 |
gen_op_exit_tb(); |
1979 |
dc->is_br = 1;
|
1980 |
break;
|
1981 |
case 0xf: /* V9 sir, nop if user */ |
1982 |
#if !defined(CONFIG_USER_ONLY)
|
1983 |
if (supervisor(dc))
|
1984 |
gen_op_sir(); |
1985 |
#endif
|
1986 |
break;
|
1987 |
case 0x13: /* Graphics Status */ |
1988 |
if (gen_trap_ifnofpu(dc))
|
1989 |
goto jmp_insn;
|
1990 |
gen_op_movtl_env_T0(offsetof(CPUSPARCState, gsr)); |
1991 |
break;
|
1992 |
case 0x17: /* Tick compare */ |
1993 |
#if !defined(CONFIG_USER_ONLY)
|
1994 |
if (!supervisor(dc))
|
1995 |
goto illegal_insn;
|
1996 |
#endif
|
1997 |
gen_op_movtl_env_T0(offsetof(CPUSPARCState, tick_cmpr)); |
1998 |
gen_op_wrtick_cmpr(); |
1999 |
break;
|
2000 |
case 0x18: /* System tick */ |
2001 |
#if !defined(CONFIG_USER_ONLY)
|
2002 |
if (!supervisor(dc))
|
2003 |
goto illegal_insn;
|
2004 |
#endif
|
2005 |
gen_op_wrstick(); |
2006 |
break;
|
2007 |
case 0x19: /* System tick compare */ |
2008 |
#if !defined(CONFIG_USER_ONLY)
|
2009 |
if (!supervisor(dc))
|
2010 |
goto illegal_insn;
|
2011 |
#endif
|
2012 |
gen_op_movtl_env_T0(offsetof(CPUSPARCState, stick_cmpr)); |
2013 |
gen_op_wrstick_cmpr(); |
2014 |
break;
|
2015 |
|
2016 |
case 0x10: /* Performance Control */ |
2017 |
case 0x11: /* Performance Instrumentation Counter */ |
2018 |
case 0x12: /* Dispatch Control */ |
2019 |
case 0x14: /* Softint set */ |
2020 |
case 0x15: /* Softint clear */ |
2021 |
case 0x16: /* Softint write */ |
2022 |
#endif
|
2023 |
default:
|
2024 |
goto illegal_insn;
|
2025 |
} |
2026 |
} |
2027 |
break;
|
2028 |
#if !defined(CONFIG_USER_ONLY)
|
2029 |
case 0x31: /* wrpsr, V9 saved, restored */ |
2030 |
{ |
2031 |
if (!supervisor(dc))
|
2032 |
goto priv_insn;
|
2033 |
#ifdef TARGET_SPARC64
|
2034 |
switch (rd) {
|
2035 |
case 0: |
2036 |
gen_op_saved(); |
2037 |
break;
|
2038 |
case 1: |
2039 |
gen_op_restored(); |
2040 |
break;
|
2041 |
case 2: /* UA2005 allclean */ |
2042 |
case 3: /* UA2005 otherw */ |
2043 |
case 4: /* UA2005 normalw */ |
2044 |
case 5: /* UA2005 invalw */ |
2045 |
// XXX
|
2046 |
default:
|
2047 |
goto illegal_insn;
|
2048 |
} |
2049 |
#else
|
2050 |
gen_op_xor_T1_T0(); |
2051 |
gen_op_wrpsr(); |
2052 |
save_state(dc); |
2053 |
gen_op_next_insn(); |
2054 |
gen_op_movl_T0_0(); |
2055 |
gen_op_exit_tb(); |
2056 |
dc->is_br = 1;
|
2057 |
#endif
|
2058 |
} |
2059 |
break;
|
2060 |
case 0x32: /* wrwim, V9 wrpr */ |
2061 |
{ |
2062 |
if (!supervisor(dc))
|
2063 |
goto priv_insn;
|
2064 |
gen_op_xor_T1_T0(); |
2065 |
#ifdef TARGET_SPARC64
|
2066 |
switch (rd) {
|
2067 |
case 0: // tpc |
2068 |
gen_op_wrtpc(); |
2069 |
break;
|
2070 |
case 1: // tnpc |
2071 |
gen_op_wrtnpc(); |
2072 |
break;
|
2073 |
case 2: // tstate |
2074 |
gen_op_wrtstate(); |
2075 |
break;
|
2076 |
case 3: // tt |
2077 |
gen_op_wrtt(); |
2078 |
break;
|
2079 |
case 4: // tick |
2080 |
gen_op_wrtick(); |
2081 |
break;
|
2082 |
case 5: // tba |
2083 |
gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr)); |
2084 |
break;
|
2085 |
case 6: // pstate |
2086 |
gen_op_wrpstate(); |
2087 |
save_state(dc); |
2088 |
gen_op_next_insn(); |
2089 |
gen_op_movl_T0_0(); |
2090 |
gen_op_exit_tb(); |
2091 |
dc->is_br = 1;
|
2092 |
break;
|
2093 |
case 7: // tl |
2094 |
gen_op_movl_env_T0(offsetof(CPUSPARCState, tl)); |
2095 |
break;
|
2096 |
case 8: // pil |
2097 |
gen_op_movl_env_T0(offsetof(CPUSPARCState, psrpil)); |
2098 |
break;
|
2099 |
case 9: // cwp |
2100 |
gen_op_wrcwp(); |
2101 |
break;
|
2102 |
case 10: // cansave |
2103 |
gen_op_movl_env_T0(offsetof(CPUSPARCState, cansave)); |
2104 |
break;
|
2105 |
case 11: // canrestore |
2106 |
gen_op_movl_env_T0(offsetof(CPUSPARCState, canrestore)); |
2107 |
break;
|
2108 |
case 12: // cleanwin |
2109 |
gen_op_movl_env_T0(offsetof(CPUSPARCState, cleanwin)); |
2110 |
break;
|
2111 |
case 13: // otherwin |
2112 |
gen_op_movl_env_T0(offsetof(CPUSPARCState, otherwin)); |
2113 |
break;
|
2114 |
case 14: // wstate |
2115 |
gen_op_movl_env_T0(offsetof(CPUSPARCState, wstate)); |
2116 |
break;
|
2117 |
case 16: // UA2005 gl |
2118 |
gen_op_movl_env_T0(offsetof(CPUSPARCState, gl)); |
2119 |
break;
|
2120 |
case 26: // UA2005 strand status |
2121 |
if (!hypervisor(dc))
|
2122 |
goto priv_insn;
|
2123 |
gen_op_movl_env_T0(offsetof(CPUSPARCState, ssr)); |
2124 |
break;
|
2125 |
default:
|
2126 |
goto illegal_insn;
|
2127 |
} |
2128 |
#else
|
2129 |
gen_op_wrwim(); |
2130 |
#endif
|
2131 |
} |
2132 |
break;
|
2133 |
case 0x33: /* wrtbr, UA2005 wrhpr */ |
2134 |
{ |
2135 |
#ifndef TARGET_SPARC64
|
2136 |
if (!supervisor(dc))
|
2137 |
goto priv_insn;
|
2138 |
gen_op_xor_T1_T0(); |
2139 |
gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr)); |
2140 |
#else
|
2141 |
if (!hypervisor(dc))
|
2142 |
goto priv_insn;
|
2143 |
gen_op_xor_T1_T0(); |
2144 |
switch (rd) {
|
2145 |
case 0: // hpstate |
2146 |
// XXX gen_op_wrhpstate();
|
2147 |
save_state(dc); |
2148 |
gen_op_next_insn(); |
2149 |
gen_op_movl_T0_0(); |
2150 |
gen_op_exit_tb(); |
2151 |
dc->is_br = 1;
|
2152 |
break;
|
2153 |
case 1: // htstate |
2154 |
// XXX gen_op_wrhtstate();
|
2155 |
break;
|
2156 |
case 3: // hintp |
2157 |
gen_op_movl_env_T0(offsetof(CPUSPARCState, hintp)); |
2158 |
break;
|
2159 |
case 5: // htba |
2160 |
gen_op_movl_env_T0(offsetof(CPUSPARCState, htba)); |
2161 |
break;
|
2162 |
case 31: // hstick_cmpr |
2163 |
gen_op_movtl_env_T0(offsetof(CPUSPARCState, hstick_cmpr)); |
2164 |
gen_op_wrhstick_cmpr(); |
2165 |
break;
|
2166 |
case 6: // hver readonly |
2167 |
default:
|
2168 |
goto illegal_insn;
|
2169 |
} |
2170 |
#endif
|
2171 |
} |
2172 |
break;
|
2173 |
#endif
|
2174 |
#ifdef TARGET_SPARC64
|
2175 |
case 0x2c: /* V9 movcc */ |
2176 |
{ |
2177 |
int cc = GET_FIELD_SP(insn, 11, 12); |
2178 |
int cond = GET_FIELD_SP(insn, 14, 17); |
2179 |
if (IS_IMM) { /* immediate */ |
2180 |
rs2 = GET_FIELD_SPs(insn, 0, 10); |
2181 |
gen_movl_simm_T1(rs2); |
2182 |
} |
2183 |
else {
|
2184 |
rs2 = GET_FIELD_SP(insn, 0, 4); |
2185 |
gen_movl_reg_T1(rs2); |
2186 |
} |
2187 |
gen_movl_reg_T0(rd); |
2188 |
flush_T2(dc); |
2189 |
if (insn & (1 << 18)) { |
2190 |
if (cc == 0) |
2191 |
gen_cond[0][cond]();
|
2192 |
else if (cc == 2) |
2193 |
gen_cond[1][cond]();
|
2194 |
else
|
2195 |
goto illegal_insn;
|
2196 |
} else {
|
2197 |
gen_fcond[cc][cond](); |
2198 |
} |
2199 |
gen_op_mov_cc(); |
2200 |
gen_movl_T0_reg(rd); |
2201 |
break;
|
2202 |
} |
2203 |
case 0x2d: /* V9 sdivx */ |
2204 |
gen_op_sdivx_T1_T0(); |
2205 |
gen_movl_T0_reg(rd); |
2206 |
break;
|
2207 |
case 0x2e: /* V9 popc */ |
2208 |
{ |
2209 |
if (IS_IMM) { /* immediate */ |
2210 |
rs2 = GET_FIELD_SPs(insn, 0, 12); |
2211 |
gen_movl_simm_T1(rs2); |
2212 |
// XXX optimize: popc(constant)
|
2213 |
} |
2214 |
else {
|
2215 |
rs2 = GET_FIELD_SP(insn, 0, 4); |
2216 |
gen_movl_reg_T1(rs2); |
2217 |
} |
2218 |
gen_op_popc(); |
2219 |
gen_movl_T0_reg(rd); |
2220 |
} |
2221 |
case 0x2f: /* V9 movr */ |
2222 |
{ |
2223 |
int cond = GET_FIELD_SP(insn, 10, 12); |
2224 |
rs1 = GET_FIELD(insn, 13, 17); |
2225 |
flush_T2(dc); |
2226 |
gen_movl_reg_T0(rs1); |
2227 |
gen_cond_reg(cond); |
2228 |
if (IS_IMM) { /* immediate */ |
2229 |
rs2 = GET_FIELD_SPs(insn, 0, 9); |
2230 |
gen_movl_simm_T1(rs2); |
2231 |
} |
2232 |
else {
|
2233 |
rs2 = GET_FIELD_SP(insn, 0, 4); |
2234 |
gen_movl_reg_T1(rs2); |
2235 |
} |
2236 |
gen_movl_reg_T0(rd); |
2237 |
gen_op_mov_cc(); |
2238 |
gen_movl_T0_reg(rd); |
2239 |
break;
|
2240 |
} |
2241 |
#endif
|
2242 |
default:
|
2243 |
goto illegal_insn;
|
2244 |
} |
2245 |
} |
2246 |
} else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */ |
2247 |
#ifdef TARGET_SPARC64
|
2248 |
int opf = GET_FIELD_SP(insn, 5, 13); |
2249 |
rs1 = GET_FIELD(insn, 13, 17); |
2250 |
rs2 = GET_FIELD(insn, 27, 31); |
2251 |
if (gen_trap_ifnofpu(dc))
|
2252 |
goto jmp_insn;
|
2253 |
|
2254 |
switch (opf) {
|
2255 |
case 0x000: /* VIS I edge8cc */ |
2256 |
case 0x001: /* VIS II edge8n */ |
2257 |
case 0x002: /* VIS I edge8lcc */ |
2258 |
case 0x003: /* VIS II edge8ln */ |
2259 |
case 0x004: /* VIS I edge16cc */ |
2260 |
case 0x005: /* VIS II edge16n */ |
2261 |
case 0x006: /* VIS I edge16lcc */ |
2262 |
case 0x007: /* VIS II edge16ln */ |
2263 |
case 0x008: /* VIS I edge32cc */ |
2264 |
case 0x009: /* VIS II edge32n */ |
2265 |
case 0x00a: /* VIS I edge32lcc */ |
2266 |
case 0x00b: /* VIS II edge32ln */ |
2267 |
// XXX
|
2268 |
goto illegal_insn;
|
2269 |
case 0x010: /* VIS I array8 */ |
2270 |
gen_movl_reg_T0(rs1); |
2271 |
gen_movl_reg_T1(rs2); |
2272 |
gen_op_array8(); |
2273 |
gen_movl_T0_reg(rd); |
2274 |
break;
|
2275 |
case 0x012: /* VIS I array16 */ |
2276 |
gen_movl_reg_T0(rs1); |
2277 |
gen_movl_reg_T1(rs2); |
2278 |
gen_op_array16(); |
2279 |
gen_movl_T0_reg(rd); |
2280 |
break;
|
2281 |
case 0x014: /* VIS I array32 */ |
2282 |
gen_movl_reg_T0(rs1); |
2283 |
gen_movl_reg_T1(rs2); |
2284 |
gen_op_array32(); |
2285 |
gen_movl_T0_reg(rd); |
2286 |
break;
|
2287 |
case 0x018: /* VIS I alignaddr */ |
2288 |
gen_movl_reg_T0(rs1); |
2289 |
gen_movl_reg_T1(rs2); |
2290 |
gen_op_alignaddr(); |
2291 |
gen_movl_T0_reg(rd); |
2292 |
break;
|
2293 |
case 0x019: /* VIS II bmask */ |
2294 |
case 0x01a: /* VIS I alignaddrl */ |
2295 |
// XXX
|
2296 |
goto illegal_insn;
|
2297 |
case 0x020: /* VIS I fcmple16 */ |
2298 |
gen_op_load_fpr_DT0(rs1); |
2299 |
gen_op_load_fpr_DT1(rs2); |
2300 |
gen_op_fcmple16(); |
2301 |
gen_op_store_DT0_fpr(rd); |
2302 |
break;
|
2303 |
case 0x022: /* VIS I fcmpne16 */ |
2304 |
gen_op_load_fpr_DT0(rs1); |
2305 |
gen_op_load_fpr_DT1(rs2); |
2306 |
gen_op_fcmpne16(); |
2307 |
gen_op_store_DT0_fpr(rd); |
2308 |
break;
|
2309 |
case 0x024: /* VIS I fcmple32 */ |
2310 |
gen_op_load_fpr_DT0(rs1); |
2311 |
gen_op_load_fpr_DT1(rs2); |
2312 |
gen_op_fcmple32(); |
2313 |
gen_op_store_DT0_fpr(rd); |
2314 |
break;
|
2315 |
case 0x026: /* VIS I fcmpne32 */ |
2316 |
gen_op_load_fpr_DT0(rs1); |
2317 |
gen_op_load_fpr_DT1(rs2); |
2318 |
gen_op_fcmpne32(); |
2319 |
gen_op_store_DT0_fpr(rd); |
2320 |
break;
|
2321 |
case 0x028: /* VIS I fcmpgt16 */ |
2322 |
gen_op_load_fpr_DT0(rs1); |
2323 |
gen_op_load_fpr_DT1(rs2); |
2324 |
gen_op_fcmpgt16(); |
2325 |
gen_op_store_DT0_fpr(rd); |
2326 |
break;
|
2327 |
case 0x02a: /* VIS I fcmpeq16 */ |
2328 |
gen_op_load_fpr_DT0(rs1); |
2329 |
gen_op_load_fpr_DT1(rs2); |
2330 |
gen_op_fcmpeq16(); |
2331 |
gen_op_store_DT0_fpr(rd); |
2332 |
break;
|
2333 |
case 0x02c: /* VIS I fcmpgt32 */ |
2334 |
gen_op_load_fpr_DT0(rs1); |
2335 |
gen_op_load_fpr_DT1(rs2); |
2336 |
gen_op_fcmpgt32(); |
2337 |
gen_op_store_DT0_fpr(rd); |
2338 |
break;
|
2339 |
case 0x02e: /* VIS I fcmpeq32 */ |
2340 |
gen_op_load_fpr_DT0(rs1); |
2341 |
gen_op_load_fpr_DT1(rs2); |
2342 |
gen_op_fcmpeq32(); |
2343 |
gen_op_store_DT0_fpr(rd); |
2344 |
break;
|
2345 |
case 0x031: /* VIS I fmul8x16 */ |
2346 |
gen_op_load_fpr_DT0(rs1); |
2347 |
gen_op_load_fpr_DT1(rs2); |
2348 |
gen_op_fmul8x16(); |
2349 |
gen_op_store_DT0_fpr(rd); |
2350 |
break;
|
2351 |
case 0x033: /* VIS I fmul8x16au */ |
2352 |
gen_op_load_fpr_DT0(rs1); |
2353 |
gen_op_load_fpr_DT1(rs2); |
2354 |
gen_op_fmul8x16au(); |
2355 |
gen_op_store_DT0_fpr(rd); |
2356 |
break;
|
2357 |
case 0x035: /* VIS I fmul8x16al */ |
2358 |
gen_op_load_fpr_DT0(rs1); |
2359 |
gen_op_load_fpr_DT1(rs2); |
2360 |
gen_op_fmul8x16al(); |
2361 |
gen_op_store_DT0_fpr(rd); |
2362 |
break;
|
2363 |
case 0x036: /* VIS I fmul8sux16 */ |
2364 |
gen_op_load_fpr_DT0(rs1); |
2365 |
gen_op_load_fpr_DT1(rs2); |
2366 |
gen_op_fmul8sux16(); |
2367 |
gen_op_store_DT0_fpr(rd); |
2368 |
break;
|
2369 |
case 0x037: /* VIS I fmul8ulx16 */ |
2370 |
gen_op_load_fpr_DT0(rs1); |
2371 |
gen_op_load_fpr_DT1(rs2); |
2372 |
gen_op_fmul8ulx16(); |
2373 |
gen_op_store_DT0_fpr(rd); |
2374 |
break;
|
2375 |
case 0x038: /* VIS I fmuld8sux16 */ |
2376 |
gen_op_load_fpr_DT0(rs1); |
2377 |
gen_op_load_fpr_DT1(rs2); |
2378 |
gen_op_fmuld8sux16(); |
2379 |
gen_op_store_DT0_fpr(rd); |
2380 |
break;
|
2381 |
case 0x039: /* VIS I fmuld8ulx16 */ |
2382 |
gen_op_load_fpr_DT0(rs1); |
2383 |
gen_op_load_fpr_DT1(rs2); |
2384 |
gen_op_fmuld8ulx16(); |
2385 |
gen_op_store_DT0_fpr(rd); |
2386 |
break;
|
2387 |
case 0x03a: /* VIS I fpack32 */ |
2388 |
case 0x03b: /* VIS I fpack16 */ |
2389 |
case 0x03d: /* VIS I fpackfix */ |
2390 |
case 0x03e: /* VIS I pdist */ |
2391 |
// XXX
|
2392 |
goto illegal_insn;
|
2393 |
case 0x048: /* VIS I faligndata */ |
2394 |
gen_op_load_fpr_DT0(rs1); |
2395 |
gen_op_load_fpr_DT1(rs2); |
2396 |
gen_op_faligndata(); |
2397 |
gen_op_store_DT0_fpr(rd); |
2398 |
break;
|
2399 |
case 0x04b: /* VIS I fpmerge */ |
2400 |
gen_op_load_fpr_DT0(rs1); |
2401 |
gen_op_load_fpr_DT1(rs2); |
2402 |
gen_op_fpmerge(); |
2403 |
gen_op_store_DT0_fpr(rd); |
2404 |
break;
|
2405 |
case 0x04c: /* VIS II bshuffle */ |
2406 |
// XXX
|
2407 |
goto illegal_insn;
|
2408 |
case 0x04d: /* VIS I fexpand */ |
2409 |
gen_op_load_fpr_DT0(rs1); |
2410 |
gen_op_load_fpr_DT1(rs2); |
2411 |
gen_op_fexpand(); |
2412 |
gen_op_store_DT0_fpr(rd); |
2413 |
break;
|
2414 |
case 0x050: /* VIS I fpadd16 */ |
2415 |
gen_op_load_fpr_DT0(rs1); |
2416 |
gen_op_load_fpr_DT1(rs2); |
2417 |
gen_op_fpadd16(); |
2418 |
gen_op_store_DT0_fpr(rd); |
2419 |
break;
|
2420 |
case 0x051: /* VIS I fpadd16s */ |
2421 |
gen_op_load_fpr_FT0(rs1); |
2422 |
gen_op_load_fpr_FT1(rs2); |
2423 |
gen_op_fpadd16s(); |
2424 |
gen_op_store_FT0_fpr(rd); |
2425 |
break;
|
2426 |
case 0x052: /* VIS I fpadd32 */ |
2427 |
gen_op_load_fpr_DT0(rs1); |
2428 |
gen_op_load_fpr_DT1(rs2); |
2429 |
gen_op_fpadd32(); |
2430 |
gen_op_store_DT0_fpr(rd); |
2431 |
break;
|
2432 |
case 0x053: /* VIS I fpadd32s */ |
2433 |
gen_op_load_fpr_FT0(rs1); |
2434 |
gen_op_load_fpr_FT1(rs2); |
2435 |
gen_op_fpadd32s(); |
2436 |
gen_op_store_FT0_fpr(rd); |
2437 |
break;
|
2438 |
case 0x054: /* VIS I fpsub16 */ |
2439 |
gen_op_load_fpr_DT0(rs1); |
2440 |
gen_op_load_fpr_DT1(rs2); |
2441 |
gen_op_fpsub16(); |
2442 |
gen_op_store_DT0_fpr(rd); |
2443 |
break;
|
2444 |
case 0x055: /* VIS I fpsub16s */ |
2445 |
gen_op_load_fpr_FT0(rs1); |
2446 |
gen_op_load_fpr_FT1(rs2); |
2447 |
gen_op_fpsub16s(); |
2448 |
gen_op_store_FT0_fpr(rd); |
2449 |
break;
|
2450 |
case 0x056: /* VIS I fpsub32 */ |
2451 |
gen_op_load_fpr_DT0(rs1); |
2452 |
gen_op_load_fpr_DT1(rs2); |
2453 |
gen_op_fpadd32(); |
2454 |
gen_op_store_DT0_fpr(rd); |
2455 |
break;
|
2456 |
case 0x057: /* VIS I fpsub32s */ |
2457 |
gen_op_load_fpr_FT0(rs1); |
2458 |
gen_op_load_fpr_FT1(rs2); |
2459 |
gen_op_fpsub32s(); |
2460 |
gen_op_store_FT0_fpr(rd); |
2461 |
break;
|
2462 |
case 0x060: /* VIS I fzero */ |
2463 |
gen_op_movl_DT0_0(); |
2464 |
gen_op_store_DT0_fpr(rd); |
2465 |
break;
|
2466 |
case 0x061: /* VIS I fzeros */ |
2467 |
gen_op_movl_FT0_0(); |
2468 |
gen_op_store_FT0_fpr(rd); |
2469 |
break;
|
2470 |
case 0x062: /* VIS I fnor */ |
2471 |
gen_op_load_fpr_DT0(rs1); |
2472 |
gen_op_load_fpr_DT1(rs2); |
2473 |
gen_op_fnor(); |
2474 |
gen_op_store_DT0_fpr(rd); |
2475 |
break;
|
2476 |
case 0x063: /* VIS I fnors */ |
2477 |
gen_op_load_fpr_FT0(rs1); |
2478 |
gen_op_load_fpr_FT1(rs2); |
2479 |
gen_op_fnors(); |
2480 |
gen_op_store_FT0_fpr(rd); |
2481 |
break;
|
2482 |
case 0x064: /* VIS I fandnot2 */ |
2483 |
gen_op_load_fpr_DT1(rs1); |
2484 |
gen_op_load_fpr_DT0(rs2); |
2485 |
gen_op_fandnot(); |
2486 |
gen_op_store_DT0_fpr(rd); |
2487 |
break;
|
2488 |
case 0x065: /* VIS I fandnot2s */ |
2489 |
gen_op_load_fpr_FT1(rs1); |
2490 |
gen_op_load_fpr_FT0(rs2); |
2491 |
gen_op_fandnots(); |
2492 |
gen_op_store_FT0_fpr(rd); |
2493 |
break;
|
2494 |
case 0x066: /* VIS I fnot2 */ |
2495 |
gen_op_load_fpr_DT1(rs2); |
2496 |
gen_op_fnot(); |
2497 |
gen_op_store_DT0_fpr(rd); |
2498 |
break;
|
2499 |
case 0x067: /* VIS I fnot2s */ |
2500 |
gen_op_load_fpr_FT1(rs2); |
2501 |
gen_op_fnot(); |
2502 |
gen_op_store_FT0_fpr(rd); |
2503 |
break;
|
2504 |
case 0x068: /* VIS I fandnot1 */ |
2505 |
gen_op_load_fpr_DT0(rs1); |
2506 |
gen_op_load_fpr_DT1(rs2); |
2507 |
gen_op_fandnot(); |
2508 |
gen_op_store_DT0_fpr(rd); |
2509 |
break;
|
2510 |
case 0x069: /* VIS I fandnot1s */ |
2511 |
gen_op_load_fpr_FT0(rs1); |
2512 |
gen_op_load_fpr_FT1(rs2); |
2513 |
gen_op_fandnots(); |
2514 |
gen_op_store_FT0_fpr(rd); |
2515 |
break;
|
2516 |
case 0x06a: /* VIS I fnot1 */ |
2517 |
gen_op_load_fpr_DT1(rs1); |
2518 |
gen_op_fnot(); |
2519 |
gen_op_store_DT0_fpr(rd); |
2520 |
break;
|
2521 |
case 0x06b: /* VIS I fnot1s */ |
2522 |
gen_op_load_fpr_FT1(rs1); |
2523 |
gen_op_fnot(); |
2524 |
gen_op_store_FT0_fpr(rd); |
2525 |
break;
|
2526 |
case 0x06c: /* VIS I fxor */ |
2527 |
gen_op_load_fpr_DT0(rs1); |
2528 |
gen_op_load_fpr_DT1(rs2); |
2529 |
gen_op_fxor(); |
2530 |
gen_op_store_DT0_fpr(rd); |
2531 |
break;
|
2532 |
case 0x06d: /* VIS I fxors */ |
2533 |
gen_op_load_fpr_FT0(rs1); |
2534 |
gen_op_load_fpr_FT1(rs2); |
2535 |
gen_op_fxors(); |
2536 |
gen_op_store_FT0_fpr(rd); |
2537 |
break;
|
2538 |
case 0x06e: /* VIS I fnand */ |
2539 |
gen_op_load_fpr_DT0(rs1); |
2540 |
gen_op_load_fpr_DT1(rs2); |
2541 |
gen_op_fnand(); |
2542 |
gen_op_store_DT0_fpr(rd); |
2543 |
break;
|
2544 |
case 0x06f: /* VIS I fnands */ |
2545 |
gen_op_load_fpr_FT0(rs1); |
2546 |
gen_op_load_fpr_FT1(rs2); |
2547 |
gen_op_fnands(); |
2548 |
gen_op_store_FT0_fpr(rd); |
2549 |
break;
|
2550 |
case 0x070: /* VIS I fand */ |
2551 |
gen_op_load_fpr_DT0(rs1); |
2552 |
gen_op_load_fpr_DT1(rs2); |
2553 |
gen_op_fand(); |
2554 |
gen_op_store_DT0_fpr(rd); |
2555 |
break;
|
2556 |
case 0x071: /* VIS I fands */ |
2557 |
gen_op_load_fpr_FT0(rs1); |
2558 |
gen_op_load_fpr_FT1(rs2); |
2559 |
gen_op_fands(); |
2560 |
gen_op_store_FT0_fpr(rd); |
2561 |
break;
|
2562 |
case 0x072: /* VIS I fxnor */ |
2563 |
gen_op_load_fpr_DT0(rs1); |
2564 |
gen_op_load_fpr_DT1(rs2); |
2565 |
gen_op_fxnor(); |
2566 |
gen_op_store_DT0_fpr(rd); |
2567 |
break;
|
2568 |
case 0x073: /* VIS I fxnors */ |
2569 |
gen_op_load_fpr_FT0(rs1); |
2570 |
gen_op_load_fpr_FT1(rs2); |
2571 |
gen_op_fxnors(); |
2572 |
gen_op_store_FT0_fpr(rd); |
2573 |
break;
|
2574 |
case 0x074: /* VIS I fsrc1 */ |
2575 |
gen_op_load_fpr_DT0(rs1); |
2576 |
gen_op_store_DT0_fpr(rd); |
2577 |
break;
|
2578 |
case 0x075: /* VIS I fsrc1s */ |
2579 |
gen_op_load_fpr_FT0(rs1); |
2580 |
gen_op_store_FT0_fpr(rd); |
2581 |
break;
|
2582 |
case 0x076: /* VIS I fornot2 */ |
2583 |
gen_op_load_fpr_DT1(rs1); |
2584 |
gen_op_load_fpr_DT0(rs2); |
2585 |
gen_op_fornot(); |
2586 |
gen_op_store_DT0_fpr(rd); |
2587 |
break;
|
2588 |
case 0x077: /* VIS I fornot2s */ |
2589 |
gen_op_load_fpr_FT1(rs1); |
2590 |
gen_op_load_fpr_FT0(rs2); |
2591 |
gen_op_fornots(); |
2592 |
gen_op_store_FT0_fpr(rd); |
2593 |
break;
|
2594 |
case 0x078: /* VIS I fsrc2 */ |
2595 |
gen_op_load_fpr_DT0(rs2); |
2596 |
gen_op_store_DT0_fpr(rd); |
2597 |
break;
|
2598 |
case 0x079: /* VIS I fsrc2s */ |
2599 |
gen_op_load_fpr_FT0(rs2); |
2600 |
gen_op_store_FT0_fpr(rd); |
2601 |
break;
|
2602 |
case 0x07a: /* VIS I fornot1 */ |
2603 |
gen_op_load_fpr_DT0(rs1); |
2604 |
gen_op_load_fpr_DT1(rs2); |
2605 |
gen_op_fornot(); |
2606 |
gen_op_store_DT0_fpr(rd); |
2607 |
break;
|
2608 |
case 0x07b: /* VIS I fornot1s */ |
2609 |
gen_op_load_fpr_FT0(rs1); |
2610 |
gen_op_load_fpr_FT1(rs2); |
2611 |
gen_op_fornots(); |
2612 |
gen_op_store_FT0_fpr(rd); |
2613 |
break;
|
2614 |
case 0x07c: /* VIS I for */ |
2615 |
gen_op_load_fpr_DT0(rs1); |
2616 |
gen_op_load_fpr_DT1(rs2); |
2617 |
gen_op_for(); |
2618 |
gen_op_store_DT0_fpr(rd); |
2619 |
break;
|
2620 |
case 0x07d: /* VIS I fors */ |
2621 |
gen_op_load_fpr_FT0(rs1); |
2622 |
gen_op_load_fpr_FT1(rs2); |
2623 |
gen_op_fors(); |
2624 |
gen_op_store_FT0_fpr(rd); |
2625 |
break;
|
2626 |
case 0x07e: /* VIS I fone */ |
2627 |
gen_op_movl_DT0_1(); |
2628 |
gen_op_store_DT0_fpr(rd); |
2629 |
break;
|
2630 |
case 0x07f: /* VIS I fones */ |
2631 |
gen_op_movl_FT0_1(); |
2632 |
gen_op_store_FT0_fpr(rd); |
2633 |
break;
|
2634 |
case 0x080: /* VIS I shutdown */ |
2635 |
case 0x081: /* VIS II siam */ |
2636 |
// XXX
|
2637 |
goto illegal_insn;
|
2638 |
default:
|
2639 |
goto illegal_insn;
|
2640 |
} |
2641 |
#else
|
2642 |
goto ncp_insn;
|
2643 |
#endif
|
2644 |
} else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */ |
2645 |
#ifdef TARGET_SPARC64
|
2646 |
goto illegal_insn;
|
2647 |
#else
|
2648 |
goto ncp_insn;
|
2649 |
#endif
|
2650 |
#ifdef TARGET_SPARC64
|
2651 |
} else if (xop == 0x39) { /* V9 return */ |
2652 |
rs1 = GET_FIELD(insn, 13, 17); |
2653 |
gen_movl_reg_T0(rs1); |
2654 |
if (IS_IMM) { /* immediate */ |
2655 |
rs2 = GET_FIELDs(insn, 19, 31); |
2656 |
#if defined(OPTIM)
|
2657 |
if (rs2) {
|
2658 |
#endif
|
2659 |
gen_movl_simm_T1(rs2); |
2660 |
gen_op_add_T1_T0(); |
2661 |
#if defined(OPTIM)
|
2662 |
} |
2663 |
#endif
|
2664 |
} else { /* register */ |
2665 |
rs2 = GET_FIELD(insn, 27, 31); |
2666 |
#if defined(OPTIM)
|
2667 |
if (rs2) {
|
2668 |
#endif
|
2669 |
gen_movl_reg_T1(rs2); |
2670 |
gen_op_add_T1_T0(); |
2671 |
#if defined(OPTIM)
|
2672 |
} |
2673 |
#endif
|
2674 |
} |
2675 |
gen_op_restore(); |
2676 |
gen_mov_pc_npc(dc); |
2677 |
gen_op_movl_npc_T0(); |
2678 |
dc->npc = DYNAMIC_PC; |
2679 |
goto jmp_insn;
|
2680 |
#endif
|
2681 |
} else {
|
2682 |
rs1 = GET_FIELD(insn, 13, 17); |
2683 |
gen_movl_reg_T0(rs1); |
2684 |
if (IS_IMM) { /* immediate */ |
2685 |
rs2 = GET_FIELDs(insn, 19, 31); |
2686 |
#if defined(OPTIM)
|
2687 |
if (rs2) {
|
2688 |
#endif
|
2689 |
gen_movl_simm_T1(rs2); |
2690 |
gen_op_add_T1_T0(); |
2691 |
#if defined(OPTIM)
|
2692 |
} |
2693 |
#endif
|
2694 |
} else { /* register */ |
2695 |
rs2 = GET_FIELD(insn, 27, 31); |
2696 |
#if defined(OPTIM)
|
2697 |
if (rs2) {
|
2698 |
#endif
|
2699 |
gen_movl_reg_T1(rs2); |
2700 |
gen_op_add_T1_T0(); |
2701 |
#if defined(OPTIM)
|
2702 |
} |
2703 |
#endif
|
2704 |
} |
2705 |
switch (xop) {
|
2706 |
case 0x38: /* jmpl */ |
2707 |
{ |
2708 |
if (rd != 0) { |
2709 |
#ifdef TARGET_SPARC64
|
2710 |
if (dc->pc == (uint32_t)dc->pc) {
|
2711 |
gen_op_movl_T1_im(dc->pc); |
2712 |
} else {
|
2713 |
gen_op_movq_T1_im64(dc->pc >> 32, dc->pc);
|
2714 |
} |
2715 |
#else
|
2716 |
gen_op_movl_T1_im(dc->pc); |
2717 |
#endif
|
2718 |
gen_movl_T1_reg(rd); |
2719 |
} |
2720 |
gen_mov_pc_npc(dc); |
2721 |
gen_op_movl_npc_T0(); |
2722 |
dc->npc = DYNAMIC_PC; |
2723 |
} |
2724 |
goto jmp_insn;
|
2725 |
#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
|
2726 |
case 0x39: /* rett, V9 return */ |
2727 |
{ |
2728 |
if (!supervisor(dc))
|
2729 |
goto priv_insn;
|
2730 |
gen_mov_pc_npc(dc); |
2731 |
gen_op_movl_npc_T0(); |
2732 |
dc->npc = DYNAMIC_PC; |
2733 |
gen_op_rett(); |
2734 |
} |
2735 |
goto jmp_insn;
|
2736 |
#endif
|
2737 |
case 0x3b: /* flush */ |
2738 |
gen_op_flush_T0(); |
2739 |
break;
|
2740 |
case 0x3c: /* save */ |
2741 |
save_state(dc); |
2742 |
gen_op_save(); |
2743 |
gen_movl_T0_reg(rd); |
2744 |
break;
|
2745 |
case 0x3d: /* restore */ |
2746 |
save_state(dc); |
2747 |
gen_op_restore(); |
2748 |
gen_movl_T0_reg(rd); |
2749 |
break;
|
2750 |
#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
|
2751 |
case 0x3e: /* V9 done/retry */ |
2752 |
{ |
2753 |
switch (rd) {
|
2754 |
case 0: |
2755 |
if (!supervisor(dc))
|
2756 |
goto priv_insn;
|
2757 |
dc->npc = DYNAMIC_PC; |
2758 |
dc->pc = DYNAMIC_PC; |
2759 |
gen_op_done(); |
2760 |
goto jmp_insn;
|
2761 |
case 1: |
2762 |
if (!supervisor(dc))
|
2763 |
goto priv_insn;
|
2764 |
dc->npc = DYNAMIC_PC; |
2765 |
dc->pc = DYNAMIC_PC; |
2766 |
gen_op_retry(); |
2767 |
goto jmp_insn;
|
2768 |
default:
|
2769 |
goto illegal_insn;
|
2770 |
} |
2771 |
} |
2772 |
break;
|
2773 |
#endif
|
2774 |
default:
|
2775 |
goto illegal_insn;
|
2776 |
} |
2777 |
} |
2778 |
break;
|
2779 |
} |
2780 |
break;
|
2781 |
case 3: /* load/store instructions */ |
2782 |
{ |
2783 |
unsigned int xop = GET_FIELD(insn, 7, 12); |
2784 |
rs1 = GET_FIELD(insn, 13, 17); |
2785 |
save_state(dc); |
2786 |
gen_movl_reg_T0(rs1); |
2787 |
if (IS_IMM) { /* immediate */ |
2788 |
rs2 = GET_FIELDs(insn, 19, 31); |
2789 |
#if defined(OPTIM)
|
2790 |
if (rs2 != 0) { |
2791 |
#endif
|
2792 |
gen_movl_simm_T1(rs2); |
2793 |
gen_op_add_T1_T0(); |
2794 |
#if defined(OPTIM)
|
2795 |
} |
2796 |
#endif
|
2797 |
} else { /* register */ |
2798 |
rs2 = GET_FIELD(insn, 27, 31); |
2799 |
#if defined(OPTIM)
|
2800 |
if (rs2 != 0) { |
2801 |
#endif
|
2802 |
gen_movl_reg_T1(rs2); |
2803 |
gen_op_add_T1_T0(); |
2804 |
#if defined(OPTIM)
|
2805 |
} |
2806 |
#endif
|
2807 |
} |
2808 |
if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) || |
2809 |
(xop > 0x17 && xop <= 0x1d ) || |
2810 |
(xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) { |
2811 |
switch (xop) {
|
2812 |
case 0x0: /* load word */ |
2813 |
gen_op_ldst(ld); |
2814 |
break;
|
2815 |
case 0x1: /* load unsigned byte */ |
2816 |
gen_op_ldst(ldub); |
2817 |
break;
|
2818 |
case 0x2: /* load unsigned halfword */ |
2819 |
gen_op_ldst(lduh); |
2820 |
break;
|
2821 |
case 0x3: /* load double word */ |
2822 |
if (rd & 1) |
2823 |
goto illegal_insn;
|
2824 |
gen_op_ldst(ldd); |
2825 |
gen_movl_T0_reg(rd + 1);
|
2826 |
break;
|
2827 |
case 0x9: /* load signed byte */ |
2828 |
gen_op_ldst(ldsb); |
2829 |
break;
|
2830 |
case 0xa: /* load signed halfword */ |
2831 |
gen_op_ldst(ldsh); |
2832 |
break;
|
2833 |
case 0xd: /* ldstub -- XXX: should be atomically */ |
2834 |
gen_op_ldst(ldstub); |
2835 |
break;
|
2836 |
case 0x0f: /* swap register with memory. Also atomically */ |
2837 |
gen_movl_reg_T1(rd); |
2838 |
gen_op_ldst(swap); |
2839 |
break;
|
2840 |
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
|
2841 |
case 0x10: /* load word alternate */ |
2842 |
#ifndef TARGET_SPARC64
|
2843 |
if (IS_IMM)
|
2844 |
goto illegal_insn;
|
2845 |
if (!supervisor(dc))
|
2846 |
goto priv_insn;
|
2847 |
#endif
|
2848 |
gen_op_lda(insn, 1, 4, 0); |
2849 |
break;
|
2850 |
case 0x11: /* load unsigned byte alternate */ |
2851 |
#ifndef TARGET_SPARC64
|
2852 |
if (IS_IMM)
|
2853 |
goto illegal_insn;
|
2854 |
if (!supervisor(dc))
|
2855 |
goto priv_insn;
|
2856 |
#endif
|
2857 |
gen_op_lduba(insn, 1, 1, 0); |
2858 |
break;
|
2859 |
case 0x12: /* load unsigned halfword alternate */ |
2860 |
#ifndef TARGET_SPARC64
|
2861 |
if (IS_IMM)
|
2862 |
goto illegal_insn;
|
2863 |
if (!supervisor(dc))
|
2864 |
goto priv_insn;
|
2865 |
#endif
|
2866 |
gen_op_lduha(insn, 1, 2, 0); |
2867 |
break;
|
2868 |
case 0x13: /* load double word alternate */ |
2869 |
#ifndef TARGET_SPARC64
|
2870 |
if (IS_IMM)
|
2871 |
goto illegal_insn;
|
2872 |
if (!supervisor(dc))
|
2873 |
goto priv_insn;
|
2874 |
#endif
|
2875 |
if (rd & 1) |
2876 |
goto illegal_insn;
|
2877 |
gen_op_ldda(insn, 1, 8, 0); |
2878 |
gen_movl_T0_reg(rd + 1);
|
2879 |
break;
|
2880 |
case 0x19: /* load signed byte alternate */ |
2881 |
#ifndef TARGET_SPARC64
|
2882 |
if (IS_IMM)
|
2883 |
goto illegal_insn;
|
2884 |
if (!supervisor(dc))
|
2885 |
goto priv_insn;
|
2886 |
#endif
|
2887 |
gen_op_ldsba(insn, 1, 1, 1); |
2888 |
break;
|
2889 |
case 0x1a: /* load signed halfword alternate */ |
2890 |
#ifndef TARGET_SPARC64
|
2891 |
if (IS_IMM)
|
2892 |
goto illegal_insn;
|
2893 |
if (!supervisor(dc))
|
2894 |
goto priv_insn;
|
2895 |
#endif
|
2896 |
gen_op_ldsha(insn, 1, 2 ,1); |
2897 |
break;
|
2898 |
case 0x1d: /* ldstuba -- XXX: should be atomically */ |
2899 |
#ifndef TARGET_SPARC64
|
2900 |
if (IS_IMM)
|
2901 |
goto illegal_insn;
|
2902 |
if (!supervisor(dc))
|
2903 |
goto priv_insn;
|
2904 |
#endif
|
2905 |
gen_op_ldstuba(insn, 1, 1, 0); |
2906 |
break;
|
2907 |
case 0x1f: /* swap reg with alt. memory. Also atomically */ |
2908 |
#ifndef TARGET_SPARC64
|
2909 |
if (IS_IMM)
|
2910 |
goto illegal_insn;
|
2911 |
if (!supervisor(dc))
|
2912 |
goto priv_insn;
|
2913 |
#endif
|
2914 |
gen_movl_reg_T1(rd); |
2915 |
gen_op_swapa(insn, 1, 4, 0); |
2916 |
break;
|
2917 |
|
2918 |
#ifndef TARGET_SPARC64
|
2919 |
case 0x30: /* ldc */ |
2920 |
case 0x31: /* ldcsr */ |
2921 |
case 0x33: /* lddc */ |
2922 |
goto ncp_insn;
|
2923 |
/* avoid warnings */
|
2924 |
(void) &gen_op_stfa;
|
2925 |
(void) &gen_op_stdfa;
|
2926 |
(void) &gen_op_ldfa;
|
2927 |
(void) &gen_op_lddfa;
|
2928 |
#else
|
2929 |
#if !defined(CONFIG_USER_ONLY)
|
2930 |
(void) &gen_op_cas;
|
2931 |
(void) &gen_op_casx;
|
2932 |
#endif
|
2933 |
#endif
|
2934 |
#endif
|
2935 |
#ifdef TARGET_SPARC64
|
2936 |
case 0x08: /* V9 ldsw */ |
2937 |
gen_op_ldst(ldsw); |
2938 |
break;
|
2939 |
case 0x0b: /* V9 ldx */ |
2940 |
gen_op_ldst(ldx); |
2941 |
break;
|
2942 |
case 0x18: /* V9 ldswa */ |
2943 |
gen_op_ldswa(insn, 1, 4, 1); |
2944 |
break;
|
2945 |
case 0x1b: /* V9 ldxa */ |
2946 |
gen_op_ldxa(insn, 1, 8, 0); |
2947 |
break;
|
2948 |
case 0x2d: /* V9 prefetch, no effect */ |
2949 |
goto skip_move;
|
2950 |
case 0x30: /* V9 ldfa */ |
2951 |
gen_op_ldfa(insn, 1, 8, 0); // XXX |
2952 |
break;
|
2953 |
case 0x33: /* V9 lddfa */ |
2954 |
gen_op_lddfa(insn, 1, 8, 0); // XXX |
2955 |
|
2956 |
break;
|
2957 |
case 0x3d: /* V9 prefetcha, no effect */ |
2958 |
goto skip_move;
|
2959 |
case 0x32: /* V9 ldqfa */ |
2960 |
goto nfpu_insn;
|
2961 |
#endif
|
2962 |
default:
|
2963 |
goto illegal_insn;
|
2964 |
} |
2965 |
gen_movl_T1_reg(rd); |
2966 |
#ifdef TARGET_SPARC64
|
2967 |
skip_move: ;
|
2968 |
#endif
|
2969 |
} else if (xop >= 0x20 && xop < 0x24) { |
2970 |
if (gen_trap_ifnofpu(dc))
|
2971 |
goto jmp_insn;
|
2972 |
switch (xop) {
|
2973 |
case 0x20: /* load fpreg */ |
2974 |
gen_op_ldst(ldf); |
2975 |
gen_op_store_FT0_fpr(rd); |
2976 |
break;
|
2977 |
case 0x21: /* load fsr */ |
2978 |
gen_op_ldst(ldf); |
2979 |
gen_op_ldfsr(); |
2980 |
break;
|
2981 |
case 0x22: /* load quad fpreg */ |
2982 |
goto nfpu_insn;
|
2983 |
case 0x23: /* load double fpreg */ |
2984 |
gen_op_ldst(lddf); |
2985 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
2986 |
break;
|
2987 |
default:
|
2988 |
goto illegal_insn;
|
2989 |
} |
2990 |
} else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \ |
2991 |
xop == 0xe || xop == 0x1e) { |
2992 |
gen_movl_reg_T1(rd); |
2993 |
switch (xop) {
|
2994 |
case 0x4: |
2995 |
gen_op_ldst(st); |
2996 |
break;
|
2997 |
case 0x5: |
2998 |
gen_op_ldst(stb); |
2999 |
break;
|
3000 |
case 0x6: |
3001 |
gen_op_ldst(sth); |
3002 |
break;
|
3003 |
case 0x7: |
3004 |
if (rd & 1) |
3005 |
goto illegal_insn;
|
3006 |
flush_T2(dc); |
3007 |
gen_movl_reg_T2(rd + 1);
|
3008 |
gen_op_ldst(std); |
3009 |
break;
|
3010 |
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
|
3011 |
case 0x14: |
3012 |
#ifndef TARGET_SPARC64
|
3013 |
if (IS_IMM)
|
3014 |
goto illegal_insn;
|
3015 |
if (!supervisor(dc))
|
3016 |
goto priv_insn;
|
3017 |
#endif
|
3018 |
gen_op_sta(insn, 0, 4, 0); |
3019 |
break;
|
3020 |
case 0x15: |
3021 |
#ifndef TARGET_SPARC64
|
3022 |
if (IS_IMM)
|
3023 |
goto illegal_insn;
|
3024 |
if (!supervisor(dc))
|
3025 |
goto priv_insn;
|
3026 |
#endif
|
3027 |
gen_op_stba(insn, 0, 1, 0); |
3028 |
break;
|
3029 |
case 0x16: |
3030 |
#ifndef TARGET_SPARC64
|
3031 |
if (IS_IMM)
|
3032 |
goto illegal_insn;
|
3033 |
if (!supervisor(dc))
|
3034 |
goto priv_insn;
|
3035 |
#endif
|
3036 |
gen_op_stha(insn, 0, 2, 0); |
3037 |
break;
|
3038 |
case 0x17: |
3039 |
#ifndef TARGET_SPARC64
|
3040 |
if (IS_IMM)
|
3041 |
goto illegal_insn;
|
3042 |
if (!supervisor(dc))
|
3043 |
goto priv_insn;
|
3044 |
#endif
|
3045 |
if (rd & 1) |
3046 |
goto illegal_insn;
|
3047 |
flush_T2(dc); |
3048 |
gen_movl_reg_T2(rd + 1);
|
3049 |
gen_op_stda(insn, 0, 8, 0); |
3050 |
break;
|
3051 |
#endif
|
3052 |
#ifdef TARGET_SPARC64
|
3053 |
case 0x0e: /* V9 stx */ |
3054 |
gen_op_ldst(stx); |
3055 |
break;
|
3056 |
case 0x1e: /* V9 stxa */ |
3057 |
gen_op_stxa(insn, 0, 8, 0); // XXX |
3058 |
break;
|
3059 |
#endif
|
3060 |
default:
|
3061 |
goto illegal_insn;
|
3062 |
} |
3063 |
} else if (xop > 0x23 && xop < 0x28) { |
3064 |
if (gen_trap_ifnofpu(dc))
|
3065 |
goto jmp_insn;
|
3066 |
switch (xop) {
|
3067 |
case 0x24: |
3068 |
gen_op_load_fpr_FT0(rd); |
3069 |
gen_op_ldst(stf); |
3070 |
break;
|
3071 |
case 0x25: /* stfsr, V9 stxfsr */ |
3072 |
gen_op_stfsr(); |
3073 |
gen_op_ldst(stf); |
3074 |
break;
|
3075 |
#if !defined(CONFIG_USER_ONLY)
|
3076 |
case 0x26: /* stdfq */ |
3077 |
if (!supervisor(dc))
|
3078 |
goto priv_insn;
|
3079 |
if (gen_trap_ifnofpu(dc))
|
3080 |
goto jmp_insn;
|
3081 |
goto nfq_insn;
|
3082 |
#endif
|
3083 |
case 0x27: |
3084 |
gen_op_load_fpr_DT0(DFPREG(rd)); |
3085 |
gen_op_ldst(stdf); |
3086 |
break;
|
3087 |
default:
|
3088 |
goto illegal_insn;
|
3089 |
} |
3090 |
} else if (xop > 0x33 && xop < 0x3f) { |
3091 |
switch (xop) {
|
3092 |
#ifdef TARGET_SPARC64
|
3093 |
case 0x34: /* V9 stfa */ |
3094 |
gen_op_stfa(insn, 0, 0, 0); // XXX |
3095 |
break;
|
3096 |
case 0x37: /* V9 stdfa */ |
3097 |
gen_op_stdfa(insn, 0, 0, 0); // XXX |
3098 |
break;
|
3099 |
case 0x3c: /* V9 casa */ |
3100 |
gen_op_casa(insn, 0, 4, 0); // XXX |
3101 |
break;
|
3102 |
case 0x3e: /* V9 casxa */ |
3103 |
gen_op_casxa(insn, 0, 8, 0); // XXX |
3104 |
break;
|
3105 |
case 0x36: /* V9 stqfa */ |
3106 |
goto nfpu_insn;
|
3107 |
#else
|
3108 |
case 0x34: /* stc */ |
3109 |
case 0x35: /* stcsr */ |
3110 |
case 0x36: /* stdcq */ |
3111 |
case 0x37: /* stdc */ |
3112 |
goto ncp_insn;
|
3113 |
#endif
|
3114 |
default:
|
3115 |
goto illegal_insn;
|
3116 |
} |
3117 |
} |
3118 |
else
|
3119 |
goto illegal_insn;
|
3120 |
} |
3121 |
break;
|
3122 |
} |
3123 |
/* default case for non jump instructions */
|
3124 |
if (dc->npc == DYNAMIC_PC) {
|
3125 |
dc->pc = DYNAMIC_PC; |
3126 |
gen_op_next_insn(); |
3127 |
} else if (dc->npc == JUMP_PC) { |
3128 |
/* we can do a static jump */
|
3129 |
gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1]); |
3130 |
dc->is_br = 1;
|
3131 |
} else {
|
3132 |
dc->pc = dc->npc; |
3133 |
dc->npc = dc->npc + 4;
|
3134 |
} |
3135 |
jmp_insn:
|
3136 |
return;
|
3137 |
illegal_insn:
|
3138 |
save_state(dc); |
3139 |
gen_op_exception(TT_ILL_INSN); |
3140 |
dc->is_br = 1;
|
3141 |
return;
|
3142 |
#if !defined(CONFIG_USER_ONLY)
|
3143 |
priv_insn:
|
3144 |
save_state(dc); |
3145 |
gen_op_exception(TT_PRIV_INSN); |
3146 |
dc->is_br = 1;
|
3147 |
return;
|
3148 |
#endif
|
3149 |
nfpu_insn:
|
3150 |
save_state(dc); |
3151 |
gen_op_fpexception_im(FSR_FTT_UNIMPFPOP); |
3152 |
dc->is_br = 1;
|
3153 |
return;
|
3154 |
#if !defined(CONFIG_USER_ONLY)
|
3155 |
nfq_insn:
|
3156 |
save_state(dc); |
3157 |
gen_op_fpexception_im(FSR_FTT_SEQ_ERROR); |
3158 |
dc->is_br = 1;
|
3159 |
return;
|
3160 |
#endif
|
3161 |
#ifndef TARGET_SPARC64
|
3162 |
ncp_insn:
|
3163 |
save_state(dc); |
3164 |
gen_op_exception(TT_NCP_INSN); |
3165 |
dc->is_br = 1;
|
3166 |
return;
|
3167 |
#endif
|
3168 |
} |
3169 |
|
3170 |
static inline int gen_intermediate_code_internal(TranslationBlock * tb, |
3171 |
int spc, CPUSPARCState *env)
|
3172 |
{ |
3173 |
target_ulong pc_start, last_pc; |
3174 |
uint16_t *gen_opc_end; |
3175 |
DisasContext dc1, *dc = &dc1; |
3176 |
int j, lj = -1; |
3177 |
|
3178 |
memset(dc, 0, sizeof(DisasContext)); |
3179 |
dc->tb = tb; |
3180 |
pc_start = tb->pc; |
3181 |
dc->pc = pc_start; |
3182 |
last_pc = dc->pc; |
3183 |
dc->npc = (target_ulong) tb->cs_base; |
3184 |
#if defined(CONFIG_USER_ONLY)
|
3185 |
dc->mem_idx = 0;
|
3186 |
dc->fpu_enabled = 1;
|
3187 |
#else
|
3188 |
dc->mem_idx = ((env->psrs) != 0);
|
3189 |
#ifdef TARGET_SPARC64
|
3190 |
dc->fpu_enabled = (((env->pstate & PS_PEF) != 0) && ((env->fprs & FPRS_FEF) != 0)); |
3191 |
#else
|
3192 |
dc->fpu_enabled = ((env->psref) != 0);
|
3193 |
#endif
|
3194 |
#endif
|
3195 |
gen_opc_ptr = gen_opc_buf; |
3196 |
gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
3197 |
gen_opparam_ptr = gen_opparam_buf; |
3198 |
nb_gen_labels = 0;
|
3199 |
|
3200 |
do {
|
3201 |
if (env->nb_breakpoints > 0) { |
3202 |
for(j = 0; j < env->nb_breakpoints; j++) { |
3203 |
if (env->breakpoints[j] == dc->pc) {
|
3204 |
if (dc->pc != pc_start)
|
3205 |
save_state(dc); |
3206 |
gen_op_debug(); |
3207 |
gen_op_movl_T0_0(); |
3208 |
gen_op_exit_tb(); |
3209 |
dc->is_br = 1;
|
3210 |
goto exit_gen_loop;
|
3211 |
} |
3212 |
} |
3213 |
} |
3214 |
if (spc) {
|
3215 |
if (loglevel > 0) |
3216 |
fprintf(logfile, "Search PC...\n");
|
3217 |
j = gen_opc_ptr - gen_opc_buf; |
3218 |
if (lj < j) {
|
3219 |
lj++; |
3220 |
while (lj < j)
|
3221 |
gen_opc_instr_start[lj++] = 0;
|
3222 |
gen_opc_pc[lj] = dc->pc; |
3223 |
gen_opc_npc[lj] = dc->npc; |
3224 |
gen_opc_instr_start[lj] = 1;
|
3225 |
} |
3226 |
} |
3227 |
last_pc = dc->pc; |
3228 |
disas_sparc_insn(dc); |
3229 |
|
3230 |
if (dc->is_br)
|
3231 |
break;
|
3232 |
/* if the next PC is different, we abort now */
|
3233 |
if (dc->pc != (last_pc + 4)) |
3234 |
break;
|
3235 |
/* if we reach a page boundary, we stop generation so that the
|
3236 |
PC of a TT_TFAULT exception is always in the right page */
|
3237 |
if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0) |
3238 |
break;
|
3239 |
/* if single step mode, we generate only one instruction and
|
3240 |
generate an exception */
|
3241 |
if (env->singlestep_enabled) {
|
3242 |
gen_jmp_im(dc->pc); |
3243 |
gen_op_movl_T0_0(); |
3244 |
gen_op_exit_tb(); |
3245 |
break;
|
3246 |
} |
3247 |
} while ((gen_opc_ptr < gen_opc_end) &&
|
3248 |
(dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
|
3249 |
|
3250 |
exit_gen_loop:
|
3251 |
if (!dc->is_br) {
|
3252 |
if (dc->pc != DYNAMIC_PC &&
|
3253 |
(dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) { |
3254 |
/* static PC and NPC: we can use direct chaining */
|
3255 |
gen_branch(dc, dc->pc, dc->npc); |
3256 |
} else {
|
3257 |
if (dc->pc != DYNAMIC_PC)
|
3258 |
gen_jmp_im(dc->pc); |
3259 |
save_npc(dc); |
3260 |
gen_op_movl_T0_0(); |
3261 |
gen_op_exit_tb(); |
3262 |
} |
3263 |
} |
3264 |
*gen_opc_ptr = INDEX_op_end; |
3265 |
if (spc) {
|
3266 |
j = gen_opc_ptr - gen_opc_buf; |
3267 |
lj++; |
3268 |
while (lj <= j)
|
3269 |
gen_opc_instr_start[lj++] = 0;
|
3270 |
tb->size = 0;
|
3271 |
#if 0
|
3272 |
if (loglevel > 0) {
|
3273 |
page_dump(logfile);
|
3274 |
}
|
3275 |
#endif
|
3276 |
gen_opc_jump_pc[0] = dc->jump_pc[0]; |
3277 |
gen_opc_jump_pc[1] = dc->jump_pc[1]; |
3278 |
} else {
|
3279 |
tb->size = last_pc + 4 - pc_start;
|
3280 |
} |
3281 |
#ifdef DEBUG_DISAS
|
3282 |
if (loglevel & CPU_LOG_TB_IN_ASM) {
|
3283 |
fprintf(logfile, "--------------\n");
|
3284 |
fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
|
3285 |
target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0); |
3286 |
fprintf(logfile, "\n");
|
3287 |
if (loglevel & CPU_LOG_TB_OP) {
|
3288 |
fprintf(logfile, "OP:\n");
|
3289 |
dump_ops(gen_opc_buf, gen_opparam_buf); |
3290 |
fprintf(logfile, "\n");
|
3291 |
} |
3292 |
} |
3293 |
#endif
|
3294 |
return 0; |
3295 |
} |
3296 |
|
3297 |
int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
|
3298 |
{ |
3299 |
return gen_intermediate_code_internal(tb, 0, env); |
3300 |
} |
3301 |
|
3302 |
int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
|
3303 |
{ |
3304 |
return gen_intermediate_code_internal(tb, 1, env); |
3305 |
} |
3306 |
|
3307 |
extern int ram_size; |
3308 |
|
3309 |
void cpu_reset(CPUSPARCState *env)
|
3310 |
{ |
3311 |
tlb_flush(env, 1);
|
3312 |
env->cwp = 0;
|
3313 |
env->wim = 1;
|
3314 |
env->regwptr = env->regbase + (env->cwp * 16);
|
3315 |
#if defined(CONFIG_USER_ONLY)
|
3316 |
env->user_mode_only = 1;
|
3317 |
#ifdef TARGET_SPARC64
|
3318 |
env->cleanwin = NWINDOWS - 2;
|
3319 |
env->cansave = NWINDOWS - 2;
|
3320 |
env->pstate = PS_RMO | PS_PEF | PS_IE; |
3321 |
env->asi = 0x82; // Primary no-fault |
3322 |
#endif
|
3323 |
#else
|
3324 |
env->psret = 0;
|
3325 |
env->psrs = 1;
|
3326 |
env->psrps = 1;
|
3327 |
#ifdef TARGET_SPARC64
|
3328 |
env->pstate = PS_PRIV; |
3329 |
env->pc = 0x1fff0000000ULL;
|
3330 |
#else
|
3331 |
env->pc = 0xffd00000;
|
3332 |
env->mmuregs[0] &= ~(MMU_E | MMU_NF);
|
3333 |
#endif
|
3334 |
env->npc = env->pc + 4;
|
3335 |
#endif
|
3336 |
} |
3337 |
|
3338 |
CPUSPARCState *cpu_sparc_init(void)
|
3339 |
{ |
3340 |
CPUSPARCState *env; |
3341 |
|
3342 |
env = qemu_mallocz(sizeof(CPUSPARCState));
|
3343 |
if (!env)
|
3344 |
return NULL; |
3345 |
cpu_exec_init(env); |
3346 |
cpu_reset(env); |
3347 |
return (env);
|
3348 |
} |
3349 |
|
3350 |
static const sparc_def_t sparc_defs[] = { |
3351 |
#ifdef TARGET_SPARC64
|
3352 |
{ |
3353 |
.name = "TI UltraSparc II",
|
3354 |
.iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0 << 24) |
3355 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
3356 |
.fpu_version = 0x00000000,
|
3357 |
.mmu_version = 0,
|
3358 |
}, |
3359 |
#else
|
3360 |
{ |
3361 |
.name = "Fujitsu MB86904",
|
3362 |
.iu_version = 0x04 << 24, /* Impl 0, ver 4 */ |
3363 |
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
3364 |
.mmu_version = 0x04 << 24, /* Impl 0, ver 4 */ |
3365 |
}, |
3366 |
{ |
3367 |
.name = "Fujitsu MB86907",
|
3368 |
.iu_version = 0x05 << 24, /* Impl 0, ver 5 */ |
3369 |
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
3370 |
.mmu_version = 0x05 << 24, /* Impl 0, ver 5 */ |
3371 |
}, |
3372 |
{ |
3373 |
.name = "TI MicroSparc I",
|
3374 |
.iu_version = 0x41000000,
|
3375 |
.fpu_version = 4 << 17, |
3376 |
.mmu_version = 0x41000000,
|
3377 |
}, |
3378 |
{ |
3379 |
.name = "TI SuperSparc II",
|
3380 |
.iu_version = 0x40000000,
|
3381 |
.fpu_version = 0 << 17, |
3382 |
.mmu_version = 0x04000000,
|
3383 |
}, |
3384 |
{ |
3385 |
.name = "Ross RT620",
|
3386 |
.iu_version = 0x1e000000,
|
3387 |
.fpu_version = 1 << 17, |
3388 |
.mmu_version = 0x17000000,
|
3389 |
}, |
3390 |
#endif
|
3391 |
}; |
3392 |
|
3393 |
int sparc_find_by_name(const unsigned char *name, const sparc_def_t **def) |
3394 |
{ |
3395 |
int ret;
|
3396 |
unsigned int i; |
3397 |
|
3398 |
ret = -1;
|
3399 |
*def = NULL;
|
3400 |
for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) { |
3401 |
if (strcasecmp(name, sparc_defs[i].name) == 0) { |
3402 |
*def = &sparc_defs[i]; |
3403 |
ret = 0;
|
3404 |
break;
|
3405 |
} |
3406 |
} |
3407 |
|
3408 |
return ret;
|
3409 |
} |
3410 |
|
3411 |
void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) |
3412 |
{ |
3413 |
unsigned int i; |
3414 |
|
3415 |
for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) { |
3416 |
(*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx " FPU %08x MMU %08x\n", |
3417 |
sparc_defs[i].name, |
3418 |
sparc_defs[i].iu_version, |
3419 |
sparc_defs[i].fpu_version, |
3420 |
sparc_defs[i].mmu_version); |
3421 |
} |
3422 |
} |
3423 |
|
3424 |
int cpu_sparc_register (CPUSPARCState *env, const sparc_def_t *def) |
3425 |
{ |
3426 |
env->version = def->iu_version; |
3427 |
env->fsr = def->fpu_version; |
3428 |
#if !defined(TARGET_SPARC64)
|
3429 |
env->mmuregs[0] = def->mmu_version;
|
3430 |
#endif
|
3431 |
return 0; |
3432 |
} |
3433 |
|
3434 |
#define GET_FLAG(a,b) ((env->psr & a)?b:'-') |
3435 |
|
3436 |
void cpu_dump_state(CPUState *env, FILE *f,
|
3437 |
int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
3438 |
int flags)
|
3439 |
{ |
3440 |
int i, x;
|
3441 |
|
3442 |
cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, env->npc); |
3443 |
cpu_fprintf(f, "General Registers:\n");
|
3444 |
for (i = 0; i < 4; i++) |
3445 |
cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]); |
3446 |
cpu_fprintf(f, "\n");
|
3447 |
for (; i < 8; i++) |
3448 |
cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]); |
3449 |
cpu_fprintf(f, "\nCurrent Register Window:\n");
|
3450 |
for (x = 0; x < 3; x++) { |
3451 |
for (i = 0; i < 4; i++) |
3452 |
cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t", |
3453 |
(x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i, |
3454 |
env->regwptr[i + x * 8]);
|
3455 |
cpu_fprintf(f, "\n");
|
3456 |
for (; i < 8; i++) |
3457 |
cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t", |
3458 |
(x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i, |
3459 |
env->regwptr[i + x * 8]);
|
3460 |
cpu_fprintf(f, "\n");
|
3461 |
} |
3462 |
cpu_fprintf(f, "\nFloating Point Registers:\n");
|
3463 |
for (i = 0; i < 32; i++) { |
3464 |
if ((i & 3) == 0) |
3465 |
cpu_fprintf(f, "%%f%02d:", i);
|
3466 |
cpu_fprintf(f, " %016lf", env->fpr[i]);
|
3467 |
if ((i & 3) == 3) |
3468 |
cpu_fprintf(f, "\n");
|
3469 |
} |
3470 |
#ifdef TARGET_SPARC64
|
3471 |
cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n",
|
3472 |
env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs); |
3473 |
cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d cleanwin %d cwp %d\n",
|
3474 |
env->cansave, env->canrestore, env->otherwin, env->wstate, |
3475 |
env->cleanwin, NWINDOWS - 1 - env->cwp);
|
3476 |
#else
|
3477 |
cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env),
|
3478 |
GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'), |
3479 |
GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'), |
3480 |
env->psrs?'S':'-', env->psrps?'P':'-', |
3481 |
env->psret?'E':'-', env->wim); |
3482 |
#endif
|
3483 |
cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env));
|
3484 |
} |
3485 |
|
3486 |
#if defined(CONFIG_USER_ONLY)
|
3487 |
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
3488 |
{ |
3489 |
return addr;
|
3490 |
} |
3491 |
|
3492 |
#else
|
3493 |
extern int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot, |
3494 |
int *access_index, target_ulong address, int rw, |
3495 |
int is_user);
|
3496 |
|
3497 |
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
3498 |
{ |
3499 |
target_phys_addr_t phys_addr; |
3500 |
int prot, access_index;
|
3501 |
|
3502 |
if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2, 0) != 0) |
3503 |
if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 0, 0) != 0) |
3504 |
return -1; |
3505 |
if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED)
|
3506 |
return -1; |
3507 |
return phys_addr;
|
3508 |
} |
3509 |
#endif
|
3510 |
|
3511 |
void helper_flush(target_ulong addr)
|
3512 |
{ |
3513 |
addr &= ~7;
|
3514 |
tb_invalidate_page_range(addr, addr + 8);
|
3515 |
} |