root / target-sparc / op_helper.c @ 6f27aba6
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#include "exec.h" |
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//#define DEBUG_PCALL
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//#define DEBUG_MMU
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//#define DEBUG_MXCC
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//#define DEBUG_UNALIGNED
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//#define DEBUG_UNASSIGNED
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#ifdef DEBUG_MMU
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#define DPRINTF_MMU(fmt, args...) \
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do { printf("MMU: " fmt , ##args); } while (0) |
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#else
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#define DPRINTF_MMU(fmt, args...)
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#endif
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#ifdef DEBUG_MXCC
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#define DPRINTF_MXCC(fmt, args...) \
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do { printf("MXCC: " fmt , ##args); } while (0) |
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#else
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#define DPRINTF_MXCC(fmt, args...)
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#endif
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void raise_exception(int tt) |
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{
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env->exception_index = tt; |
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cpu_loop_exit(); |
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} |
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|
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void check_ieee_exceptions()
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{
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T0 = get_float_exception_flags(&env->fp_status); |
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if (T0)
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{
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/* Copy IEEE 754 flags into FSR */
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if (T0 & float_flag_invalid)
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env->fsr |= FSR_NVC; |
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if (T0 & float_flag_overflow)
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env->fsr |= FSR_OFC; |
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if (T0 & float_flag_underflow)
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env->fsr |= FSR_UFC; |
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if (T0 & float_flag_divbyzero)
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env->fsr |= FSR_DZC; |
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if (T0 & float_flag_inexact)
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env->fsr |= FSR_NXC; |
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if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23)) |
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{
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/* Unmasked exception, generate a trap */
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env->fsr |= FSR_FTT_IEEE_EXCP; |
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raise_exception(TT_FP_EXCP); |
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} |
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else
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{
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/* Accumulate exceptions */
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env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
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} |
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} |
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} |
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#ifdef USE_INT_TO_FLOAT_HELPERS
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void do_fitos(void) |
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{
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set_float_exception_flags(0, &env->fp_status);
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FT0 = int32_to_float32(*((int32_t *)&FT1), &env->fp_status); |
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check_ieee_exceptions(); |
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} |
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|
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void do_fitod(void) |
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{
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DT0 = int32_to_float64(*((int32_t *)&FT1), &env->fp_status); |
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} |
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#endif
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void do_fabss(void) |
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{
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FT0 = float32_abs(FT1); |
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} |
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#ifdef TARGET_SPARC64
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void do_fabsd(void) |
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{
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DT0 = float64_abs(DT1); |
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} |
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#endif
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void do_fsqrts(void) |
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{
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set_float_exception_flags(0, &env->fp_status);
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FT0 = float32_sqrt(FT1, &env->fp_status); |
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check_ieee_exceptions(); |
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} |
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|
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void do_fsqrtd(void) |
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{
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set_float_exception_flags(0, &env->fp_status);
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DT0 = float64_sqrt(DT1, &env->fp_status); |
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check_ieee_exceptions(); |
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} |
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#define GEN_FCMP(name, size, reg1, reg2, FS, TRAP) \
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void glue(do_, name) (void) \ |
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{ \
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env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \ |
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switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
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case float_relation_unordered: \
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T0 = (FSR_FCC1 | FSR_FCC0) << FS; \ |
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if ((env->fsr & FSR_NVM) || TRAP) { \
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env->fsr |= T0; \ |
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env->fsr |= FSR_NVC; \ |
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env->fsr |= FSR_FTT_IEEE_EXCP; \ |
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raise_exception(TT_FP_EXCP); \ |
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} else { \
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env->fsr |= FSR_NVA; \ |
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} \ |
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break; \
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case float_relation_less: \
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T0 = FSR_FCC0 << FS; \ |
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break; \
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case float_relation_greater: \
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T0 = FSR_FCC1 << FS; \ |
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break; \
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default: \
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T0 = 0; \
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break; \
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} \ |
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env->fsr |= T0; \ |
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} |
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GEN_FCMP(fcmps, float32, FT0, FT1, 0, 0); |
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GEN_FCMP(fcmpd, float64, DT0, DT1, 0, 0); |
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|
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GEN_FCMP(fcmpes, float32, FT0, FT1, 0, 1); |
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GEN_FCMP(fcmped, float64, DT0, DT1, 0, 1); |
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#ifdef TARGET_SPARC64
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GEN_FCMP(fcmps_fcc1, float32, FT0, FT1, 22, 0); |
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GEN_FCMP(fcmpd_fcc1, float64, DT0, DT1, 22, 0); |
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GEN_FCMP(fcmps_fcc2, float32, FT0, FT1, 24, 0); |
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GEN_FCMP(fcmpd_fcc2, float64, DT0, DT1, 24, 0); |
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GEN_FCMP(fcmps_fcc3, float32, FT0, FT1, 26, 0); |
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GEN_FCMP(fcmpd_fcc3, float64, DT0, DT1, 26, 0); |
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|
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GEN_FCMP(fcmpes_fcc1, float32, FT0, FT1, 22, 1); |
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GEN_FCMP(fcmped_fcc1, float64, DT0, DT1, 22, 1); |
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GEN_FCMP(fcmpes_fcc2, float32, FT0, FT1, 24, 1); |
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GEN_FCMP(fcmped_fcc2, float64, DT0, DT1, 24, 1); |
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|
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GEN_FCMP(fcmpes_fcc3, float32, FT0, FT1, 26, 1); |
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GEN_FCMP(fcmped_fcc3, float64, DT0, DT1, 26, 1); |
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#endif
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#ifndef TARGET_SPARC64
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#ifndef CONFIG_USER_ONLY
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#ifdef DEBUG_MXCC
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static void dump_mxcc(CPUState *env) |
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{
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printf("mxccdata: %016llx %016llx %016llx %016llx\n",
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env->mxccdata[0], env->mxccdata[1], env->mxccdata[2], env->mxccdata[3]); |
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printf("mxccregs: %016llx %016llx %016llx %016llx\n"
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" %016llx %016llx %016llx %016llx\n",
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env->mxccregs[0], env->mxccregs[1], env->mxccregs[2], env->mxccregs[3], |
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env->mxccregs[4], env->mxccregs[5], env->mxccregs[6], env->mxccregs[7]); |
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} |
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#endif
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void helper_ld_asi(int asi, int size, int sign) |
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{
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uint32_t ret = 0;
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#ifdef DEBUG_MXCC
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uint32_t last_T0 = T0; |
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#endif
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switch (asi) {
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case 2: /* SuperSparc MXCC registers */ |
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switch (T0) {
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case 0x01c00a00: /* MXCC control register */ |
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if (size == 8) { |
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ret = env->mxccregs[3];
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T0 = env->mxccregs[3] >> 32; |
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} else
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DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
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break;
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case 0x01c00a04: /* MXCC control register */ |
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if (size == 4) |
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ret = env->mxccregs[3];
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else
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DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
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break;
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case 0x01c00f00: /* MBus port address register */ |
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if (size == 8) { |
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ret = env->mxccregs[7];
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T0 = env->mxccregs[7] >> 32; |
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} else
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DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
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break;
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default:
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DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", T0, size);
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break;
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} |
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DPRINTF_MXCC("asi = %d, size = %d, sign = %d, T0 = %08x -> ret = %08x,"
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"T0 = %08x\n", asi, size, sign, last_T0, ret, T0);
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#ifdef DEBUG_MXCC
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dump_mxcc(env); |
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#endif
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break;
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case 3: /* MMU probe */ |
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{
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int mmulev;
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mmulev = (T0 >> 8) & 15; |
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if (mmulev > 4) |
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ret = 0;
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else {
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ret = mmu_probe(env, T0, mmulev); |
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//bswap32s(&ret);
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} |
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DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08x\n", T0, mmulev, ret);
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} |
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break;
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case 4: /* read MMU regs */ |
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{
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int reg = (T0 >> 8) & 0xf; |
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ret = env->mmuregs[reg]; |
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if (reg == 3) /* Fault status cleared on read */ |
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env->mmuregs[reg] = 0;
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DPRINTF_MMU("mmu_read: reg[%d] = 0x%08x\n", reg, ret);
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} |
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break;
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case 9: /* Supervisor code access */ |
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switch(size) {
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case 1: |
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ret = ldub_code(T0); |
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break;
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case 2: |
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ret = lduw_code(T0 & ~1);
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break;
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default:
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case 4: |
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ret = ldl_code(T0 & ~3);
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break;
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case 8: |
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ret = ldl_code(T0 & ~3);
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T0 = ldl_code((T0 + 4) & ~3); |
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break;
|
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} |
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break;
|
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case 0xa: /* User data access */ |
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switch(size) {
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case 1: |
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ret = ldub_user(T0); |
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break;
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case 2: |
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ret = lduw_user(T0 & ~1);
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break;
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default:
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case 4: |
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ret = ldl_user(T0 & ~3);
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break;
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case 8: |
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ret = ldl_user(T0 & ~3);
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T0 = ldl_user((T0 + 4) & ~3); |
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break;
|
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} |
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break;
|
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case 0xb: /* Supervisor data access */ |
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switch(size) {
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case 1: |
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ret = ldub_kernel(T0); |
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break;
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case 2: |
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ret = lduw_kernel(T0 & ~1);
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break;
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default:
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case 4: |
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ret = ldl_kernel(T0 & ~3);
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break;
|
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case 8: |
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ret = ldl_kernel(T0 & ~3);
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T0 = ldl_kernel((T0 + 4) & ~3); |
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break;
|
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} |
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break;
|
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case 0xc: /* I-cache tag */ |
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case 0xd: /* I-cache data */ |
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case 0xe: /* D-cache tag */ |
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case 0xf: /* D-cache data */ |
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break;
|
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case 0x20: /* MMU passthrough */ |
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switch(size) {
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case 1: |
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ret = ldub_phys(T0); |
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break;
|
| 298 |
case 2: |
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ret = lduw_phys(T0 & ~1);
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break;
|
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default:
|
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case 4: |
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ret = ldl_phys(T0 & ~3);
|
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break;
|
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case 8: |
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ret = ldl_phys(T0 & ~3);
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T0 = ldl_phys((T0 + 4) & ~3); |
| 308 |
break;
|
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} |
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break;
|
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case 0x2e: /* MMU passthrough, 0xexxxxxxxx */ |
| 312 |
case 0x2f: /* MMU passthrough, 0xfxxxxxxxx */ |
| 313 |
switch(size) {
|
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case 1: |
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ret = ldub_phys((target_phys_addr_t)T0 |
| 316 |
| ((target_phys_addr_t)(asi & 0xf) << 32)); |
| 317 |
break;
|
| 318 |
case 2: |
| 319 |
ret = lduw_phys((target_phys_addr_t)(T0 & ~1)
|
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| ((target_phys_addr_t)(asi & 0xf) << 32)); |
| 321 |
break;
|
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default:
|
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case 4: |
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ret = ldl_phys((target_phys_addr_t)(T0 & ~3)
|
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| ((target_phys_addr_t)(asi & 0xf) << 32)); |
| 326 |
break;
|
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case 8: |
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ret = ldl_phys((target_phys_addr_t)(T0 & ~3)
|
| 329 |
| ((target_phys_addr_t)(asi & 0xf) << 32)); |
| 330 |
T0 = ldl_phys((target_phys_addr_t)((T0 + 4) & ~3) |
| 331 |
| ((target_phys_addr_t)(asi & 0xf) << 32)); |
| 332 |
break;
|
| 333 |
} |
| 334 |
break;
|
| 335 |
case 0x21 ... 0x2d: /* MMU passthrough, unassigned */ |
| 336 |
default:
|
| 337 |
do_unassigned_access(T0, 0, 0, 1); |
| 338 |
ret = 0;
|
| 339 |
break;
|
| 340 |
} |
| 341 |
if (sign) {
|
| 342 |
switch(size) {
|
| 343 |
case 1: |
| 344 |
T1 = (int8_t) ret; |
| 345 |
break;
|
| 346 |
case 2: |
| 347 |
T1 = (int16_t) ret; |
| 348 |
break;
|
| 349 |
default:
|
| 350 |
T1 = ret; |
| 351 |
break;
|
| 352 |
} |
| 353 |
} |
| 354 |
else
|
| 355 |
T1 = ret; |
| 356 |
} |
| 357 |
|
| 358 |
void helper_st_asi(int asi, int size) |
| 359 |
{
|
| 360 |
switch(asi) {
|
| 361 |
case 2: /* SuperSparc MXCC registers */ |
| 362 |
switch (T0) {
|
| 363 |
case 0x01c00000: /* MXCC stream data register 0 */ |
| 364 |
if (size == 8) |
| 365 |
env->mxccdata[0] = ((uint64_t)T1 << 32) | T2; |
| 366 |
else
|
| 367 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
|
| 368 |
break;
|
| 369 |
case 0x01c00008: /* MXCC stream data register 1 */ |
| 370 |
if (size == 8) |
| 371 |
env->mxccdata[1] = ((uint64_t)T1 << 32) | T2; |
| 372 |
else
|
| 373 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
|
| 374 |
break;
|
| 375 |
case 0x01c00010: /* MXCC stream data register 2 */ |
| 376 |
if (size == 8) |
| 377 |
env->mxccdata[2] = ((uint64_t)T1 << 32) | T2; |
| 378 |
else
|
| 379 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
|
| 380 |
break;
|
| 381 |
case 0x01c00018: /* MXCC stream data register 3 */ |
| 382 |
if (size == 8) |
| 383 |
env->mxccdata[3] = ((uint64_t)T1 << 32) | T2; |
| 384 |
else
|
| 385 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
|
| 386 |
break;
|
| 387 |
case 0x01c00100: /* MXCC stream source */ |
| 388 |
if (size == 8) |
| 389 |
env->mxccregs[0] = ((uint64_t)T1 << 32) | T2; |
| 390 |
else
|
| 391 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
|
| 392 |
env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 0); |
| 393 |
env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 8); |
| 394 |
env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 16); |
| 395 |
env->mxccdata[3] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 24); |
| 396 |
break;
|
| 397 |
case 0x01c00200: /* MXCC stream destination */ |
| 398 |
if (size == 8) |
| 399 |
env->mxccregs[1] = ((uint64_t)T1 << 32) | T2; |
| 400 |
else
|
| 401 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
|
| 402 |
stq_phys((env->mxccregs[1] & 0xffffffffULL) + 0, env->mxccdata[0]); |
| 403 |
stq_phys((env->mxccregs[1] & 0xffffffffULL) + 8, env->mxccdata[1]); |
| 404 |
stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16, env->mxccdata[2]); |
| 405 |
stq_phys((env->mxccregs[1] & 0xffffffffULL) + 24, env->mxccdata[3]); |
| 406 |
break;
|
| 407 |
case 0x01c00a00: /* MXCC control register */ |
| 408 |
if (size == 8) |
| 409 |
env->mxccregs[3] = ((uint64_t)T1 << 32) | T2; |
| 410 |
else
|
| 411 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
|
| 412 |
break;
|
| 413 |
case 0x01c00a04: /* MXCC control register */ |
| 414 |
if (size == 4) |
| 415 |
env->mxccregs[3] = (env->mxccregs[0xa] & 0xffffffff00000000) | T1; |
| 416 |
else
|
| 417 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
|
| 418 |
break;
|
| 419 |
case 0x01c00e00: /* MXCC error register */ |
| 420 |
if (size == 8) |
| 421 |
env->mxccregs[6] = ((uint64_t)T1 << 32) | T2; |
| 422 |
else
|
| 423 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
|
| 424 |
if (env->mxccregs[6] == 0xffffffffffffffffULL) { |
| 425 |
// this is probably a reset
|
| 426 |
} |
| 427 |
break;
|
| 428 |
case 0x01c00f00: /* MBus port address register */ |
| 429 |
if (size == 8) |
| 430 |
env->mxccregs[7] = ((uint64_t)T1 << 32) | T2; |
| 431 |
else
|
| 432 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
|
| 433 |
break;
|
| 434 |
default:
|
| 435 |
DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", T0, size);
|
| 436 |
break;
|
| 437 |
} |
| 438 |
DPRINTF_MXCC("asi = %d, size = %d, T0 = %08x, T1 = %08x\n", asi, size, T0, T1);
|
| 439 |
#ifdef DEBUG_MXCC
|
| 440 |
dump_mxcc(env); |
| 441 |
#endif
|
| 442 |
break;
|
| 443 |
case 3: /* MMU flush */ |
| 444 |
{
|
| 445 |
int mmulev;
|
| 446 |
|
| 447 |
mmulev = (T0 >> 8) & 15; |
| 448 |
DPRINTF_MMU("mmu flush level %d\n", mmulev);
|
| 449 |
switch (mmulev) {
|
| 450 |
case 0: // flush page |
| 451 |
tlb_flush_page(env, T0 & 0xfffff000);
|
| 452 |
break;
|
| 453 |
case 1: // flush segment (256k) |
| 454 |
case 2: // flush region (16M) |
| 455 |
case 3: // flush context (4G) |
| 456 |
case 4: // flush entire |
| 457 |
tlb_flush(env, 1);
|
| 458 |
break;
|
| 459 |
default:
|
| 460 |
break;
|
| 461 |
} |
| 462 |
#ifdef DEBUG_MMU
|
| 463 |
dump_mmu(env); |
| 464 |
#endif
|
| 465 |
return;
|
| 466 |
} |
| 467 |
case 4: /* write MMU regs */ |
| 468 |
{
|
| 469 |
int reg = (T0 >> 8) & 0xf; |
| 470 |
uint32_t oldreg; |
| 471 |
|
| 472 |
oldreg = env->mmuregs[reg]; |
| 473 |
switch(reg) {
|
| 474 |
case 0: |
| 475 |
env->mmuregs[reg] &= ~(MMU_E | MMU_NF | MMU_BM); |
| 476 |
env->mmuregs[reg] |= T1 & (MMU_E | MMU_NF | MMU_BM); |
| 477 |
// Mappings generated during no-fault mode or MMU
|
| 478 |
// disabled mode are invalid in normal mode
|
| 479 |
if (oldreg != env->mmuregs[reg])
|
| 480 |
tlb_flush(env, 1);
|
| 481 |
break;
|
| 482 |
case 2: |
| 483 |
env->mmuregs[reg] = T1; |
| 484 |
if (oldreg != env->mmuregs[reg]) {
|
| 485 |
/* we flush when the MMU context changes because
|
| 486 |
QEMU has no MMU context support */
|
| 487 |
tlb_flush(env, 1);
|
| 488 |
} |
| 489 |
break;
|
| 490 |
case 3: |
| 491 |
case 4: |
| 492 |
break;
|
| 493 |
default:
|
| 494 |
env->mmuregs[reg] = T1; |
| 495 |
break;
|
| 496 |
} |
| 497 |
if (oldreg != env->mmuregs[reg]) {
|
| 498 |
DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n", reg, oldreg, env->mmuregs[reg]);
|
| 499 |
} |
| 500 |
#ifdef DEBUG_MMU
|
| 501 |
dump_mmu(env); |
| 502 |
#endif
|
| 503 |
return;
|
| 504 |
} |
| 505 |
case 0xa: /* User data access */ |
| 506 |
switch(size) {
|
| 507 |
case 1: |
| 508 |
stb_user(T0, T1); |
| 509 |
break;
|
| 510 |
case 2: |
| 511 |
stw_user(T0 & ~1, T1);
|
| 512 |
break;
|
| 513 |
default:
|
| 514 |
case 4: |
| 515 |
stl_user(T0 & ~3, T1);
|
| 516 |
break;
|
| 517 |
case 8: |
| 518 |
stl_user(T0 & ~3, T1);
|
| 519 |
stl_user((T0 + 4) & ~3, T2); |
| 520 |
break;
|
| 521 |
} |
| 522 |
break;
|
| 523 |
case 0xb: /* Supervisor data access */ |
| 524 |
switch(size) {
|
| 525 |
case 1: |
| 526 |
stb_kernel(T0, T1); |
| 527 |
break;
|
| 528 |
case 2: |
| 529 |
stw_kernel(T0 & ~1, T1);
|
| 530 |
break;
|
| 531 |
default:
|
| 532 |
case 4: |
| 533 |
stl_kernel(T0 & ~3, T1);
|
| 534 |
break;
|
| 535 |
case 8: |
| 536 |
stl_kernel(T0 & ~3, T1);
|
| 537 |
stl_kernel((T0 + 4) & ~3, T2); |
| 538 |
break;
|
| 539 |
} |
| 540 |
break;
|
| 541 |
case 0xc: /* I-cache tag */ |
| 542 |
case 0xd: /* I-cache data */ |
| 543 |
case 0xe: /* D-cache tag */ |
| 544 |
case 0xf: /* D-cache data */ |
| 545 |
case 0x10: /* I/D-cache flush page */ |
| 546 |
case 0x11: /* I/D-cache flush segment */ |
| 547 |
case 0x12: /* I/D-cache flush region */ |
| 548 |
case 0x13: /* I/D-cache flush context */ |
| 549 |
case 0x14: /* I/D-cache flush user */ |
| 550 |
break;
|
| 551 |
case 0x17: /* Block copy, sta access */ |
| 552 |
{
|
| 553 |
// value (T1) = src
|
| 554 |
// address (T0) = dst
|
| 555 |
// copy 32 bytes
|
| 556 |
unsigned int i; |
| 557 |
uint32_t src = T1 & ~3, dst = T0 & ~3, temp; |
| 558 |
|
| 559 |
for (i = 0; i < 32; i += 4, src += 4, dst += 4) { |
| 560 |
temp = ldl_kernel(src); |
| 561 |
stl_kernel(dst, temp); |
| 562 |
} |
| 563 |
} |
| 564 |
return;
|
| 565 |
case 0x1f: /* Block fill, stda access */ |
| 566 |
{
|
| 567 |
// value (T1, T2)
|
| 568 |
// address (T0) = dst
|
| 569 |
// fill 32 bytes
|
| 570 |
unsigned int i; |
| 571 |
uint32_t dst = T0 & 7;
|
| 572 |
uint64_t val; |
| 573 |
|
| 574 |
val = (((uint64_t)T1) << 32) | T2;
|
| 575 |
|
| 576 |
for (i = 0; i < 32; i += 8, dst += 8) |
| 577 |
stq_kernel(dst, val); |
| 578 |
} |
| 579 |
return;
|
| 580 |
case 0x20: /* MMU passthrough */ |
| 581 |
{
|
| 582 |
switch(size) {
|
| 583 |
case 1: |
| 584 |
stb_phys(T0, T1); |
| 585 |
break;
|
| 586 |
case 2: |
| 587 |
stw_phys(T0 & ~1, T1);
|
| 588 |
break;
|
| 589 |
case 4: |
| 590 |
default:
|
| 591 |
stl_phys(T0 & ~3, T1);
|
| 592 |
break;
|
| 593 |
case 8: |
| 594 |
stl_phys(T0 & ~3, T1);
|
| 595 |
stl_phys((T0 + 4) & ~3, T2); |
| 596 |
break;
|
| 597 |
} |
| 598 |
} |
| 599 |
return;
|
| 600 |
case 0x2e: /* MMU passthrough, 0xexxxxxxxx */ |
| 601 |
case 0x2f: /* MMU passthrough, 0xfxxxxxxxx */ |
| 602 |
{
|
| 603 |
switch(size) {
|
| 604 |
case 1: |
| 605 |
stb_phys((target_phys_addr_t)T0 |
| 606 |
| ((target_phys_addr_t)(asi & 0xf) << 32), T1); |
| 607 |
break;
|
| 608 |
case 2: |
| 609 |
stw_phys((target_phys_addr_t)(T0 & ~1)
|
| 610 |
| ((target_phys_addr_t)(asi & 0xf) << 32), T1); |
| 611 |
break;
|
| 612 |
case 4: |
| 613 |
default:
|
| 614 |
stl_phys((target_phys_addr_t)(T0 & ~3)
|
| 615 |
| ((target_phys_addr_t)(asi & 0xf) << 32), T1); |
| 616 |
break;
|
| 617 |
case 8: |
| 618 |
stl_phys((target_phys_addr_t)(T0 & ~3)
|
| 619 |
| ((target_phys_addr_t)(asi & 0xf) << 32), T1); |
| 620 |
stl_phys((target_phys_addr_t)((T0 + 4) & ~3) |
| 621 |
| ((target_phys_addr_t)(asi & 0xf) << 32), T1); |
| 622 |
break;
|
| 623 |
} |
| 624 |
} |
| 625 |
return;
|
| 626 |
case 0x31: /* Ross RT620 I-cache flush */ |
| 627 |
case 0x36: /* I-cache flash clear */ |
| 628 |
case 0x37: /* D-cache flash clear */ |
| 629 |
break;
|
| 630 |
case 9: /* Supervisor code access, XXX */ |
| 631 |
case 0x21 ... 0x2d: /* MMU passthrough, unassigned */ |
| 632 |
default:
|
| 633 |
do_unassigned_access(T0, 1, 0, 1); |
| 634 |
return;
|
| 635 |
} |
| 636 |
} |
| 637 |
|
| 638 |
#endif /* CONFIG_USER_ONLY */ |
| 639 |
#else /* TARGET_SPARC64 */ |
| 640 |
|
| 641 |
#ifdef CONFIG_USER_ONLY
|
| 642 |
void helper_ld_asi(int asi, int size, int sign) |
| 643 |
{
|
| 644 |
uint64_t ret = 0;
|
| 645 |
|
| 646 |
if (asi < 0x80) |
| 647 |
raise_exception(TT_PRIV_ACT); |
| 648 |
|
| 649 |
switch (asi) {
|
| 650 |
case 0x80: // Primary |
| 651 |
case 0x82: // Primary no-fault |
| 652 |
case 0x88: // Primary LE |
| 653 |
case 0x8a: // Primary no-fault LE |
| 654 |
{
|
| 655 |
switch(size) {
|
| 656 |
case 1: |
| 657 |
ret = ldub_raw(T0); |
| 658 |
break;
|
| 659 |
case 2: |
| 660 |
ret = lduw_raw(T0 & ~1);
|
| 661 |
break;
|
| 662 |
case 4: |
| 663 |
ret = ldl_raw(T0 & ~3);
|
| 664 |
break;
|
| 665 |
default:
|
| 666 |
case 8: |
| 667 |
ret = ldq_raw(T0 & ~7);
|
| 668 |
break;
|
| 669 |
} |
| 670 |
} |
| 671 |
break;
|
| 672 |
case 0x81: // Secondary |
| 673 |
case 0x83: // Secondary no-fault |
| 674 |
case 0x89: // Secondary LE |
| 675 |
case 0x8b: // Secondary no-fault LE |
| 676 |
// XXX
|
| 677 |
break;
|
| 678 |
default:
|
| 679 |
break;
|
| 680 |
} |
| 681 |
|
| 682 |
/* Convert from little endian */
|
| 683 |
switch (asi) {
|
| 684 |
case 0x88: // Primary LE |
| 685 |
case 0x89: // Secondary LE |
| 686 |
case 0x8a: // Primary no-fault LE |
| 687 |
case 0x8b: // Secondary no-fault LE |
| 688 |
switch(size) {
|
| 689 |
case 2: |
| 690 |
ret = bswap16(ret); |
| 691 |
break;
|
| 692 |
case 4: |
| 693 |
ret = bswap32(ret); |
| 694 |
break;
|
| 695 |
case 8: |
| 696 |
ret = bswap64(ret); |
| 697 |
break;
|
| 698 |
default:
|
| 699 |
break;
|
| 700 |
} |
| 701 |
default:
|
| 702 |
break;
|
| 703 |
} |
| 704 |
|
| 705 |
/* Convert to signed number */
|
| 706 |
if (sign) {
|
| 707 |
switch(size) {
|
| 708 |
case 1: |
| 709 |
ret = (int8_t) ret; |
| 710 |
break;
|
| 711 |
case 2: |
| 712 |
ret = (int16_t) ret; |
| 713 |
break;
|
| 714 |
case 4: |
| 715 |
ret = (int32_t) ret; |
| 716 |
break;
|
| 717 |
default:
|
| 718 |
break;
|
| 719 |
} |
| 720 |
} |
| 721 |
T1 = ret; |
| 722 |
} |
| 723 |
|
| 724 |
void helper_st_asi(int asi, int size) |
| 725 |
{
|
| 726 |
if (asi < 0x80) |
| 727 |
raise_exception(TT_PRIV_ACT); |
| 728 |
|
| 729 |
/* Convert to little endian */
|
| 730 |
switch (asi) {
|
| 731 |
case 0x88: // Primary LE |
| 732 |
case 0x89: // Secondary LE |
| 733 |
switch(size) {
|
| 734 |
case 2: |
| 735 |
T0 = bswap16(T0); |
| 736 |
break;
|
| 737 |
case 4: |
| 738 |
T0 = bswap32(T0); |
| 739 |
break;
|
| 740 |
case 8: |
| 741 |
T0 = bswap64(T0); |
| 742 |
break;
|
| 743 |
default:
|
| 744 |
break;
|
| 745 |
} |
| 746 |
default:
|
| 747 |
break;
|
| 748 |
} |
| 749 |
|
| 750 |
switch(asi) {
|
| 751 |
case 0x80: // Primary |
| 752 |
case 0x88: // Primary LE |
| 753 |
{
|
| 754 |
switch(size) {
|
| 755 |
case 1: |
| 756 |
stb_raw(T0, T1); |
| 757 |
break;
|
| 758 |
case 2: |
| 759 |
stw_raw(T0 & ~1, T1);
|
| 760 |
break;
|
| 761 |
case 4: |
| 762 |
stl_raw(T0 & ~3, T1);
|
| 763 |
break;
|
| 764 |
case 8: |
| 765 |
default:
|
| 766 |
stq_raw(T0 & ~7, T1);
|
| 767 |
break;
|
| 768 |
} |
| 769 |
} |
| 770 |
break;
|
| 771 |
case 0x81: // Secondary |
| 772 |
case 0x89: // Secondary LE |
| 773 |
// XXX
|
| 774 |
return;
|
| 775 |
|
| 776 |
case 0x82: // Primary no-fault, RO |
| 777 |
case 0x83: // Secondary no-fault, RO |
| 778 |
case 0x8a: // Primary no-fault LE, RO |
| 779 |
case 0x8b: // Secondary no-fault LE, RO |
| 780 |
default:
|
| 781 |
do_unassigned_access(T0, 1, 0, 1); |
| 782 |
return;
|
| 783 |
} |
| 784 |
} |
| 785 |
|
| 786 |
#else /* CONFIG_USER_ONLY */ |
| 787 |
|
| 788 |
void helper_ld_asi(int asi, int size, int sign) |
| 789 |
{
|
| 790 |
uint64_t ret = 0;
|
| 791 |
|
| 792 |
if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0) |
| 793 |
|| (asi >= 0x30 && asi < 0x80) && !(env->hpstate & HS_PRIV)) |
| 794 |
raise_exception(TT_PRIV_ACT); |
| 795 |
|
| 796 |
switch (asi) {
|
| 797 |
case 0x10: // As if user primary |
| 798 |
case 0x18: // As if user primary LE |
| 799 |
case 0x80: // Primary |
| 800 |
case 0x82: // Primary no-fault |
| 801 |
case 0x88: // Primary LE |
| 802 |
case 0x8a: // Primary no-fault LE |
| 803 |
if ((asi & 0x80) && (env->pstate & PS_PRIV)) { |
| 804 |
if (env->hpstate & HS_PRIV) {
|
| 805 |
switch(size) {
|
| 806 |
case 1: |
| 807 |
ret = ldub_hypv(T0); |
| 808 |
break;
|
| 809 |
case 2: |
| 810 |
ret = lduw_hypv(T0 & ~1);
|
| 811 |
break;
|
| 812 |
case 4: |
| 813 |
ret = ldl_hypv(T0 & ~3);
|
| 814 |
break;
|
| 815 |
default:
|
| 816 |
case 8: |
| 817 |
ret = ldq_hypv(T0 & ~7);
|
| 818 |
break;
|
| 819 |
} |
| 820 |
} else {
|
| 821 |
switch(size) {
|
| 822 |
case 1: |
| 823 |
ret = ldub_kernel(T0); |
| 824 |
break;
|
| 825 |
case 2: |
| 826 |
ret = lduw_kernel(T0 & ~1);
|
| 827 |
break;
|
| 828 |
case 4: |
| 829 |
ret = ldl_kernel(T0 & ~3);
|
| 830 |
break;
|
| 831 |
default:
|
| 832 |
case 8: |
| 833 |
ret = ldq_kernel(T0 & ~7);
|
| 834 |
break;
|
| 835 |
} |
| 836 |
} |
| 837 |
} else {
|
| 838 |
switch(size) {
|
| 839 |
case 1: |
| 840 |
ret = ldub_user(T0); |
| 841 |
break;
|
| 842 |
case 2: |
| 843 |
ret = lduw_user(T0 & ~1);
|
| 844 |
break;
|
| 845 |
case 4: |
| 846 |
ret = ldl_user(T0 & ~3);
|
| 847 |
break;
|
| 848 |
default:
|
| 849 |
case 8: |
| 850 |
ret = ldq_user(T0 & ~7);
|
| 851 |
break;
|
| 852 |
} |
| 853 |
} |
| 854 |
break;
|
| 855 |
case 0x14: // Bypass |
| 856 |
case 0x15: // Bypass, non-cacheable |
| 857 |
case 0x1c: // Bypass LE |
| 858 |
case 0x1d: // Bypass, non-cacheable LE |
| 859 |
{
|
| 860 |
switch(size) {
|
| 861 |
case 1: |
| 862 |
ret = ldub_phys(T0); |
| 863 |
break;
|
| 864 |
case 2: |
| 865 |
ret = lduw_phys(T0 & ~1);
|
| 866 |
break;
|
| 867 |
case 4: |
| 868 |
ret = ldl_phys(T0 & ~3);
|
| 869 |
break;
|
| 870 |
default:
|
| 871 |
case 8: |
| 872 |
ret = ldq_phys(T0 & ~7);
|
| 873 |
break;
|
| 874 |
} |
| 875 |
break;
|
| 876 |
} |
| 877 |
case 0x04: // Nucleus |
| 878 |
case 0x0c: // Nucleus Little Endian (LE) |
| 879 |
case 0x11: // As if user secondary |
| 880 |
case 0x19: // As if user secondary LE |
| 881 |
case 0x24: // Nucleus quad LDD 128 bit atomic |
| 882 |
case 0x2c: // Nucleus quad LDD 128 bit atomic |
| 883 |
case 0x4a: // UPA config |
| 884 |
case 0x81: // Secondary |
| 885 |
case 0x83: // Secondary no-fault |
| 886 |
case 0x89: // Secondary LE |
| 887 |
case 0x8b: // Secondary no-fault LE |
| 888 |
// XXX
|
| 889 |
break;
|
| 890 |
case 0x45: // LSU |
| 891 |
ret = env->lsu; |
| 892 |
break;
|
| 893 |
case 0x50: // I-MMU regs |
| 894 |
{
|
| 895 |
int reg = (T0 >> 3) & 0xf; |
| 896 |
|
| 897 |
ret = env->immuregs[reg]; |
| 898 |
break;
|
| 899 |
} |
| 900 |
case 0x51: // I-MMU 8k TSB pointer |
| 901 |
case 0x52: // I-MMU 64k TSB pointer |
| 902 |
case 0x55: // I-MMU data access |
| 903 |
// XXX
|
| 904 |
break;
|
| 905 |
case 0x56: // I-MMU tag read |
| 906 |
{
|
| 907 |
unsigned int i; |
| 908 |
|
| 909 |
for (i = 0; i < 64; i++) { |
| 910 |
// Valid, ctx match, vaddr match
|
| 911 |
if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0 && |
| 912 |
env->itlb_tag[i] == T0) {
|
| 913 |
ret = env->itlb_tag[i]; |
| 914 |
break;
|
| 915 |
} |
| 916 |
} |
| 917 |
break;
|
| 918 |
} |
| 919 |
case 0x58: // D-MMU regs |
| 920 |
{
|
| 921 |
int reg = (T0 >> 3) & 0xf; |
| 922 |
|
| 923 |
ret = env->dmmuregs[reg]; |
| 924 |
break;
|
| 925 |
} |
| 926 |
case 0x5e: // D-MMU tag read |
| 927 |
{
|
| 928 |
unsigned int i; |
| 929 |
|
| 930 |
for (i = 0; i < 64; i++) { |
| 931 |
// Valid, ctx match, vaddr match
|
| 932 |
if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0 && |
| 933 |
env->dtlb_tag[i] == T0) {
|
| 934 |
ret = env->dtlb_tag[i]; |
| 935 |
break;
|
| 936 |
} |
| 937 |
} |
| 938 |
break;
|
| 939 |
} |
| 940 |
case 0x59: // D-MMU 8k TSB pointer |
| 941 |
case 0x5a: // D-MMU 64k TSB pointer |
| 942 |
case 0x5b: // D-MMU data pointer |
| 943 |
case 0x5d: // D-MMU data access |
| 944 |
case 0x48: // Interrupt dispatch, RO |
| 945 |
case 0x49: // Interrupt data receive |
| 946 |
case 0x7f: // Incoming interrupt vector, RO |
| 947 |
// XXX
|
| 948 |
break;
|
| 949 |
case 0x54: // I-MMU data in, WO |
| 950 |
case 0x57: // I-MMU demap, WO |
| 951 |
case 0x5c: // D-MMU data in, WO |
| 952 |
case 0x5f: // D-MMU demap, WO |
| 953 |
case 0x77: // Interrupt vector, WO |
| 954 |
default:
|
| 955 |
do_unassigned_access(T0, 0, 0, 1); |
| 956 |
ret = 0;
|
| 957 |
break;
|
| 958 |
} |
| 959 |
|
| 960 |
/* Convert from little endian */
|
| 961 |
switch (asi) {
|
| 962 |
case 0x0c: // Nucleus Little Endian (LE) |
| 963 |
case 0x18: // As if user primary LE |
| 964 |
case 0x19: // As if user secondary LE |
| 965 |
case 0x1c: // Bypass LE |
| 966 |
case 0x1d: // Bypass, non-cacheable LE |
| 967 |
case 0x88: // Primary LE |
| 968 |
case 0x89: // Secondary LE |
| 969 |
case 0x8a: // Primary no-fault LE |
| 970 |
case 0x8b: // Secondary no-fault LE |
| 971 |
switch(size) {
|
| 972 |
case 2: |
| 973 |
ret = bswap16(ret); |
| 974 |
break;
|
| 975 |
case 4: |
| 976 |
ret = bswap32(ret); |
| 977 |
break;
|
| 978 |
case 8: |
| 979 |
ret = bswap64(ret); |
| 980 |
break;
|
| 981 |
default:
|
| 982 |
break;
|
| 983 |
} |
| 984 |
default:
|
| 985 |
break;
|
| 986 |
} |
| 987 |
|
| 988 |
/* Convert to signed number */
|
| 989 |
if (sign) {
|
| 990 |
switch(size) {
|
| 991 |
case 1: |
| 992 |
ret = (int8_t) ret; |
| 993 |
break;
|
| 994 |
case 2: |
| 995 |
ret = (int16_t) ret; |
| 996 |
break;
|
| 997 |
case 4: |
| 998 |
ret = (int32_t) ret; |
| 999 |
break;
|
| 1000 |
default:
|
| 1001 |
break;
|
| 1002 |
} |
| 1003 |
} |
| 1004 |
T1 = ret; |
| 1005 |
} |
| 1006 |
|
| 1007 |
void helper_st_asi(int asi, int size) |
| 1008 |
{
|
| 1009 |
if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0) |
| 1010 |
|| (asi >= 0x30 && asi < 0x80) && !(env->hpstate & HS_PRIV)) |
| 1011 |
raise_exception(TT_PRIV_ACT); |
| 1012 |
|
| 1013 |
/* Convert to little endian */
|
| 1014 |
switch (asi) {
|
| 1015 |
case 0x0c: // Nucleus Little Endian (LE) |
| 1016 |
case 0x18: // As if user primary LE |
| 1017 |
case 0x19: // As if user secondary LE |
| 1018 |
case 0x1c: // Bypass LE |
| 1019 |
case 0x1d: // Bypass, non-cacheable LE |
| 1020 |
case 0x88: // Primary LE |
| 1021 |
case 0x89: // Secondary LE |
| 1022 |
switch(size) {
|
| 1023 |
case 2: |
| 1024 |
T0 = bswap16(T0); |
| 1025 |
break;
|
| 1026 |
case 4: |
| 1027 |
T0 = bswap32(T0); |
| 1028 |
break;
|
| 1029 |
case 8: |
| 1030 |
T0 = bswap64(T0); |
| 1031 |
break;
|
| 1032 |
default:
|
| 1033 |
break;
|
| 1034 |
} |
| 1035 |
default:
|
| 1036 |
break;
|
| 1037 |
} |
| 1038 |
|
| 1039 |
switch(asi) {
|
| 1040 |
case 0x10: // As if user primary |
| 1041 |
case 0x18: // As if user primary LE |
| 1042 |
case 0x80: // Primary |
| 1043 |
case 0x88: // Primary LE |
| 1044 |
if ((asi & 0x80) && (env->pstate & PS_PRIV)) { |
| 1045 |
if (env->hpstate & HS_PRIV) {
|
| 1046 |
switch(size) {
|
| 1047 |
case 1: |
| 1048 |
stb_hypv(T0, T1); |
| 1049 |
break;
|
| 1050 |
case 2: |
| 1051 |
stw_hypv(T0 & ~1, T1);
|
| 1052 |
break;
|
| 1053 |
case 4: |
| 1054 |
stl_hypv(T0 & ~3, T1);
|
| 1055 |
break;
|
| 1056 |
case 8: |
| 1057 |
default:
|
| 1058 |
stq_hypv(T0 & ~7, T1);
|
| 1059 |
break;
|
| 1060 |
} |
| 1061 |
} else {
|
| 1062 |
switch(size) {
|
| 1063 |
case 1: |
| 1064 |
stb_kernel(T0, T1); |
| 1065 |
break;
|
| 1066 |
case 2: |
| 1067 |
stw_kernel(T0 & ~1, T1);
|
| 1068 |
break;
|
| 1069 |
case 4: |
| 1070 |
stl_kernel(T0 & ~3, T1);
|
| 1071 |
break;
|
| 1072 |
case 8: |
| 1073 |
default:
|
| 1074 |
stq_kernel(T0 & ~7, T1);
|
| 1075 |
break;
|
| 1076 |
} |
| 1077 |
} |
| 1078 |
} else {
|
| 1079 |
switch(size) {
|
| 1080 |
case 1: |
| 1081 |
stb_user(T0, T1); |
| 1082 |
break;
|
| 1083 |
case 2: |
| 1084 |
stw_user(T0 & ~1, T1);
|
| 1085 |
break;
|
| 1086 |
case 4: |
| 1087 |
stl_user(T0 & ~3, T1);
|
| 1088 |
break;
|
| 1089 |
case 8: |
| 1090 |
default:
|
| 1091 |
stq_user(T0 & ~7, T1);
|
| 1092 |
break;
|
| 1093 |
} |
| 1094 |
} |
| 1095 |
break;
|
| 1096 |
case 0x14: // Bypass |
| 1097 |
case 0x15: // Bypass, non-cacheable |
| 1098 |
case 0x1c: // Bypass LE |
| 1099 |
case 0x1d: // Bypass, non-cacheable LE |
| 1100 |
{
|
| 1101 |
switch(size) {
|
| 1102 |
case 1: |
| 1103 |
stb_phys(T0, T1); |
| 1104 |
break;
|
| 1105 |
case 2: |
| 1106 |
stw_phys(T0 & ~1, T1);
|
| 1107 |
break;
|
| 1108 |
case 4: |
| 1109 |
stl_phys(T0 & ~3, T1);
|
| 1110 |
break;
|
| 1111 |
case 8: |
| 1112 |
default:
|
| 1113 |
stq_phys(T0 & ~7, T1);
|
| 1114 |
break;
|
| 1115 |
} |
| 1116 |
} |
| 1117 |
return;
|
| 1118 |
case 0x04: // Nucleus |
| 1119 |
case 0x0c: // Nucleus Little Endian (LE) |
| 1120 |
case 0x11: // As if user secondary |
| 1121 |
case 0x19: // As if user secondary LE |
| 1122 |
case 0x24: // Nucleus quad LDD 128 bit atomic |
| 1123 |
case 0x2c: // Nucleus quad LDD 128 bit atomic |
| 1124 |
case 0x4a: // UPA config |
| 1125 |
case 0x81: // Secondary |
| 1126 |
case 0x89: // Secondary LE |
| 1127 |
// XXX
|
| 1128 |
return;
|
| 1129 |
case 0x45: // LSU |
| 1130 |
{
|
| 1131 |
uint64_t oldreg; |
| 1132 |
|
| 1133 |
oldreg = env->lsu; |
| 1134 |
env->lsu = T1 & (DMMU_E | IMMU_E); |
| 1135 |
// Mappings generated during D/I MMU disabled mode are
|
| 1136 |
// invalid in normal mode
|
| 1137 |
if (oldreg != env->lsu) {
|
| 1138 |
DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n", oldreg, env->lsu); |
| 1139 |
#ifdef DEBUG_MMU
|
| 1140 |
dump_mmu(env); |
| 1141 |
#endif
|
| 1142 |
tlb_flush(env, 1);
|
| 1143 |
} |
| 1144 |
return;
|
| 1145 |
} |
| 1146 |
case 0x50: // I-MMU regs |
| 1147 |
{
|
| 1148 |
int reg = (T0 >> 3) & 0xf; |
| 1149 |
uint64_t oldreg; |
| 1150 |
|
| 1151 |
oldreg = env->immuregs[reg]; |
| 1152 |
switch(reg) {
|
| 1153 |
case 0: // RO |
| 1154 |
case 4: |
| 1155 |
return;
|
| 1156 |
case 1: // Not in I-MMU |
| 1157 |
case 2: |
| 1158 |
case 7: |
| 1159 |
case 8: |
| 1160 |
return;
|
| 1161 |
case 3: // SFSR |
| 1162 |
if ((T1 & 1) == 0) |
| 1163 |
T1 = 0; // Clear SFSR |
| 1164 |
break;
|
| 1165 |
case 5: // TSB access |
| 1166 |
case 6: // Tag access |
| 1167 |
default:
|
| 1168 |
break;
|
| 1169 |
} |
| 1170 |
env->immuregs[reg] = T1; |
| 1171 |
if (oldreg != env->immuregs[reg]) {
|
| 1172 |
DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->immuregs[reg]); |
| 1173 |
} |
| 1174 |
#ifdef DEBUG_MMU
|
| 1175 |
dump_mmu(env); |
| 1176 |
#endif
|
| 1177 |
return;
|
| 1178 |
} |
| 1179 |
case 0x54: // I-MMU data in |
| 1180 |
{
|
| 1181 |
unsigned int i; |
| 1182 |
|
| 1183 |
// Try finding an invalid entry
|
| 1184 |
for (i = 0; i < 64; i++) { |
| 1185 |
if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0) { |
| 1186 |
env->itlb_tag[i] = env->immuregs[6];
|
| 1187 |
env->itlb_tte[i] = T1; |
| 1188 |
return;
|
| 1189 |
} |
| 1190 |
} |
| 1191 |
// Try finding an unlocked entry
|
| 1192 |
for (i = 0; i < 64; i++) { |
| 1193 |
if ((env->itlb_tte[i] & 0x40) == 0) { |
| 1194 |
env->itlb_tag[i] = env->immuregs[6];
|
| 1195 |
env->itlb_tte[i] = T1; |
| 1196 |
return;
|
| 1197 |
} |
| 1198 |
} |
| 1199 |
// error state?
|
| 1200 |
return;
|
| 1201 |
} |
| 1202 |
case 0x55: // I-MMU data access |
| 1203 |
{
|
| 1204 |
unsigned int i = (T0 >> 3) & 0x3f; |
| 1205 |
|
| 1206 |
env->itlb_tag[i] = env->immuregs[6];
|
| 1207 |
env->itlb_tte[i] = T1; |
| 1208 |
return;
|
| 1209 |
} |
| 1210 |
case 0x57: // I-MMU demap |
| 1211 |
// XXX
|
| 1212 |
return;
|
| 1213 |
case 0x58: // D-MMU regs |
| 1214 |
{
|
| 1215 |
int reg = (T0 >> 3) & 0xf; |
| 1216 |
uint64_t oldreg; |
| 1217 |
|
| 1218 |
oldreg = env->dmmuregs[reg]; |
| 1219 |
switch(reg) {
|
| 1220 |
case 0: // RO |
| 1221 |
case 4: |
| 1222 |
return;
|
| 1223 |
case 3: // SFSR |
| 1224 |
if ((T1 & 1) == 0) { |
| 1225 |
T1 = 0; // Clear SFSR, Fault address |
| 1226 |
env->dmmuregs[4] = 0; |
| 1227 |
} |
| 1228 |
env->dmmuregs[reg] = T1; |
| 1229 |
break;
|
| 1230 |
case 1: // Primary context |
| 1231 |
case 2: // Secondary context |
| 1232 |
case 5: // TSB access |
| 1233 |
case 6: // Tag access |
| 1234 |
case 7: // Virtual Watchpoint |
| 1235 |
case 8: // Physical Watchpoint |
| 1236 |
default:
|
| 1237 |
break;
|
| 1238 |
} |
| 1239 |
env->dmmuregs[reg] = T1; |
| 1240 |
if (oldreg != env->dmmuregs[reg]) {
|
| 1241 |
DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]); |
| 1242 |
} |
| 1243 |
#ifdef DEBUG_MMU
|
| 1244 |
dump_mmu(env); |
| 1245 |
#endif
|
| 1246 |
return;
|
| 1247 |
} |
| 1248 |
case 0x5c: // D-MMU data in |
| 1249 |
{
|
| 1250 |
unsigned int i; |
| 1251 |
|
| 1252 |
// Try finding an invalid entry
|
| 1253 |
for (i = 0; i < 64; i++) { |
| 1254 |
if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0) { |
| 1255 |
env->dtlb_tag[i] = env->dmmuregs[6];
|
| 1256 |
env->dtlb_tte[i] = T1; |
| 1257 |
return;
|
| 1258 |
} |
| 1259 |
} |
| 1260 |
// Try finding an unlocked entry
|
| 1261 |
for (i = 0; i < 64; i++) { |
| 1262 |
if ((env->dtlb_tte[i] & 0x40) == 0) { |
| 1263 |
env->dtlb_tag[i] = env->dmmuregs[6];
|
| 1264 |
env->dtlb_tte[i] = T1; |
| 1265 |
return;
|
| 1266 |
} |
| 1267 |
} |
| 1268 |
// error state?
|
| 1269 |
return;
|
| 1270 |
} |
| 1271 |
case 0x5d: // D-MMU data access |
| 1272 |
{
|
| 1273 |
unsigned int i = (T0 >> 3) & 0x3f; |
| 1274 |
|
| 1275 |
env->dtlb_tag[i] = env->dmmuregs[6];
|
| 1276 |
env->dtlb_tte[i] = T1; |
| 1277 |
return;
|
| 1278 |
} |
| 1279 |
case 0x5f: // D-MMU demap |
| 1280 |
case 0x49: // Interrupt data receive |
| 1281 |
// XXX
|
| 1282 |
return;
|
| 1283 |
case 0x51: // I-MMU 8k TSB pointer, RO |
| 1284 |
case 0x52: // I-MMU 64k TSB pointer, RO |
| 1285 |
case 0x56: // I-MMU tag read, RO |
| 1286 |
case 0x59: // D-MMU 8k TSB pointer, RO |
| 1287 |
case 0x5a: // D-MMU 64k TSB pointer, RO |
| 1288 |
case 0x5b: // D-MMU data pointer, RO |
| 1289 |
case 0x5e: // D-MMU tag read, RO |
| 1290 |
case 0x48: // Interrupt dispatch, RO |
| 1291 |
case 0x7f: // Incoming interrupt vector, RO |
| 1292 |
case 0x82: // Primary no-fault, RO |
| 1293 |
case 0x83: // Secondary no-fault, RO |
| 1294 |
case 0x8a: // Primary no-fault LE, RO |
| 1295 |
case 0x8b: // Secondary no-fault LE, RO |
| 1296 |
default:
|
| 1297 |
do_unassigned_access(T0, 1, 0, 1); |
| 1298 |
return;
|
| 1299 |
} |
| 1300 |
} |
| 1301 |
#endif /* CONFIG_USER_ONLY */ |
| 1302 |
|
| 1303 |
void helper_ldf_asi(int asi, int size, int rd) |
| 1304 |
{
|
| 1305 |
target_ulong tmp_T0 = T0, tmp_T1 = T1; |
| 1306 |
unsigned int i; |
| 1307 |
|
| 1308 |
switch (asi) {
|
| 1309 |
case 0xf0: // Block load primary |
| 1310 |
case 0xf1: // Block load secondary |
| 1311 |
case 0xf8: // Block load primary LE |
| 1312 |
case 0xf9: // Block load secondary LE |
| 1313 |
if (rd & 7) { |
| 1314 |
raise_exception(TT_ILL_INSN); |
| 1315 |
return;
|
| 1316 |
} |
| 1317 |
if (T0 & 0x3f) { |
| 1318 |
raise_exception(TT_UNALIGNED); |
| 1319 |
return;
|
| 1320 |
} |
| 1321 |
for (i = 0; i < 16; i++) { |
| 1322 |
helper_ld_asi(asi & 0x8f, 4, 0); |
| 1323 |
*(uint32_t *)&env->fpr[rd++] = T1; |
| 1324 |
T0 += 4;
|
| 1325 |
} |
| 1326 |
T0 = tmp_T0; |
| 1327 |
T1 = tmp_T1; |
| 1328 |
|
| 1329 |
return;
|
| 1330 |
default:
|
| 1331 |
break;
|
| 1332 |
} |
| 1333 |
|
| 1334 |
helper_ld_asi(asi, size, 0);
|
| 1335 |
switch(size) {
|
| 1336 |
default:
|
| 1337 |
case 4: |
| 1338 |
*((uint32_t *)&FT0) = T1; |
| 1339 |
break;
|
| 1340 |
case 8: |
| 1341 |
*((int64_t *)&DT0) = T1; |
| 1342 |
break;
|
| 1343 |
} |
| 1344 |
T1 = tmp_T1; |
| 1345 |
} |
| 1346 |
|
| 1347 |
void helper_stf_asi(int asi, int size, int rd) |
| 1348 |
{
|
| 1349 |
target_ulong tmp_T0 = T0, tmp_T1 = T1; |
| 1350 |
unsigned int i; |
| 1351 |
|
| 1352 |
switch (asi) {
|
| 1353 |
case 0xf0: // Block store primary |
| 1354 |
case 0xf1: // Block store secondary |
| 1355 |
case 0xf8: // Block store primary LE |
| 1356 |
case 0xf9: // Block store secondary LE |
| 1357 |
if (rd & 7) { |
| 1358 |
raise_exception(TT_ILL_INSN); |
| 1359 |
return;
|
| 1360 |
} |
| 1361 |
if (T0 & 0x3f) { |
| 1362 |
raise_exception(TT_UNALIGNED); |
| 1363 |
return;
|
| 1364 |
} |
| 1365 |
for (i = 0; i < 16; i++) { |
| 1366 |
T1 = *(uint32_t *)&env->fpr[rd++]; |
| 1367 |
helper_st_asi(asi & 0x8f, 4); |
| 1368 |
T0 += 4;
|
| 1369 |
} |
| 1370 |
T0 = tmp_T0; |
| 1371 |
T1 = tmp_T1; |
| 1372 |
|
| 1373 |
return;
|
| 1374 |
default:
|
| 1375 |
break;
|
| 1376 |
} |
| 1377 |
|
| 1378 |
switch(size) {
|
| 1379 |
default:
|
| 1380 |
case 4: |
| 1381 |
T1 = *((uint32_t *)&FT0); |
| 1382 |
break;
|
| 1383 |
case 8: |
| 1384 |
T1 = *((int64_t *)&DT0); |
| 1385 |
break;
|
| 1386 |
} |
| 1387 |
helper_st_asi(asi, size); |
| 1388 |
T1 = tmp_T1; |
| 1389 |
} |
| 1390 |
|
| 1391 |
#endif /* TARGET_SPARC64 */ |
| 1392 |
|
| 1393 |
#ifndef TARGET_SPARC64
|
| 1394 |
void helper_rett()
|
| 1395 |
{
|
| 1396 |
unsigned int cwp; |
| 1397 |
|
| 1398 |
if (env->psret == 1) |
| 1399 |
raise_exception(TT_ILL_INSN); |
| 1400 |
|
| 1401 |
env->psret = 1;
|
| 1402 |
cwp = (env->cwp + 1) & (NWINDOWS - 1); |
| 1403 |
if (env->wim & (1 << cwp)) { |
| 1404 |
raise_exception(TT_WIN_UNF); |
| 1405 |
} |
| 1406 |
set_cwp(cwp); |
| 1407 |
env->psrs = env->psrps; |
| 1408 |
} |
| 1409 |
#endif
|
| 1410 |
|
| 1411 |
void helper_ldfsr(void) |
| 1412 |
{
|
| 1413 |
int rnd_mode;
|
| 1414 |
switch (env->fsr & FSR_RD_MASK) {
|
| 1415 |
case FSR_RD_NEAREST:
|
| 1416 |
rnd_mode = float_round_nearest_even; |
| 1417 |
break;
|
| 1418 |
default:
|
| 1419 |
case FSR_RD_ZERO:
|
| 1420 |
rnd_mode = float_round_to_zero; |
| 1421 |
break;
|
| 1422 |
case FSR_RD_POS:
|
| 1423 |
rnd_mode = float_round_up; |
| 1424 |
break;
|
| 1425 |
case FSR_RD_NEG:
|
| 1426 |
rnd_mode = float_round_down; |
| 1427 |
break;
|
| 1428 |
} |
| 1429 |
set_float_rounding_mode(rnd_mode, &env->fp_status); |
| 1430 |
} |
| 1431 |
|
| 1432 |
void helper_debug()
|
| 1433 |
{
|
| 1434 |
env->exception_index = EXCP_DEBUG; |
| 1435 |
cpu_loop_exit(); |
| 1436 |
} |
| 1437 |
|
| 1438 |
#ifndef TARGET_SPARC64
|
| 1439 |
void do_wrpsr()
|
| 1440 |
{
|
| 1441 |
if ((T0 & PSR_CWP) >= NWINDOWS)
|
| 1442 |
raise_exception(TT_ILL_INSN); |
| 1443 |
else
|
| 1444 |
PUT_PSR(env, T0); |
| 1445 |
} |
| 1446 |
|
| 1447 |
void do_rdpsr()
|
| 1448 |
{
|
| 1449 |
T0 = GET_PSR(env); |
| 1450 |
} |
| 1451 |
|
| 1452 |
#else
|
| 1453 |
|
| 1454 |
void do_popc()
|
| 1455 |
{
|
| 1456 |
T0 = (T1 & 0x5555555555555555ULL) + ((T1 >> 1) & 0x5555555555555555ULL); |
| 1457 |
T0 = (T0 & 0x3333333333333333ULL) + ((T0 >> 2) & 0x3333333333333333ULL); |
| 1458 |
T0 = (T0 & 0x0f0f0f0f0f0f0f0fULL) + ((T0 >> 4) & 0x0f0f0f0f0f0f0f0fULL); |
| 1459 |
T0 = (T0 & 0x00ff00ff00ff00ffULL) + ((T0 >> 8) & 0x00ff00ff00ff00ffULL); |
| 1460 |
T0 = (T0 & 0x0000ffff0000ffffULL) + ((T0 >> 16) & 0x0000ffff0000ffffULL); |
| 1461 |
T0 = (T0 & 0x00000000ffffffffULL) + ((T0 >> 32) & 0x00000000ffffffffULL); |
| 1462 |
} |
| 1463 |
|
| 1464 |
static inline uint64_t *get_gregset(uint64_t pstate) |
| 1465 |
{
|
| 1466 |
switch (pstate) {
|
| 1467 |
default:
|
| 1468 |
case 0: |
| 1469 |
return env->bgregs;
|
| 1470 |
case PS_AG:
|
| 1471 |
return env->agregs;
|
| 1472 |
case PS_MG:
|
| 1473 |
return env->mgregs;
|
| 1474 |
case PS_IG:
|
| 1475 |
return env->igregs;
|
| 1476 |
} |
| 1477 |
} |
| 1478 |
|
| 1479 |
static inline void change_pstate(uint64_t new_pstate) |
| 1480 |
{
|
| 1481 |
uint64_t pstate_regs, new_pstate_regs; |
| 1482 |
uint64_t *src, *dst; |
| 1483 |
|
| 1484 |
pstate_regs = env->pstate & 0xc01;
|
| 1485 |
new_pstate_regs = new_pstate & 0xc01;
|
| 1486 |
if (new_pstate_regs != pstate_regs) {
|
| 1487 |
// Switch global register bank
|
| 1488 |
src = get_gregset(new_pstate_regs); |
| 1489 |
dst = get_gregset(pstate_regs); |
| 1490 |
memcpy32(dst, env->gregs); |
| 1491 |
memcpy32(env->gregs, src); |
| 1492 |
} |
| 1493 |
env->pstate = new_pstate; |
| 1494 |
} |
| 1495 |
|
| 1496 |
void do_wrpstate(void) |
| 1497 |
{
|
| 1498 |
change_pstate(T0 & 0xf3f);
|
| 1499 |
} |
| 1500 |
|
| 1501 |
void do_done(void) |
| 1502 |
{
|
| 1503 |
env->tl--; |
| 1504 |
env->pc = env->tnpc[env->tl]; |
| 1505 |
env->npc = env->tnpc[env->tl] + 4;
|
| 1506 |
PUT_CCR(env, env->tstate[env->tl] >> 32);
|
| 1507 |
env->asi = (env->tstate[env->tl] >> 24) & 0xff; |
| 1508 |
change_pstate((env->tstate[env->tl] >> 8) & 0xf3f); |
| 1509 |
PUT_CWP64(env, env->tstate[env->tl] & 0xff);
|
| 1510 |
} |
| 1511 |
|
| 1512 |
void do_retry(void) |
| 1513 |
{
|
| 1514 |
env->tl--; |
| 1515 |
env->pc = env->tpc[env->tl]; |
| 1516 |
env->npc = env->tnpc[env->tl]; |
| 1517 |
PUT_CCR(env, env->tstate[env->tl] >> 32);
|
| 1518 |
env->asi = (env->tstate[env->tl] >> 24) & 0xff; |
| 1519 |
change_pstate((env->tstate[env->tl] >> 8) & 0xf3f); |
| 1520 |
PUT_CWP64(env, env->tstate[env->tl] & 0xff);
|
| 1521 |
} |
| 1522 |
#endif
|
| 1523 |
|
| 1524 |
void set_cwp(int new_cwp) |
| 1525 |
{
|
| 1526 |
/* put the modified wrap registers at their proper location */
|
| 1527 |
if (env->cwp == (NWINDOWS - 1)) |
| 1528 |
memcpy32(env->regbase, env->regbase + NWINDOWS * 16);
|
| 1529 |
env->cwp = new_cwp; |
| 1530 |
/* put the wrap registers at their temporary location */
|
| 1531 |
if (new_cwp == (NWINDOWS - 1)) |
| 1532 |
memcpy32(env->regbase + NWINDOWS * 16, env->regbase);
|
| 1533 |
env->regwptr = env->regbase + (new_cwp * 16);
|
| 1534 |
REGWPTR = env->regwptr; |
| 1535 |
} |
| 1536 |
|
| 1537 |
void cpu_set_cwp(CPUState *env1, int new_cwp) |
| 1538 |
{
|
| 1539 |
CPUState *saved_env; |
| 1540 |
#ifdef reg_REGWPTR
|
| 1541 |
target_ulong *saved_regwptr; |
| 1542 |
#endif
|
| 1543 |
|
| 1544 |
saved_env = env; |
| 1545 |
#ifdef reg_REGWPTR
|
| 1546 |
saved_regwptr = REGWPTR; |
| 1547 |
#endif
|
| 1548 |
env = env1; |
| 1549 |
set_cwp(new_cwp); |
| 1550 |
env = saved_env; |
| 1551 |
#ifdef reg_REGWPTR
|
| 1552 |
REGWPTR = saved_regwptr; |
| 1553 |
#endif
|
| 1554 |
} |
| 1555 |
|
| 1556 |
#ifdef TARGET_SPARC64
|
| 1557 |
void do_interrupt(int intno) |
| 1558 |
{
|
| 1559 |
#ifdef DEBUG_PCALL
|
| 1560 |
if (loglevel & CPU_LOG_INT) {
|
| 1561 |
static int count; |
| 1562 |
fprintf(logfile, "%6d: v=%04x pc=%016" PRIx64 " npc=%016" PRIx64 " SP=%016" PRIx64 "\n", |
| 1563 |
count, intno, |
| 1564 |
env->pc, |
| 1565 |
env->npc, env->regwptr[6]);
|
| 1566 |
cpu_dump_state(env, logfile, fprintf, 0);
|
| 1567 |
#if 0
|
| 1568 |
{
|
| 1569 |
int i;
|
| 1570 |
uint8_t *ptr;
|
| 1571 |
|
| 1572 |
fprintf(logfile, " code=");
|
| 1573 |
ptr = (uint8_t *)env->pc;
|
| 1574 |
for(i = 0; i < 16; i++) {
|
| 1575 |
fprintf(logfile, " %02x", ldub(ptr + i));
|
| 1576 |
}
|
| 1577 |
fprintf(logfile, "\n");
|
| 1578 |
}
|
| 1579 |
#endif
|
| 1580 |
count++; |
| 1581 |
} |
| 1582 |
#endif
|
| 1583 |
#if !defined(CONFIG_USER_ONLY)
|
| 1584 |
if (env->tl == MAXTL) {
|
| 1585 |
cpu_abort(env, "Trap 0x%04x while trap level is MAXTL, Error state", env->exception_index);
|
| 1586 |
return;
|
| 1587 |
} |
| 1588 |
#endif
|
| 1589 |
env->tstate[env->tl] = ((uint64_t)GET_CCR(env) << 32) | ((env->asi & 0xff) << 24) | |
| 1590 |
((env->pstate & 0xf3f) << 8) | GET_CWP64(env); |
| 1591 |
env->tpc[env->tl] = env->pc; |
| 1592 |
env->tnpc[env->tl] = env->npc; |
| 1593 |
env->tt[env->tl] = intno; |
| 1594 |
change_pstate(PS_PEF | PS_PRIV | PS_AG); |
| 1595 |
|
| 1596 |
if (intno == TT_CLRWIN)
|
| 1597 |
set_cwp((env->cwp - 1) & (NWINDOWS - 1)); |
| 1598 |
else if ((intno & 0x1c0) == TT_SPILL) |
| 1599 |
set_cwp((env->cwp - env->cansave - 2) & (NWINDOWS - 1)); |
| 1600 |
else if ((intno & 0x1c0) == TT_FILL) |
| 1601 |
set_cwp((env->cwp + 1) & (NWINDOWS - 1)); |
| 1602 |
env->tbr &= ~0x7fffULL;
|
| 1603 |
env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5); |
| 1604 |
if (env->tl < MAXTL - 1) { |
| 1605 |
env->tl++; |
| 1606 |
} else {
|
| 1607 |
env->pstate |= PS_RED; |
| 1608 |
if (env->tl != MAXTL)
|
| 1609 |
env->tl++; |
| 1610 |
} |
| 1611 |
env->pc = env->tbr; |
| 1612 |
env->npc = env->pc + 4;
|
| 1613 |
env->exception_index = 0;
|
| 1614 |
} |
| 1615 |
#else
|
| 1616 |
void do_interrupt(int intno) |
| 1617 |
{
|
| 1618 |
int cwp;
|
| 1619 |
|
| 1620 |
#ifdef DEBUG_PCALL
|
| 1621 |
if (loglevel & CPU_LOG_INT) {
|
| 1622 |
static int count; |
| 1623 |
fprintf(logfile, "%6d: v=%02x pc=%08x npc=%08x SP=%08x\n",
|
| 1624 |
count, intno, |
| 1625 |
env->pc, |
| 1626 |
env->npc, env->regwptr[6]);
|
| 1627 |
cpu_dump_state(env, logfile, fprintf, 0);
|
| 1628 |
#if 0
|
| 1629 |
{
|
| 1630 |
int i;
|
| 1631 |
uint8_t *ptr;
|
| 1632 |
|
| 1633 |
fprintf(logfile, " code=");
|
| 1634 |
ptr = (uint8_t *)env->pc;
|
| 1635 |
for(i = 0; i < 16; i++) {
|
| 1636 |
fprintf(logfile, " %02x", ldub(ptr + i));
|
| 1637 |
}
|
| 1638 |
fprintf(logfile, "\n");
|
| 1639 |
}
|
| 1640 |
#endif
|
| 1641 |
count++; |
| 1642 |
} |
| 1643 |
#endif
|
| 1644 |
#if !defined(CONFIG_USER_ONLY)
|
| 1645 |
if (env->psret == 0) { |
| 1646 |
cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state", env->exception_index);
|
| 1647 |
return;
|
| 1648 |
} |
| 1649 |
#endif
|
| 1650 |
env->psret = 0;
|
| 1651 |
cwp = (env->cwp - 1) & (NWINDOWS - 1); |
| 1652 |
set_cwp(cwp); |
| 1653 |
env->regwptr[9] = env->pc;
|
| 1654 |
env->regwptr[10] = env->npc;
|
| 1655 |
env->psrps = env->psrs; |
| 1656 |
env->psrs = 1;
|
| 1657 |
env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
|
| 1658 |
env->pc = env->tbr; |
| 1659 |
env->npc = env->pc + 4;
|
| 1660 |
env->exception_index = 0;
|
| 1661 |
} |
| 1662 |
#endif
|
| 1663 |
|
| 1664 |
#if !defined(CONFIG_USER_ONLY)
|
| 1665 |
|
| 1666 |
static void do_unaligned_access(target_ulong addr, int is_write, int is_user, |
| 1667 |
void *retaddr);
|
| 1668 |
|
| 1669 |
#define MMUSUFFIX _mmu
|
| 1670 |
#define ALIGNED_ONLY
|
| 1671 |
#define GETPC() (__builtin_return_address(0)) |
| 1672 |
|
| 1673 |
#define SHIFT 0 |
| 1674 |
#include "softmmu_template.h" |
| 1675 |
|
| 1676 |
#define SHIFT 1 |
| 1677 |
#include "softmmu_template.h" |
| 1678 |
|
| 1679 |
#define SHIFT 2 |
| 1680 |
#include "softmmu_template.h" |
| 1681 |
|
| 1682 |
#define SHIFT 3 |
| 1683 |
#include "softmmu_template.h" |
| 1684 |
|
| 1685 |
static void do_unaligned_access(target_ulong addr, int is_write, int is_user, |
| 1686 |
void *retaddr)
|
| 1687 |
{
|
| 1688 |
#ifdef DEBUG_UNALIGNED
|
| 1689 |
printf("Unaligned access to 0x%x from 0x%x\n", addr, env->pc);
|
| 1690 |
#endif
|
| 1691 |
raise_exception(TT_UNALIGNED); |
| 1692 |
} |
| 1693 |
|
| 1694 |
/* try to fill the TLB and return an exception if error. If retaddr is
|
| 1695 |
NULL, it means that the function was called in C code (i.e. not
|
| 1696 |
from generated code or from helper.c) */
|
| 1697 |
/* XXX: fix it to restore all registers */
|
| 1698 |
void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr) |
| 1699 |
{
|
| 1700 |
TranslationBlock *tb; |
| 1701 |
int ret;
|
| 1702 |
unsigned long pc; |
| 1703 |
CPUState *saved_env; |
| 1704 |
|
| 1705 |
/* XXX: hack to restore env in all cases, even if not called from
|
| 1706 |
generated code */
|
| 1707 |
saved_env = env; |
| 1708 |
env = cpu_single_env; |
| 1709 |
|
| 1710 |
ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
|
| 1711 |
if (ret) {
|
| 1712 |
if (retaddr) {
|
| 1713 |
/* now we have a real cpu fault */
|
| 1714 |
pc = (unsigned long)retaddr; |
| 1715 |
tb = tb_find_pc(pc); |
| 1716 |
if (tb) {
|
| 1717 |
/* the PC is inside the translated code. It means that we have
|
| 1718 |
a virtual CPU fault */
|
| 1719 |
cpu_restore_state(tb, env, pc, (void *)T2);
|
| 1720 |
} |
| 1721 |
} |
| 1722 |
cpu_loop_exit(); |
| 1723 |
} |
| 1724 |
env = saved_env; |
| 1725 |
} |
| 1726 |
|
| 1727 |
#endif
|
| 1728 |
|
| 1729 |
#ifndef TARGET_SPARC64
|
| 1730 |
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, |
| 1731 |
int is_asi)
|
| 1732 |
{
|
| 1733 |
CPUState *saved_env; |
| 1734 |
|
| 1735 |
/* XXX: hack to restore env in all cases, even if not called from
|
| 1736 |
generated code */
|
| 1737 |
saved_env = env; |
| 1738 |
env = cpu_single_env; |
| 1739 |
if (env->mmuregs[3]) /* Fault status register */ |
| 1740 |
env->mmuregs[3] = 1; /* overflow (not read before another fault) */ |
| 1741 |
if (is_asi)
|
| 1742 |
env->mmuregs[3] |= 1 << 16; |
| 1743 |
if (env->psrs)
|
| 1744 |
env->mmuregs[3] |= 1 << 5; |
| 1745 |
if (is_exec)
|
| 1746 |
env->mmuregs[3] |= 1 << 6; |
| 1747 |
if (is_write)
|
| 1748 |
env->mmuregs[3] |= 1 << 7; |
| 1749 |
env->mmuregs[3] |= (5 << 2) | 2; |
| 1750 |
env->mmuregs[4] = addr; /* Fault address register */ |
| 1751 |
if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) { |
| 1752 |
#ifdef DEBUG_UNASSIGNED
|
| 1753 |
printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx |
| 1754 |
"\n", addr, env->pc);
|
| 1755 |
#endif
|
| 1756 |
if (is_exec)
|
| 1757 |
raise_exception(TT_CODE_ACCESS); |
| 1758 |
else
|
| 1759 |
raise_exception(TT_DATA_ACCESS); |
| 1760 |
} |
| 1761 |
env = saved_env; |
| 1762 |
} |
| 1763 |
#else
|
| 1764 |
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, |
| 1765 |
int is_asi)
|
| 1766 |
{
|
| 1767 |
#ifdef DEBUG_UNASSIGNED
|
| 1768 |
CPUState *saved_env; |
| 1769 |
|
| 1770 |
/* XXX: hack to restore env in all cases, even if not called from
|
| 1771 |
generated code */
|
| 1772 |
saved_env = env; |
| 1773 |
env = cpu_single_env; |
| 1774 |
printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx "\n", |
| 1775 |
addr, env->pc); |
| 1776 |
env = saved_env; |
| 1777 |
#endif
|
| 1778 |
if (is_exec)
|
| 1779 |
raise_exception(TT_CODE_ACCESS); |
| 1780 |
else
|
| 1781 |
raise_exception(TT_DATA_ACCESS); |
| 1782 |
} |
| 1783 |
#endif
|
| 1784 |
|
| 1785 |
#ifdef TARGET_SPARC64
|
| 1786 |
void do_tick_set_count(void *opaque, uint64_t count) |
| 1787 |
{
|
| 1788 |
#if !defined(CONFIG_USER_ONLY)
|
| 1789 |
ptimer_set_count(opaque, -count); |
| 1790 |
#endif
|
| 1791 |
} |
| 1792 |
|
| 1793 |
uint64_t do_tick_get_count(void *opaque)
|
| 1794 |
{
|
| 1795 |
#if !defined(CONFIG_USER_ONLY)
|
| 1796 |
return -ptimer_get_count(opaque);
|
| 1797 |
#else
|
| 1798 |
return 0; |
| 1799 |
#endif
|
| 1800 |
} |
| 1801 |
|
| 1802 |
void do_tick_set_limit(void *opaque, uint64_t limit) |
| 1803 |
{
|
| 1804 |
#if !defined(CONFIG_USER_ONLY)
|
| 1805 |
ptimer_set_limit(opaque, -limit, 0);
|
| 1806 |
#endif
|
| 1807 |
} |
| 1808 |
#endif
|