Revision 6f57bbf4 hw/sparc32_dma.c
| b/hw/sparc32_dma.c | ||
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* |
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* Copyright (c) 2006 Fabrice Bellard |
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* |
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* Modifications: |
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* 2010-Feb-14 Artyom Tarasenko : reworked irq generation |
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* |
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* Permission is hereby granted, free of charge, to any person obtaining a copy |
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* of this software and associated documentation files (the "Software"), to deal |
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* in the Software without restriction, including without limitation the rights |
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{
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DMAState *s = opaque; |
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if (level) {
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DPRINTF("Raise IRQ\n");
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s->dmaregs[0] |= DMA_INTR; |
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qemu_irq_raise(s->irq); |
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if (s->dmaregs[0] & DMA_INTREN) {
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DPRINTF("Raise IRQ\n");
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qemu_irq_raise(s->irq); |
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} |
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} else {
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s->dmaregs[0] &= ~DMA_INTR; |
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DPRINTF("Lower IRQ\n");
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qemu_irq_lower(s->irq); |
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if (s->dmaregs[0] & DMA_INTR) {
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s->dmaregs[0] &= ~DMA_INTR; |
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if (s->dmaregs[0] & DMA_INTREN) {
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DPRINTF("Lower IRQ\n");
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qemu_irq_lower(s->irq); |
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} |
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} |
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} |
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} |
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|
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DPRINTF("DMA read, direction: %c, addr 0x%8.8x\n",
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s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]); |
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sparc_iommu_memory_read(s->iommu, s->dmaregs[1], buf, len); |
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s->dmaregs[0] |= DMA_INTR; |
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s->dmaregs[1] += len; |
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} |
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|
| ... | ... | |
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DPRINTF("DMA write, direction: %c, addr 0x%8.8x\n",
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s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]); |
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sparc_iommu_memory_write(s->iommu, s->dmaregs[1], buf, len); |
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s->dmaregs[0] |= DMA_INTR; |
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s->dmaregs[1] += len; |
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} |
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|
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s->dmaregs[saddr], val); |
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switch (saddr) {
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case 0: |
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if (!(val & DMA_INTREN)) {
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DPRINTF("Lower IRQ\n");
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qemu_irq_lower(s->irq); |
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if (val & DMA_INTREN) {
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if (val & DMA_INTR) {
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DPRINTF("Raise IRQ\n");
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qemu_irq_raise(s->irq); |
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} |
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} else {
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if (s->dmaregs[0] & (DMA_INTR | DMA_INTREN)) {
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DPRINTF("Lower IRQ\n");
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qemu_irq_lower(s->irq); |
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} |
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} |
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if (val & DMA_RESET) {
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qemu_irq_raise(s->dev_reset); |
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