root / target-sparc / helper.c @ 6f7e9aec
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1 | e8af50a3 | bellard | /*
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2 | e8af50a3 | bellard | * sparc helpers
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3 | e8af50a3 | bellard | *
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4 | e8af50a3 | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | e8af50a3 | bellard | *
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6 | e8af50a3 | bellard | * This library is free software; you can redistribute it and/or
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7 | e8af50a3 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | e8af50a3 | bellard | * License as published by the Free Software Foundation; either
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9 | e8af50a3 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | e8af50a3 | bellard | *
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11 | e8af50a3 | bellard | * This library is distributed in the hope that it will be useful,
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12 | e8af50a3 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | e8af50a3 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | e8af50a3 | bellard | * Lesser General Public License for more details.
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15 | e8af50a3 | bellard | *
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16 | e8af50a3 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | e8af50a3 | bellard | * License along with this library; if not, write to the Free Software
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18 | e8af50a3 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | e8af50a3 | bellard | */
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20 | e8af50a3 | bellard | #include "exec.h" |
21 | e8af50a3 | bellard | |
22 | e80cfcfc | bellard | //#define DEBUG_PCALL
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23 | e80cfcfc | bellard | //#define DEBUG_MMU
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24 | e8af50a3 | bellard | |
25 | e8af50a3 | bellard | /* Sparc MMU emulation */
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26 | e8af50a3 | bellard | |
27 | e8af50a3 | bellard | /* thread support */
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28 | e8af50a3 | bellard | |
29 | e8af50a3 | bellard | spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED; |
30 | e8af50a3 | bellard | |
31 | e8af50a3 | bellard | void cpu_lock(void) |
32 | e8af50a3 | bellard | { |
33 | e8af50a3 | bellard | spin_lock(&global_cpu_lock); |
34 | e8af50a3 | bellard | } |
35 | e8af50a3 | bellard | |
36 | e8af50a3 | bellard | void cpu_unlock(void) |
37 | e8af50a3 | bellard | { |
38 | e8af50a3 | bellard | spin_unlock(&global_cpu_lock); |
39 | e8af50a3 | bellard | } |
40 | e8af50a3 | bellard | |
41 | 9d893301 | bellard | #if defined(CONFIG_USER_ONLY)
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42 | 9d893301 | bellard | |
43 | 9d893301 | bellard | int cpu_sparc_handle_mmu_fault(CPUState *env, target_ulong address, int rw, |
44 | 9d893301 | bellard | int is_user, int is_softmmu) |
45 | 9d893301 | bellard | { |
46 | 9d893301 | bellard | env->mmuregs[4] = address;
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47 | 878d3096 | bellard | if (rw & 2) |
48 | 878d3096 | bellard | env->exception_index = TT_TFAULT; |
49 | 878d3096 | bellard | else
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50 | 878d3096 | bellard | env->exception_index = TT_DFAULT; |
51 | 9d893301 | bellard | return 1; |
52 | 9d893301 | bellard | } |
53 | 9d893301 | bellard | |
54 | 9d893301 | bellard | #else
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55 | e8af50a3 | bellard | |
56 | e8af50a3 | bellard | #define MMUSUFFIX _mmu
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57 | e8af50a3 | bellard | #define GETPC() (__builtin_return_address(0)) |
58 | e8af50a3 | bellard | |
59 | e8af50a3 | bellard | #define SHIFT 0 |
60 | e8af50a3 | bellard | #include "softmmu_template.h" |
61 | e8af50a3 | bellard | |
62 | e8af50a3 | bellard | #define SHIFT 1 |
63 | e8af50a3 | bellard | #include "softmmu_template.h" |
64 | e8af50a3 | bellard | |
65 | e8af50a3 | bellard | #define SHIFT 2 |
66 | e8af50a3 | bellard | #include "softmmu_template.h" |
67 | e8af50a3 | bellard | |
68 | e8af50a3 | bellard | #define SHIFT 3 |
69 | e8af50a3 | bellard | #include "softmmu_template.h" |
70 | e8af50a3 | bellard | |
71 | e8af50a3 | bellard | |
72 | e8af50a3 | bellard | /* try to fill the TLB and return an exception if error. If retaddr is
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73 | e8af50a3 | bellard | NULL, it means that the function was called in C code (i.e. not
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74 | e8af50a3 | bellard | from generated code or from helper.c) */
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75 | e8af50a3 | bellard | /* XXX: fix it to restore all registers */
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76 | 0fa85d43 | bellard | void tlb_fill(target_ulong addr, int is_write, int is_user, void *retaddr) |
77 | e8af50a3 | bellard | { |
78 | e8af50a3 | bellard | TranslationBlock *tb; |
79 | e8af50a3 | bellard | int ret;
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80 | e8af50a3 | bellard | unsigned long pc; |
81 | e8af50a3 | bellard | CPUState *saved_env; |
82 | e8af50a3 | bellard | |
83 | e8af50a3 | bellard | /* XXX: hack to restore env in all cases, even if not called from
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84 | e8af50a3 | bellard | generated code */
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85 | e8af50a3 | bellard | saved_env = env; |
86 | e8af50a3 | bellard | env = cpu_single_env; |
87 | e8af50a3 | bellard | |
88 | e8af50a3 | bellard | ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, is_user, 1);
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89 | e8af50a3 | bellard | if (ret) {
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90 | e8af50a3 | bellard | if (retaddr) {
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91 | e8af50a3 | bellard | /* now we have a real cpu fault */
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92 | e8af50a3 | bellard | pc = (unsigned long)retaddr; |
93 | e8af50a3 | bellard | tb = tb_find_pc(pc); |
94 | e8af50a3 | bellard | if (tb) {
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95 | e8af50a3 | bellard | /* the PC is inside the translated code. It means that we have
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96 | e8af50a3 | bellard | a virtual CPU fault */
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97 | e8af50a3 | bellard | cpu_restore_state(tb, env, pc, NULL);
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98 | e8af50a3 | bellard | } |
99 | e8af50a3 | bellard | } |
100 | 878d3096 | bellard | cpu_loop_exit(); |
101 | e8af50a3 | bellard | } |
102 | e8af50a3 | bellard | env = saved_env; |
103 | e8af50a3 | bellard | } |
104 | e8af50a3 | bellard | |
105 | e8af50a3 | bellard | static const int access_table[8][8] = { |
106 | e8af50a3 | bellard | { 0, 0, 0, 0, 2, 0, 3, 3 }, |
107 | e8af50a3 | bellard | { 0, 0, 0, 0, 2, 0, 0, 0 }, |
108 | e8af50a3 | bellard | { 2, 2, 0, 0, 0, 2, 3, 3 }, |
109 | e8af50a3 | bellard | { 2, 2, 0, 0, 0, 2, 0, 0 }, |
110 | e8af50a3 | bellard | { 2, 0, 2, 0, 2, 2, 3, 3 }, |
111 | e8af50a3 | bellard | { 2, 0, 2, 0, 2, 0, 2, 0 }, |
112 | e8af50a3 | bellard | { 2, 2, 2, 0, 2, 2, 3, 3 }, |
113 | e8af50a3 | bellard | { 2, 2, 2, 0, 2, 2, 2, 0 } |
114 | e8af50a3 | bellard | }; |
115 | e8af50a3 | bellard | |
116 | e8af50a3 | bellard | /* 1 = write OK */
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117 | e8af50a3 | bellard | static const int rw_table[2][8] = { |
118 | e8af50a3 | bellard | { 0, 1, 0, 1, 0, 1, 0, 1 }, |
119 | e8af50a3 | bellard | { 0, 1, 0, 1, 0, 0, 0, 0 } |
120 | e8af50a3 | bellard | }; |
121 | e8af50a3 | bellard | |
122 | af7bf89b | bellard | int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot, |
123 | af7bf89b | bellard | int *access_index, target_ulong address, int rw, |
124 | e80cfcfc | bellard | int is_user)
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125 | e8af50a3 | bellard | { |
126 | e80cfcfc | bellard | int access_perms = 0; |
127 | e80cfcfc | bellard | target_phys_addr_t pde_ptr; |
128 | af7bf89b | bellard | uint32_t pde; |
129 | af7bf89b | bellard | target_ulong virt_addr; |
130 | e80cfcfc | bellard | int error_code = 0, is_dirty; |
131 | e80cfcfc | bellard | unsigned long page_offset; |
132 | e8af50a3 | bellard | |
133 | e8af50a3 | bellard | virt_addr = address & TARGET_PAGE_MASK; |
134 | e8af50a3 | bellard | if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */ |
135 | e80cfcfc | bellard | *physical = address; |
136 | e80cfcfc | bellard | *prot = PAGE_READ | PAGE_WRITE; |
137 | e80cfcfc | bellard | return 0; |
138 | e8af50a3 | bellard | } |
139 | e8af50a3 | bellard | |
140 | 7483750d | bellard | *access_index = ((rw & 1) << 2) | (rw & 2) | (is_user? 0 : 1); |
141 | 6f7e9aec | bellard | *physical = 0xfffff000;
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142 | 7483750d | bellard | |
143 | e8af50a3 | bellard | /* SPARC reference MMU table walk: Context table->L1->L2->PTE */
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144 | e8af50a3 | bellard | /* Context base + context number */
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145 | e80cfcfc | bellard | pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 4); |
146 | 49be8030 | bellard | pde = ldl_phys(pde_ptr); |
147 | e8af50a3 | bellard | |
148 | e8af50a3 | bellard | /* Ctx pde */
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149 | e8af50a3 | bellard | switch (pde & PTE_ENTRYTYPE_MASK) {
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150 | e80cfcfc | bellard | default:
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151 | e8af50a3 | bellard | case 0: /* Invalid */ |
152 | 7483750d | bellard | return 1 << 2; |
153 | e80cfcfc | bellard | case 2: /* L0 PTE, maybe should not happen? */ |
154 | e8af50a3 | bellard | case 3: /* Reserved */ |
155 | 7483750d | bellard | return 4 << 2; |
156 | e80cfcfc | bellard | case 1: /* L0 PDE */ |
157 | e80cfcfc | bellard | pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4); |
158 | 49be8030 | bellard | pde = ldl_phys(pde_ptr); |
159 | e8af50a3 | bellard | |
160 | e8af50a3 | bellard | switch (pde & PTE_ENTRYTYPE_MASK) {
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161 | e80cfcfc | bellard | default:
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162 | e8af50a3 | bellard | case 0: /* Invalid */ |
163 | 7483750d | bellard | return (1 << 8) | (1 << 2); |
164 | e8af50a3 | bellard | case 3: /* Reserved */ |
165 | 7483750d | bellard | return (1 << 8) | (4 << 2); |
166 | e80cfcfc | bellard | case 1: /* L1 PDE */ |
167 | e80cfcfc | bellard | pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4); |
168 | 49be8030 | bellard | pde = ldl_phys(pde_ptr); |
169 | e8af50a3 | bellard | |
170 | e8af50a3 | bellard | switch (pde & PTE_ENTRYTYPE_MASK) {
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171 | e80cfcfc | bellard | default:
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172 | e8af50a3 | bellard | case 0: /* Invalid */ |
173 | 7483750d | bellard | return (2 << 8) | (1 << 2); |
174 | e8af50a3 | bellard | case 3: /* Reserved */ |
175 | 7483750d | bellard | return (2 << 8) | (4 << 2); |
176 | e80cfcfc | bellard | case 1: /* L2 PDE */ |
177 | e80cfcfc | bellard | pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4); |
178 | 49be8030 | bellard | pde = ldl_phys(pde_ptr); |
179 | e8af50a3 | bellard | |
180 | e8af50a3 | bellard | switch (pde & PTE_ENTRYTYPE_MASK) {
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181 | e80cfcfc | bellard | default:
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182 | e8af50a3 | bellard | case 0: /* Invalid */ |
183 | 7483750d | bellard | return (3 << 8) | (1 << 2); |
184 | e8af50a3 | bellard | case 1: /* PDE, should not happen */ |
185 | e8af50a3 | bellard | case 3: /* Reserved */ |
186 | 7483750d | bellard | return (3 << 8) | (4 << 2); |
187 | e8af50a3 | bellard | case 2: /* L3 PTE */ |
188 | e8af50a3 | bellard | virt_addr = address & TARGET_PAGE_MASK; |
189 | e8af50a3 | bellard | page_offset = (address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1);
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190 | e8af50a3 | bellard | } |
191 | e8af50a3 | bellard | break;
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192 | e8af50a3 | bellard | case 2: /* L2 PTE */ |
193 | e8af50a3 | bellard | virt_addr = address & ~0x3ffff;
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194 | e8af50a3 | bellard | page_offset = address & 0x3ffff;
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195 | e8af50a3 | bellard | } |
196 | e8af50a3 | bellard | break;
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197 | e8af50a3 | bellard | case 2: /* L1 PTE */ |
198 | e8af50a3 | bellard | virt_addr = address & ~0xffffff;
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199 | e8af50a3 | bellard | page_offset = address & 0xffffff;
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200 | e8af50a3 | bellard | } |
201 | e8af50a3 | bellard | } |
202 | e8af50a3 | bellard | |
203 | e8af50a3 | bellard | /* update page modified and dirty bits */
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204 | b769d8fe | bellard | is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK);
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205 | e8af50a3 | bellard | if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
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206 | e8af50a3 | bellard | pde |= PG_ACCESSED_MASK; |
207 | e8af50a3 | bellard | if (is_dirty)
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208 | e8af50a3 | bellard | pde |= PG_MODIFIED_MASK; |
209 | 49be8030 | bellard | stl_phys_notdirty(pde_ptr, pde); |
210 | e8af50a3 | bellard | } |
211 | e8af50a3 | bellard | /* check access */
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212 | e8af50a3 | bellard | access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT; |
213 | e80cfcfc | bellard | error_code = access_table[*access_index][access_perms]; |
214 | 6f7e9aec | bellard | if (error_code && !(env->mmuregs[0] & MMU_NF)) |
215 | e80cfcfc | bellard | return error_code;
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216 | e8af50a3 | bellard | |
217 | e8af50a3 | bellard | /* the page can be put in the TLB */
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218 | e80cfcfc | bellard | *prot = PAGE_READ; |
219 | e8af50a3 | bellard | if (pde & PG_MODIFIED_MASK) {
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220 | e8af50a3 | bellard | /* only set write access if already dirty... otherwise wait
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221 | e8af50a3 | bellard | for dirty access */
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222 | e8af50a3 | bellard | if (rw_table[is_user][access_perms])
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223 | e80cfcfc | bellard | *prot |= PAGE_WRITE; |
224 | e8af50a3 | bellard | } |
225 | e8af50a3 | bellard | |
226 | e8af50a3 | bellard | /* Even if large ptes, we map only one 4KB page in the cache to
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227 | e8af50a3 | bellard | avoid filling it too fast */
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228 | e80cfcfc | bellard | *physical = ((pde & PTE_ADDR_MASK) << 4) + page_offset;
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229 | 6f7e9aec | bellard | return error_code;
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230 | e80cfcfc | bellard | } |
231 | e80cfcfc | bellard | |
232 | e80cfcfc | bellard | /* Perform address translation */
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233 | af7bf89b | bellard | int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
234 | e80cfcfc | bellard | int is_user, int is_softmmu) |
235 | e80cfcfc | bellard | { |
236 | af7bf89b | bellard | target_ulong virt_addr; |
237 | af7bf89b | bellard | target_phys_addr_t paddr; |
238 | e80cfcfc | bellard | unsigned long vaddr; |
239 | e80cfcfc | bellard | int error_code = 0, prot, ret = 0, access_index; |
240 | e8af50a3 | bellard | |
241 | e80cfcfc | bellard | error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, is_user); |
242 | e80cfcfc | bellard | if (error_code == 0) { |
243 | e80cfcfc | bellard | virt_addr = address & TARGET_PAGE_MASK; |
244 | e80cfcfc | bellard | vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1));
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245 | e80cfcfc | bellard | ret = tlb_set_page(env, vaddr, paddr, prot, is_user, is_softmmu); |
246 | e80cfcfc | bellard | return ret;
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247 | e80cfcfc | bellard | } |
248 | e8af50a3 | bellard | |
249 | e8af50a3 | bellard | if (env->mmuregs[3]) /* Fault status register */ |
250 | e8af50a3 | bellard | env->mmuregs[3] = 1; /* overflow (not read before another fault) */ |
251 | 7483750d | bellard | env->mmuregs[3] |= (access_index << 5) | error_code | 2; |
252 | e8af50a3 | bellard | env->mmuregs[4] = address; /* Fault address register */ |
253 | e8af50a3 | bellard | |
254 | 878d3096 | bellard | if ((env->mmuregs[0] & MMU_NF) || env->psret == 0) { |
255 | 6f7e9aec | bellard | // No fault mode: if a mapping is available, just override
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256 | 6f7e9aec | bellard | // permissions. If no mapping is available, redirect accesses to
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257 | 6f7e9aec | bellard | // neverland. Fake/overridden mappings will be flushed when
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258 | 6f7e9aec | bellard | // switching to normal mode.
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259 | 7483750d | bellard | vaddr = address & TARGET_PAGE_MASK; |
260 | 7483750d | bellard | prot = PAGE_READ | PAGE_WRITE; |
261 | 7483750d | bellard | ret = tlb_set_page(env, vaddr, paddr, prot, is_user, is_softmmu); |
262 | 7483750d | bellard | return ret;
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263 | 7483750d | bellard | } else {
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264 | 7483750d | bellard | if (rw & 2) |
265 | 7483750d | bellard | env->exception_index = TT_TFAULT; |
266 | 7483750d | bellard | else
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267 | 7483750d | bellard | env->exception_index = TT_DFAULT; |
268 | 7483750d | bellard | return 1; |
269 | 878d3096 | bellard | } |
270 | e8af50a3 | bellard | } |
271 | 9d893301 | bellard | #endif
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272 | e8af50a3 | bellard | |
273 | af7bf89b | bellard | void memcpy32(target_ulong *dst, const target_ulong *src) |
274 | e8af50a3 | bellard | { |
275 | e8af50a3 | bellard | dst[0] = src[0]; |
276 | e8af50a3 | bellard | dst[1] = src[1]; |
277 | e8af50a3 | bellard | dst[2] = src[2]; |
278 | e8af50a3 | bellard | dst[3] = src[3]; |
279 | e8af50a3 | bellard | dst[4] = src[4]; |
280 | e8af50a3 | bellard | dst[5] = src[5]; |
281 | e8af50a3 | bellard | dst[6] = src[6]; |
282 | e8af50a3 | bellard | dst[7] = src[7]; |
283 | e8af50a3 | bellard | } |
284 | e8af50a3 | bellard | |
285 | e8af50a3 | bellard | void set_cwp(int new_cwp) |
286 | e8af50a3 | bellard | { |
287 | e8af50a3 | bellard | /* put the modified wrap registers at their proper location */
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288 | e8af50a3 | bellard | if (env->cwp == (NWINDOWS - 1)) |
289 | e8af50a3 | bellard | memcpy32(env->regbase, env->regbase + NWINDOWS * 16);
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290 | e8af50a3 | bellard | env->cwp = new_cwp; |
291 | e8af50a3 | bellard | /* put the wrap registers at their temporary location */
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292 | e8af50a3 | bellard | if (new_cwp == (NWINDOWS - 1)) |
293 | e8af50a3 | bellard | memcpy32(env->regbase + NWINDOWS * 16, env->regbase);
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294 | e8af50a3 | bellard | env->regwptr = env->regbase + (new_cwp * 16);
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295 | e8af50a3 | bellard | } |
296 | e8af50a3 | bellard | |
297 | 0fa85d43 | bellard | void cpu_set_cwp(CPUState *env1, int new_cwp) |
298 | 0fa85d43 | bellard | { |
299 | 0fa85d43 | bellard | CPUState *saved_env; |
300 | 0fa85d43 | bellard | saved_env = env; |
301 | 0fa85d43 | bellard | env = env1; |
302 | 0fa85d43 | bellard | set_cwp(new_cwp); |
303 | 0fa85d43 | bellard | env = saved_env; |
304 | 0fa85d43 | bellard | } |
305 | 0fa85d43 | bellard | |
306 | 878d3096 | bellard | void do_interrupt(int intno) |
307 | e8af50a3 | bellard | { |
308 | e8af50a3 | bellard | int cwp;
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309 | e8af50a3 | bellard | |
310 | e8af50a3 | bellard | #ifdef DEBUG_PCALL
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311 | e8af50a3 | bellard | if (loglevel & CPU_LOG_INT) {
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312 | e8af50a3 | bellard | static int count; |
313 | 878d3096 | bellard | fprintf(logfile, "%6d: v=%02x pc=%08x npc=%08x SP=%08x\n",
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314 | 878d3096 | bellard | count, intno, |
315 | 9d893301 | bellard | env->pc, |
316 | 9d893301 | bellard | env->npc, env->regwptr[6]);
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317 | 7fe48483 | bellard | cpu_dump_state(env, logfile, fprintf, 0);
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318 | 6f7e9aec | bellard | #if 0
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319 | e8af50a3 | bellard | {
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320 | e8af50a3 | bellard | int i;
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321 | e8af50a3 | bellard | uint8_t *ptr;
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322 | e80cfcfc | bellard | |
323 | e8af50a3 | bellard | fprintf(logfile, " code=");
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324 | e80cfcfc | bellard | ptr = (uint8_t *)env->pc;
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325 | e8af50a3 | bellard | for(i = 0; i < 16; i++) {
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326 | e8af50a3 | bellard | fprintf(logfile, " %02x", ldub(ptr + i));
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327 | e8af50a3 | bellard | }
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328 | e8af50a3 | bellard | fprintf(logfile, "\n");
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329 | e8af50a3 | bellard | }
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330 | e8af50a3 | bellard | #endif
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331 | e8af50a3 | bellard | count++; |
332 | e8af50a3 | bellard | } |
333 | e8af50a3 | bellard | #endif
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334 | e80cfcfc | bellard | #if !defined(CONFIG_USER_ONLY)
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335 | e80cfcfc | bellard | if (env->psret == 0) { |
336 | 878d3096 | bellard | cpu_abort(cpu_single_env, "Trap 0x%02x while interrupts disabled, Error state", env->exception_index);
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337 | e80cfcfc | bellard | return;
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338 | e80cfcfc | bellard | } |
339 | e80cfcfc | bellard | #endif
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340 | e8af50a3 | bellard | env->psret = 0;
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341 | e8af50a3 | bellard | cwp = (env->cwp - 1) & (NWINDOWS - 1); |
342 | e8af50a3 | bellard | set_cwp(cwp); |
343 | 878d3096 | bellard | env->regwptr[9] = env->pc;
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344 | 878d3096 | bellard | env->regwptr[10] = env->npc;
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345 | e8af50a3 | bellard | env->psrps = env->psrs; |
346 | e8af50a3 | bellard | env->psrs = 1;
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347 | e8af50a3 | bellard | env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
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348 | e8af50a3 | bellard | env->pc = env->tbr; |
349 | e8af50a3 | bellard | env->npc = env->pc + 4;
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350 | e8af50a3 | bellard | env->exception_index = 0;
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351 | e8af50a3 | bellard | } |
352 | e8af50a3 | bellard | |
353 | af7bf89b | bellard | target_ulong mmu_probe(target_ulong address, int mmulev)
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354 | e80cfcfc | bellard | { |
355 | e80cfcfc | bellard | target_phys_addr_t pde_ptr; |
356 | e80cfcfc | bellard | uint32_t pde; |
357 | e80cfcfc | bellard | |
358 | e80cfcfc | bellard | /* Context base + context number */
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359 | e80cfcfc | bellard | pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 4); |
360 | 49be8030 | bellard | pde = ldl_phys(pde_ptr); |
361 | 49be8030 | bellard | |
362 | e80cfcfc | bellard | switch (pde & PTE_ENTRYTYPE_MASK) {
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363 | e80cfcfc | bellard | default:
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364 | e80cfcfc | bellard | case 0: /* Invalid */ |
365 | e80cfcfc | bellard | case 2: /* PTE, maybe should not happen? */ |
366 | e80cfcfc | bellard | case 3: /* Reserved */ |
367 | e80cfcfc | bellard | return 0; |
368 | e80cfcfc | bellard | case 1: /* L1 PDE */ |
369 | e80cfcfc | bellard | if (mmulev == 3) |
370 | e80cfcfc | bellard | return pde;
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371 | e80cfcfc | bellard | pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4); |
372 | 49be8030 | bellard | pde = ldl_phys(pde_ptr); |
373 | e80cfcfc | bellard | |
374 | e80cfcfc | bellard | switch (pde & PTE_ENTRYTYPE_MASK) {
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375 | e80cfcfc | bellard | default:
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376 | e80cfcfc | bellard | case 0: /* Invalid */ |
377 | e80cfcfc | bellard | case 3: /* Reserved */ |
378 | e80cfcfc | bellard | return 0; |
379 | e80cfcfc | bellard | case 2: /* L1 PTE */ |
380 | e80cfcfc | bellard | return pde;
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381 | e80cfcfc | bellard | case 1: /* L2 PDE */ |
382 | e80cfcfc | bellard | if (mmulev == 2) |
383 | e80cfcfc | bellard | return pde;
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384 | e80cfcfc | bellard | pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4); |
385 | 49be8030 | bellard | pde = ldl_phys(pde_ptr); |
386 | e80cfcfc | bellard | |
387 | e80cfcfc | bellard | switch (pde & PTE_ENTRYTYPE_MASK) {
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388 | e80cfcfc | bellard | default:
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389 | e80cfcfc | bellard | case 0: /* Invalid */ |
390 | e80cfcfc | bellard | case 3: /* Reserved */ |
391 | e80cfcfc | bellard | return 0; |
392 | e80cfcfc | bellard | case 2: /* L2 PTE */ |
393 | e80cfcfc | bellard | return pde;
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394 | e80cfcfc | bellard | case 1: /* L3 PDE */ |
395 | e80cfcfc | bellard | if (mmulev == 1) |
396 | e80cfcfc | bellard | return pde;
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397 | e80cfcfc | bellard | pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4); |
398 | 49be8030 | bellard | pde = ldl_phys(pde_ptr); |
399 | e80cfcfc | bellard | |
400 | e80cfcfc | bellard | switch (pde & PTE_ENTRYTYPE_MASK) {
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401 | e80cfcfc | bellard | default:
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402 | e80cfcfc | bellard | case 0: /* Invalid */ |
403 | e80cfcfc | bellard | case 1: /* PDE, should not happen */ |
404 | e80cfcfc | bellard | case 3: /* Reserved */ |
405 | e80cfcfc | bellard | return 0; |
406 | e80cfcfc | bellard | case 2: /* L3 PTE */ |
407 | e80cfcfc | bellard | return pde;
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408 | e80cfcfc | bellard | } |
409 | e80cfcfc | bellard | } |
410 | e80cfcfc | bellard | } |
411 | e80cfcfc | bellard | } |
412 | e80cfcfc | bellard | return 0; |
413 | e80cfcfc | bellard | } |
414 | e80cfcfc | bellard | |
415 | 55754d9e | bellard | #ifdef DEBUG_MMU
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416 | e80cfcfc | bellard | void dump_mmu(void) |
417 | e80cfcfc | bellard | { |
418 | af7bf89b | bellard | target_ulong va, va1, va2; |
419 | af7bf89b | bellard | unsigned int n, m, o; |
420 | af7bf89b | bellard | target_phys_addr_t pde_ptr, pa; |
421 | e80cfcfc | bellard | uint32_t pde; |
422 | e80cfcfc | bellard | |
423 | e80cfcfc | bellard | printf("MMU dump:\n");
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424 | e80cfcfc | bellard | pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 4); |
425 | 49be8030 | bellard | pde = ldl_phys(pde_ptr); |
426 | af7bf89b | bellard | printf("Root ptr: " TARGET_FMT_lx ", ctx: %d\n", env->mmuregs[1] << 4, env->mmuregs[2]); |
427 | e80cfcfc | bellard | for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) { |
428 | e80cfcfc | bellard | pde_ptr = mmu_probe(va, 2);
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429 | e80cfcfc | bellard | if (pde_ptr) {
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430 | e80cfcfc | bellard | pa = cpu_get_phys_page_debug(env, va); |
431 | af7bf89b | bellard | printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PDE: " TARGET_FMT_lx "\n", va, pa, pde_ptr); |
432 | e80cfcfc | bellard | for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) { |
433 | e80cfcfc | bellard | pde_ptr = mmu_probe(va1, 1);
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434 | e80cfcfc | bellard | if (pde_ptr) {
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435 | e80cfcfc | bellard | pa = cpu_get_phys_page_debug(env, va1); |
436 | af7bf89b | bellard | printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PDE: " TARGET_FMT_lx "\n", va1, pa, pde_ptr); |
437 | e80cfcfc | bellard | for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) { |
438 | e80cfcfc | bellard | pde_ptr = mmu_probe(va2, 0);
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439 | e80cfcfc | bellard | if (pde_ptr) {
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440 | e80cfcfc | bellard | pa = cpu_get_phys_page_debug(env, va2); |
441 | af7bf89b | bellard | printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PTE: " TARGET_FMT_lx "\n", va2, pa, pde_ptr); |
442 | e80cfcfc | bellard | } |
443 | e80cfcfc | bellard | } |
444 | e80cfcfc | bellard | } |
445 | e80cfcfc | bellard | } |
446 | e80cfcfc | bellard | } |
447 | e80cfcfc | bellard | } |
448 | e80cfcfc | bellard | printf("MMU dump ends\n");
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449 | e80cfcfc | bellard | } |
450 | 55754d9e | bellard | #endif |