Revision 6f7e9aec hw/sun4m.c
| b/hw/sun4m.c | ||
|---|---|---|
| 36 | 36 |
// IRQs are not PIL ones, but master interrupt controller register |
| 37 | 37 |
// bits |
| 38 | 38 |
#define PHYS_JJ_IOMMU 0x10000000 /* I/O MMU */ |
| 39 |
#define PHYS_JJ_TCX_FB 0x50800000 /* Start address, frame buffer body */ |
|
| 39 |
#define PHYS_JJ_TCX_FB 0x50000000 /* TCX frame buffer */ |
|
| 40 |
#define PHYS_JJ_ESPDMA 0x78400000 /* ESP DMA controller */ |
|
| 41 |
#define PHYS_JJ_ESP 0x78800000 /* ESP SCSI */ |
|
| 42 |
#define PHYS_JJ_ESP_IRQ 18 |
|
| 40 | 43 |
#define PHYS_JJ_LEDMA 0x78400010 /* Lance DMA controller */ |
| 41 | 44 |
#define PHYS_JJ_LE 0x78C00000 /* Lance ethernet */ |
| 42 | 45 |
#define PHYS_JJ_LE_IRQ 16 |
| ... | ... | |
| 50 | 53 |
#define PHYS_JJ_MS_KBD_IRQ 14 |
| 51 | 54 |
#define PHYS_JJ_SER 0x71100000 /* Serial */ |
| 52 | 55 |
#define PHYS_JJ_SER_IRQ 15 |
| 53 |
#define PHYS_JJ_SCSI_IRQ 18 |
|
| 54 | 56 |
#define PHYS_JJ_FDC 0x71400000 /* Floppy */ |
| 55 | 57 |
#define PHYS_JJ_FLOPPY_IRQ 22 |
| 56 | 58 |
|
| ... | ... | |
| 61 | 63 |
return qemu_get_clock(vm_clock); |
| 62 | 64 |
} |
| 63 | 65 |
|
| 64 |
void DMA_run() {}
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int DMA_get_channel_mode (int nchan) |
|
| 67 |
{
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return 0; |
|
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} |
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int DMA_read_memory (int nchan, void *buf, int pos, int size) |
|
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{
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return 0; |
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} |
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int DMA_write_memory (int nchan, void *buf, int pos, int size) |
|
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{
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return 0; |
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} |
|
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void DMA_hold_DREQ (int nchan) {}
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void DMA_release_DREQ (int nchan) {}
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void DMA_schedule(int nchan) {}
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void DMA_run (void) {}
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void DMA_init (int high_page_enable) {}
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void DMA_register_channel (int nchan, |
|
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DMA_transfer_handler transfer_handler, |
|
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void *opaque) |
|
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{
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} |
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static void nvram_set_word (m48t08_t *nvram, uint32_t addr, uint16_t value) |
|
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{
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m48t08_write(nvram, addr++, (value >> 8) & 0xff); |
|
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m48t08_write(nvram, addr++, value & 0xff); |
|
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} |
|
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|
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static void nvram_set_lword (m48t08_t *nvram, uint32_t addr, uint32_t value) |
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{
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m48t08_write(nvram, addr++, value >> 24); |
|
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m48t08_write(nvram, addr++, (value >> 16) & 0xff); |
|
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m48t08_write(nvram, addr++, (value >> 8) & 0xff); |
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m48t08_write(nvram, addr++, value & 0xff); |
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} |
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static void nvram_set_string (m48t08_t *nvram, uint32_t addr, |
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const unsigned char *str, uint32_t max) |
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{
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unsigned int i; |
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for (i = 0; i < max && str[i] != '\0'; i++) {
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m48t08_write(nvram, addr + i, str[i]); |
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} |
|
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m48t08_write(nvram, addr + max - 1, '\0'); |
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} |
|
| 65 | 113 |
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| 66 | 114 |
static m48t08_t *nvram; |
| 67 | 115 |
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static void nvram_init(m48t08_t *nvram, uint8_t *macaddr, const char *cmdline) |
|
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extern int nographic; |
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static void nvram_init(m48t08_t *nvram, uint8_t *macaddr, const char *cmdline, |
|
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int boot_device, uint32_t RAM_size, |
|
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uint32_t kernel_size, |
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int width, int height, int depth) |
|
| 69 | 122 |
{
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| 70 | 123 |
unsigned char tmp = 0; |
| 71 | 124 |
int i, j; |
| 72 | 125 |
|
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i = 0x40; |
|
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// Try to match PPC NVRAM |
|
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nvram_set_string(nvram, 0x00, "QEMU_BIOS", 16); |
|
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nvram_set_lword(nvram, 0x10, 0x00000001); /* structure v1 */ |
|
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// NVRAM_size, arch not applicable |
|
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m48t08_write(nvram, 0x2F, nographic & 0xff); |
|
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nvram_set_lword(nvram, 0x30, RAM_size); |
|
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m48t08_write(nvram, 0x34, boot_device & 0xff); |
|
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nvram_set_lword(nvram, 0x38, KERNEL_LOAD_ADDR); |
|
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nvram_set_lword(nvram, 0x3C, kernel_size); |
|
| 74 | 135 |
if (cmdline) {
|
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uint32_t cmdline_len; |
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|
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| 77 | 136 |
strcpy(phys_ram_base + CMDLINE_ADDR, cmdline); |
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m48t08_write(nvram, i++, CMDLINE_ADDR >> 24); |
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m48t08_write(nvram, i++, (CMDLINE_ADDR >> 16) & 0xff); |
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m48t08_write(nvram, i++, (CMDLINE_ADDR >> 8) & 0xff); |
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m48t08_write(nvram, i++, CMDLINE_ADDR & 0xff); |
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cmdline_len = strlen(cmdline); |
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m48t08_write(nvram, i++, cmdline_len >> 24); |
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m48t08_write(nvram, i++, (cmdline_len >> 16) & 0xff); |
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m48t08_write(nvram, i++, (cmdline_len >> 8) & 0xff); |
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m48t08_write(nvram, i++, cmdline_len & 0xff); |
|
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nvram_set_lword(nvram, 0x40, CMDLINE_ADDR); |
|
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nvram_set_lword(nvram, 0x44, strlen(cmdline)); |
|
| 88 | 139 |
} |
| 140 |
// initrd_image, initrd_size passed differently |
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nvram_set_word(nvram, 0x54, width); |
|
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nvram_set_word(nvram, 0x56, height); |
|
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nvram_set_word(nvram, 0x58, depth); |
|
| 89 | 144 |
|
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// Sun4m specific use |
|
| 90 | 146 |
i = 0x1fd8; |
| 91 | 147 |
m48t08_write(nvram, i++, 0x01); |
| 92 | 148 |
m48t08_write(nvram, i++, 0x80); /* Sun4m OBP */ |
| ... | ... | |
| 155 | 211 |
char buf[1024]; |
| 156 | 212 |
int ret, linux_boot; |
| 157 | 213 |
unsigned int i; |
| 158 |
unsigned long vram_size = 0x100000, prom_offset, initrd_size;
|
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long vram_size = 0x100000, prom_offset, initrd_size, kernel_size;
|
|
| 159 | 215 |
|
| 160 | 216 |
linux_boot = (kernel_filename != NULL); |
| 161 | 217 |
|
| ... | ... | |
| 164 | 220 |
|
| 165 | 221 |
iommu = iommu_init(PHYS_JJ_IOMMU); |
| 166 | 222 |
slavio_intctl = slavio_intctl_init(PHYS_JJ_INTR0, PHYS_JJ_INTR_G); |
| 167 |
tcx = tcx_init(ds, PHYS_JJ_TCX_FB, phys_ram_base + ram_size, ram_size, vram_size); |
|
| 223 |
tcx = tcx_init(ds, PHYS_JJ_TCX_FB, phys_ram_base + ram_size, ram_size, vram_size, graphic_width, graphic_height);
|
|
| 168 | 224 |
lance_init(&nd_table[0], PHYS_JJ_LE_IRQ, PHYS_JJ_LE, PHYS_JJ_LEDMA); |
| 169 | 225 |
nvram = m48t08_init(PHYS_JJ_EEPROM, PHYS_JJ_EEPROM_SIZE); |
| 170 |
nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline); |
|
| 171 | 226 |
slavio_timer_init(PHYS_JJ_CLOCK, PHYS_JJ_CLOCK_IRQ, PHYS_JJ_CLOCK1, PHYS_JJ_CLOCK1_IRQ); |
| 172 | 227 |
slavio_serial_ms_kbd_init(PHYS_JJ_MS_KBD, PHYS_JJ_MS_KBD_IRQ); |
| 173 | 228 |
slavio_serial_init(PHYS_JJ_SER, PHYS_JJ_SER_IRQ, serial_hds[0], serial_hds[1]); |
| 174 | 229 |
fdctrl_init(PHYS_JJ_FLOPPY_IRQ, 0, 1, PHYS_JJ_FDC, fd_table); |
| 230 |
esp_init(bs_table, PHYS_JJ_ESP_IRQ, PHYS_JJ_ESP, PHYS_JJ_ESPDMA); |
|
| 175 | 231 |
|
| 176 | 232 |
prom_offset = ram_size + vram_size; |
| 177 | 233 |
|
| ... | ... | |
| 189 | 245 |
cpu_register_physical_memory(PROM_ADDR, (ret + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK, |
| 190 | 246 |
prom_offset | IO_MEM_ROM); |
| 191 | 247 |
|
| 248 |
kernel_size = 0; |
|
| 192 | 249 |
if (linux_boot) {
|
| 193 |
ret = load_elf(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
|
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| 194 |
if (ret < 0)
|
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| 195 |
ret = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
|
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| 196 |
if (ret < 0)
|
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| 197 |
ret = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
|
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| 198 |
if (ret < 0) {
|
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| 250 |
kernel_size = load_elf(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
|
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| 251 |
if (kernel_size < 0)
|
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| 252 |
kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
|
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| 253 |
if (kernel_size < 0)
|
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| 254 |
kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
|
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| 255 |
if (kernel_size < 0) {
|
|
| 199 | 256 |
fprintf(stderr, "qemu: could not load kernel '%s'\n", |
| 200 | 257 |
kernel_filename); |
| 201 | 258 |
exit(1); |
| ... | ... | |
| 222 | 279 |
} |
| 223 | 280 |
} |
| 224 | 281 |
} |
| 282 |
nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline, boot_device, ram_size, kernel_size, graphic_width, graphic_height, graphic_depth); |
|
| 225 | 283 |
} |
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