Revision 6f7e9aec target-sparc/helper.c

b/target-sparc/helper.c
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    }
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    *access_index = ((rw & 1) << 2) | (rw & 2) | (is_user? 0 : 1);
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    *physical = 0xfffff000;
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    /* SPARC reference MMU table walk: Context table->L1->L2->PTE */
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    /* Context base + context number */
......
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    /* check access */
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    access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT;
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    error_code = access_table[*access_index][access_perms];
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    if (error_code)
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    if (error_code && !(env->mmuregs[0] & MMU_NF))
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	return error_code;
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    /* the page can be put in the TLB */
......
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    /* Even if large ptes, we map only one 4KB page in the cache to
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       avoid filling it too fast */
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    *physical = ((pde & PTE_ADDR_MASK) << 4) + page_offset;
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    return 0;
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    return error_code;
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}
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/* Perform address translation */
......
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    env->mmuregs[4] = address; /* Fault address register */
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    if ((env->mmuregs[0] & MMU_NF) || env->psret == 0)  {
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#if 0
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        // No fault
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        // No fault mode: if a mapping is available, just override
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        // permissions. If no mapping is available, redirect accesses to
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        // neverland. Fake/overridden mappings will be flushed when
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        // switching to normal mode.
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	vaddr = address & TARGET_PAGE_MASK;
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        paddr = 0xfffff000;
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        prot = PAGE_READ | PAGE_WRITE;
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        ret = tlb_set_page(env, vaddr, paddr, prot, is_user, is_softmmu);
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	return ret;
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#else
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        cpu_abort(env, "MMU no fault case no handled");
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        return 0;
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#endif
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    } else {
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        if (rw & 2)
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            env->exception_index = TT_TFAULT;
......
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                count, intno,
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                env->pc,
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                env->npc, env->regwptr[6]);
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#if 1
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	cpu_dump_state(env, logfile, fprintf, 0);
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#if 0
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	{
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	    int i;
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	    uint8_t *ptr;

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