Revision 6fa724a3
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/*****************************************************************************/ |
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/* Vector status and control register */ |
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#define VSCR_NJ 16 /* Vector non-java */ |
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#define VSCR_SAT 0 /* Vector saturation */ |
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#define vscr_nj (((env->vscr) >> VSCR_NJ) & 0x1) |
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#define vscr_sat (((env->vscr) >> VSCR_SAT) & 0x1) |
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/*****************************************************************************/ |
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/* The whole PowerPC CPU context */ |
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#define NB_MMU_MODES 3 |
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