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1 | 2c0262af | bellard | /*
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2 | 5fafdf24 | ths | * i386 execution defines
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3 | 2c0262af | bellard | *
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4 | 2c0262af | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | 2c0262af | bellard | *
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6 | 2c0262af | bellard | * This library is free software; you can redistribute it and/or
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7 | 2c0262af | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 2c0262af | bellard | * License as published by the Free Software Foundation; either
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9 | 2c0262af | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 2c0262af | bellard | *
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11 | 2c0262af | bellard | * This library is distributed in the hope that it will be useful,
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12 | 2c0262af | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 2c0262af | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 2c0262af | bellard | * Lesser General Public License for more details.
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15 | 2c0262af | bellard | *
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16 | 2c0262af | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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18 | 2c0262af | bellard | */
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19 | 7d3505c5 | bellard | #include "config.h" |
20 | 2c0262af | bellard | #include "dyngen-exec.h" |
21 | 2c0262af | bellard | |
22 | 14ce26e7 | bellard | /* XXX: factorize this mess */
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23 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
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24 | 14ce26e7 | bellard | #define TARGET_LONG_BITS 64 |
25 | 14ce26e7 | bellard | #else
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26 | 14ce26e7 | bellard | #define TARGET_LONG_BITS 32 |
27 | 14ce26e7 | bellard | #endif
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28 | 14ce26e7 | bellard | |
29 | d785e6be | bellard | #include "cpu-defs.h" |
30 | d785e6be | bellard | |
31 | 2c0262af | bellard | register struct CPUX86State *env asm(AREG0); |
32 | 14ce26e7 | bellard | |
33 | 7d99a001 | blueswir1 | #include "qemu-common.h" |
34 | 79383c9c | blueswir1 | #include "qemu-log.h" |
35 | 2c0262af | bellard | |
36 | aba1d00a | Blue Swirl | #undef EAX
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37 | 2c0262af | bellard | #define EAX (env->regs[R_EAX])
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38 | aba1d00a | Blue Swirl | #undef ECX
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39 | 2c0262af | bellard | #define ECX (env->regs[R_ECX])
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40 | aba1d00a | Blue Swirl | #undef EDX
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41 | 2c0262af | bellard | #define EDX (env->regs[R_EDX])
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42 | aba1d00a | Blue Swirl | #undef EBX
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43 | 2c0262af | bellard | #define EBX (env->regs[R_EBX])
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44 | aba1d00a | Blue Swirl | #undef ESP
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45 | 2c0262af | bellard | #define ESP (env->regs[R_ESP])
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46 | aba1d00a | Blue Swirl | #undef EBP
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47 | 2c0262af | bellard | #define EBP (env->regs[R_EBP])
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48 | aba1d00a | Blue Swirl | #undef ESI
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49 | 2c0262af | bellard | #define ESI (env->regs[R_ESI])
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50 | aba1d00a | Blue Swirl | #undef EDI
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51 | 2c0262af | bellard | #define EDI (env->regs[R_EDI])
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52 | aba1d00a | Blue Swirl | #undef EIP
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53 | 1e4840bf | bellard | #define EIP (env->eip)
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54 | 2c0262af | bellard | #define DF (env->df)
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55 | 2c0262af | bellard | |
56 | 2c0262af | bellard | #define CC_SRC (env->cc_src)
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57 | 2c0262af | bellard | #define CC_DST (env->cc_dst)
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58 | 2c0262af | bellard | #define CC_OP (env->cc_op)
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59 | 2c0262af | bellard | |
60 | 2c0262af | bellard | /* float macros */
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61 | 2c0262af | bellard | #define FT0 (env->ft0)
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62 | 664e0f19 | bellard | #define ST0 (env->fpregs[env->fpstt].d)
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63 | 664e0f19 | bellard | #define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d) |
64 | 2c0262af | bellard | #define ST1 ST(1) |
65 | 2c0262af | bellard | |
66 | 2c0262af | bellard | #include "cpu.h" |
67 | 2c0262af | bellard | #include "exec-all.h" |
68 | 2c0262af | bellard | |
69 | d9957a8b | blueswir1 | /* op_helper.c */
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70 | 5fafdf24 | ths | void do_interrupt(int intno, int is_int, int error_code, |
71 | 14ce26e7 | bellard | target_ulong next_eip, int is_hw);
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72 | 5fafdf24 | ths | void do_interrupt_user(int intno, int is_int, int error_code, |
73 | 14ce26e7 | bellard | target_ulong next_eip); |
74 | a5e50b26 | malc | void QEMU_NORETURN raise_exception_err(int exception_index, int error_code); |
75 | a5e50b26 | malc | void QEMU_NORETURN raise_exception(int exception_index); |
76 | 3b21e03e | bellard | void do_smm_enter(void); |
77 | 2c0262af | bellard | |
78 | b6abf97d | bellard | /* n must be a constant to be efficient */
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79 | b6abf97d | bellard | static inline target_long lshift(target_long x, int n) |
80 | b6abf97d | bellard | { |
81 | b6abf97d | bellard | if (n >= 0) |
82 | b6abf97d | bellard | return x << n;
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83 | b6abf97d | bellard | else
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84 | b6abf97d | bellard | return x >> (-n);
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85 | b6abf97d | bellard | } |
86 | b6abf97d | bellard | |
87 | 57fec1fe | bellard | #include "helper.h" |
88 | 57fec1fe | bellard | |
89 | b8b6a50b | bellard | static inline void svm_check_intercept(uint32_t type) |
90 | b8b6a50b | bellard | { |
91 | b8b6a50b | bellard | helper_svm_check_intercept_param(type, 0);
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92 | b8b6a50b | bellard | } |
93 | 3e25f951 | bellard | |
94 | 9951bf39 | bellard | #if !defined(CONFIG_USER_ONLY)
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95 | 9951bf39 | bellard | |
96 | a9049a07 | bellard | #include "softmmu_exec.h" |
97 | 9951bf39 | bellard | |
98 | 9951bf39 | bellard | #endif /* !defined(CONFIG_USER_ONLY) */ |
99 | 9951bf39 | bellard | |
100 | 2c0262af | bellard | #ifdef USE_X86LDOUBLE
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101 | 2c0262af | bellard | /* use long double functions */
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102 | 7a0e1f41 | bellard | #define floatx_to_int32 floatx80_to_int32
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103 | 7a0e1f41 | bellard | #define floatx_to_int64 floatx80_to_int64
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104 | 465e9838 | bellard | #define floatx_to_int32_round_to_zero floatx80_to_int32_round_to_zero
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105 | 465e9838 | bellard | #define floatx_to_int64_round_to_zero floatx80_to_int64_round_to_zero
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106 | 19e6c4b8 | bellard | #define int32_to_floatx int32_to_floatx80
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107 | 19e6c4b8 | bellard | #define int64_to_floatx int64_to_floatx80
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108 | 19e6c4b8 | bellard | #define float32_to_floatx float32_to_floatx80
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109 | 19e6c4b8 | bellard | #define float64_to_floatx float64_to_floatx80
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110 | 19e6c4b8 | bellard | #define floatx_to_float32 floatx80_to_float32
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111 | 19e6c4b8 | bellard | #define floatx_to_float64 floatx80_to_float64
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112 | 7a0e1f41 | bellard | #define floatx_abs floatx80_abs
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113 | 7a0e1f41 | bellard | #define floatx_chs floatx80_chs
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114 | 7a0e1f41 | bellard | #define floatx_round_to_int floatx80_round_to_int
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115 | 8422b113 | bellard | #define floatx_compare floatx80_compare
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116 | 8422b113 | bellard | #define floatx_compare_quiet floatx80_compare_quiet
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117 | 7d3505c5 | bellard | #else
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118 | 7a0e1f41 | bellard | #define floatx_to_int32 float64_to_int32
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119 | 7a0e1f41 | bellard | #define floatx_to_int64 float64_to_int64
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120 | 465e9838 | bellard | #define floatx_to_int32_round_to_zero float64_to_int32_round_to_zero
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121 | 465e9838 | bellard | #define floatx_to_int64_round_to_zero float64_to_int64_round_to_zero
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122 | 19e6c4b8 | bellard | #define int32_to_floatx int32_to_float64
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123 | 19e6c4b8 | bellard | #define int64_to_floatx int64_to_float64
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124 | 19e6c4b8 | bellard | #define float32_to_floatx float32_to_float64
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125 | 19e6c4b8 | bellard | #define float64_to_floatx(x, e) (x)
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126 | 19e6c4b8 | bellard | #define floatx_to_float32 float64_to_float32
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127 | 19e6c4b8 | bellard | #define floatx_to_float64(x, e) (x)
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128 | 7a0e1f41 | bellard | #define floatx_abs float64_abs
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129 | 7a0e1f41 | bellard | #define floatx_chs float64_chs
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130 | 7a0e1f41 | bellard | #define floatx_round_to_int float64_round_to_int
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131 | 8422b113 | bellard | #define floatx_compare float64_compare
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132 | 8422b113 | bellard | #define floatx_compare_quiet float64_compare_quiet
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133 | 7d3505c5 | bellard | #endif
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134 | 7a0e1f41 | bellard | |
135 | 2c0262af | bellard | #define RC_MASK 0xc00 |
136 | 2c0262af | bellard | #define RC_NEAR 0x000 |
137 | 2c0262af | bellard | #define RC_DOWN 0x400 |
138 | 2c0262af | bellard | #define RC_UP 0x800 |
139 | 2c0262af | bellard | #define RC_CHOP 0xc00 |
140 | 2c0262af | bellard | |
141 | 2c0262af | bellard | #define MAXTAN 9223372036854775808.0 |
142 | 2c0262af | bellard | |
143 | 2c0262af | bellard | #ifdef USE_X86LDOUBLE
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144 | 2c0262af | bellard | |
145 | 2c0262af | bellard | /* only for x86 */
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146 | 2c0262af | bellard | typedef union { |
147 | 2c0262af | bellard | long double d; |
148 | 2c0262af | bellard | struct {
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149 | 2c0262af | bellard | unsigned long long lower; |
150 | 2c0262af | bellard | unsigned short upper; |
151 | 2c0262af | bellard | } l; |
152 | 2c0262af | bellard | } CPU86_LDoubleU; |
153 | 2c0262af | bellard | |
154 | 2c0262af | bellard | /* the following deal with x86 long double-precision numbers */
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155 | 2c0262af | bellard | #define MAXEXPD 0x7fff |
156 | 2c0262af | bellard | #define EXPBIAS 16383 |
157 | 2c0262af | bellard | #define EXPD(fp) (fp.l.upper & 0x7fff) |
158 | 2c0262af | bellard | #define SIGND(fp) ((fp.l.upper) & 0x8000) |
159 | 2c0262af | bellard | #define MANTD(fp) (fp.l.lower)
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160 | 2c0262af | bellard | #define BIASEXPONENT(fp) fp.l.upper = (fp.l.upper & ~(0x7fff)) | EXPBIAS |
161 | 2c0262af | bellard | |
162 | 2c0262af | bellard | #else
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163 | 2c0262af | bellard | |
164 | 2c0262af | bellard | /* NOTE: arm is horrible as double 32 bit words are stored in big endian ! */
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165 | 2c0262af | bellard | typedef union { |
166 | 2c0262af | bellard | double d;
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167 | e2542fe2 | Juan Quintela | #if !defined(HOST_WORDS_BIGENDIAN) && !defined(__arm__)
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168 | 2c0262af | bellard | struct {
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169 | 2c0262af | bellard | uint32_t lower; |
170 | 2c0262af | bellard | int32_t upper; |
171 | 2c0262af | bellard | } l; |
172 | 2c0262af | bellard | #else
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173 | 2c0262af | bellard | struct {
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174 | 2c0262af | bellard | int32_t upper; |
175 | 2c0262af | bellard | uint32_t lower; |
176 | 2c0262af | bellard | } l; |
177 | 2c0262af | bellard | #endif
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178 | 2c0262af | bellard | #ifndef __arm__
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179 | 2c0262af | bellard | int64_t ll; |
180 | 2c0262af | bellard | #endif
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181 | 2c0262af | bellard | } CPU86_LDoubleU; |
182 | 2c0262af | bellard | |
183 | 2c0262af | bellard | /* the following deal with IEEE double-precision numbers */
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184 | 2c0262af | bellard | #define MAXEXPD 0x7ff |
185 | 2c0262af | bellard | #define EXPBIAS 1023 |
186 | 2c0262af | bellard | #define EXPD(fp) (((fp.l.upper) >> 20) & 0x7FF) |
187 | 2c0262af | bellard | #define SIGND(fp) ((fp.l.upper) & 0x80000000) |
188 | 2c0262af | bellard | #ifdef __arm__
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189 | 2c0262af | bellard | #define MANTD(fp) (fp.l.lower | ((uint64_t)(fp.l.upper & ((1 << 20) - 1)) << 32)) |
190 | 2c0262af | bellard | #else
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191 | 2c0262af | bellard | #define MANTD(fp) (fp.ll & ((1LL << 52) - 1)) |
192 | 2c0262af | bellard | #endif
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193 | 2c0262af | bellard | #define BIASEXPONENT(fp) fp.l.upper = (fp.l.upper & ~(0x7ff << 20)) | (EXPBIAS << 20) |
194 | 2c0262af | bellard | #endif
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195 | 2c0262af | bellard | |
196 | 2c0262af | bellard | static inline void fpush(void) |
197 | 2c0262af | bellard | { |
198 | 2c0262af | bellard | env->fpstt = (env->fpstt - 1) & 7; |
199 | 2c0262af | bellard | env->fptags[env->fpstt] = 0; /* validate stack entry */ |
200 | 2c0262af | bellard | } |
201 | 2c0262af | bellard | |
202 | 2c0262af | bellard | static inline void fpop(void) |
203 | 2c0262af | bellard | { |
204 | 2c0262af | bellard | env->fptags[env->fpstt] = 1; /* invvalidate stack entry */ |
205 | 2c0262af | bellard | env->fpstt = (env->fpstt + 1) & 7; |
206 | 2c0262af | bellard | } |
207 | 2c0262af | bellard | |
208 | 2c0262af | bellard | #ifndef USE_X86LDOUBLE
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209 | 14ce26e7 | bellard | static inline CPU86_LDouble helper_fldt(target_ulong ptr) |
210 | 2c0262af | bellard | { |
211 | 2c0262af | bellard | CPU86_LDoubleU temp; |
212 | 2c0262af | bellard | int upper, e;
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213 | 2c0262af | bellard | uint64_t ll; |
214 | 2c0262af | bellard | |
215 | 2c0262af | bellard | /* mantissa */
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216 | 2c0262af | bellard | upper = lduw(ptr + 8);
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217 | 2c0262af | bellard | /* XXX: handle overflow ? */
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218 | 2c0262af | bellard | e = (upper & 0x7fff) - 16383 + EXPBIAS; /* exponent */ |
219 | 2c0262af | bellard | e |= (upper >> 4) & 0x800; /* sign */ |
220 | 2c0262af | bellard | ll = (ldq(ptr) >> 11) & ((1LL << 52) - 1); |
221 | 2c0262af | bellard | #ifdef __arm__
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222 | 2c0262af | bellard | temp.l.upper = (e << 20) | (ll >> 32); |
223 | 2c0262af | bellard | temp.l.lower = ll; |
224 | 2c0262af | bellard | #else
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225 | 2c0262af | bellard | temp.ll = ll | ((uint64_t)e << 52);
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226 | 2c0262af | bellard | #endif
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227 | 2c0262af | bellard | return temp.d;
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228 | 2c0262af | bellard | } |
229 | 2c0262af | bellard | |
230 | 664e0f19 | bellard | static inline void helper_fstt(CPU86_LDouble f, target_ulong ptr) |
231 | 2c0262af | bellard | { |
232 | 2c0262af | bellard | CPU86_LDoubleU temp; |
233 | 2c0262af | bellard | int e;
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234 | 2c0262af | bellard | |
235 | 2c0262af | bellard | temp.d = f; |
236 | 2c0262af | bellard | /* mantissa */
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237 | 2c0262af | bellard | stq(ptr, (MANTD(temp) << 11) | (1LL << 63)); |
238 | 2c0262af | bellard | /* exponent + sign */
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239 | 2c0262af | bellard | e = EXPD(temp) - EXPBIAS + 16383;
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240 | 2c0262af | bellard | e |= SIGND(temp) >> 16;
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241 | 2c0262af | bellard | stw(ptr + 8, e);
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242 | 2c0262af | bellard | } |
243 | 9951bf39 | bellard | #else
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244 | 9951bf39 | bellard | |
245 | 9951bf39 | bellard | /* we use memory access macros */
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246 | 9951bf39 | bellard | |
247 | 14ce26e7 | bellard | static inline CPU86_LDouble helper_fldt(target_ulong ptr) |
248 | 9951bf39 | bellard | { |
249 | 9951bf39 | bellard | CPU86_LDoubleU temp; |
250 | 9951bf39 | bellard | |
251 | 9951bf39 | bellard | temp.l.lower = ldq(ptr); |
252 | 9951bf39 | bellard | temp.l.upper = lduw(ptr + 8);
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253 | 9951bf39 | bellard | return temp.d;
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254 | 9951bf39 | bellard | } |
255 | 9951bf39 | bellard | |
256 | 14ce26e7 | bellard | static inline void helper_fstt(CPU86_LDouble f, target_ulong ptr) |
257 | 9951bf39 | bellard | { |
258 | 9951bf39 | bellard | CPU86_LDoubleU temp; |
259 | 3b46e624 | ths | |
260 | 9951bf39 | bellard | temp.d = f; |
261 | 9951bf39 | bellard | stq(ptr, temp.l.lower); |
262 | 9951bf39 | bellard | stw(ptr + 8, temp.l.upper);
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263 | 9951bf39 | bellard | } |
264 | 9951bf39 | bellard | |
265 | 9951bf39 | bellard | #endif /* USE_X86LDOUBLE */ |
266 | 2c0262af | bellard | |
267 | 2ee73ac3 | bellard | #define FPUS_IE (1 << 0) |
268 | 2ee73ac3 | bellard | #define FPUS_DE (1 << 1) |
269 | 2ee73ac3 | bellard | #define FPUS_ZE (1 << 2) |
270 | 2ee73ac3 | bellard | #define FPUS_OE (1 << 3) |
271 | 2ee73ac3 | bellard | #define FPUS_UE (1 << 4) |
272 | 2ee73ac3 | bellard | #define FPUS_PE (1 << 5) |
273 | 2ee73ac3 | bellard | #define FPUS_SF (1 << 6) |
274 | 2ee73ac3 | bellard | #define FPUS_SE (1 << 7) |
275 | 2ee73ac3 | bellard | #define FPUS_B (1 << 15) |
276 | 2ee73ac3 | bellard | |
277 | 2ee73ac3 | bellard | #define FPUC_EM 0x3f |
278 | 2ee73ac3 | bellard | |
279 | 2c0262af | bellard | static inline uint32_t compute_eflags(void) |
280 | 2c0262af | bellard | { |
281 | a7812ae4 | pbrook | return env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK);
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282 | 2c0262af | bellard | } |
283 | 2c0262af | bellard | |
284 | 2c0262af | bellard | /* NOTE: CC_OP must be modified manually to CC_OP_EFLAGS */
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285 | 2c0262af | bellard | static inline void load_eflags(int eflags, int update_mask) |
286 | 2c0262af | bellard | { |
287 | 2c0262af | bellard | CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
288 | 2c0262af | bellard | DF = 1 - (2 * ((eflags >> 10) & 1)); |
289 | 5fafdf24 | ths | env->eflags = (env->eflags & ~update_mask) | |
290 | 093f8f06 | bellard | (eflags & update_mask) | 0x2;
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291 | 2c0262af | bellard | } |
292 | 2c0262af | bellard | |
293 | 0d1a29f9 | bellard | static inline void env_to_regs(void) |
294 | 0d1a29f9 | bellard | { |
295 | 0d1a29f9 | bellard | #ifdef reg_EAX
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296 | 0d1a29f9 | bellard | EAX = env->regs[R_EAX]; |
297 | 0d1a29f9 | bellard | #endif
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298 | 0d1a29f9 | bellard | #ifdef reg_ECX
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299 | 0d1a29f9 | bellard | ECX = env->regs[R_ECX]; |
300 | 0d1a29f9 | bellard | #endif
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301 | 0d1a29f9 | bellard | #ifdef reg_EDX
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302 | 0d1a29f9 | bellard | EDX = env->regs[R_EDX]; |
303 | 0d1a29f9 | bellard | #endif
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304 | 0d1a29f9 | bellard | #ifdef reg_EBX
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305 | 0d1a29f9 | bellard | EBX = env->regs[R_EBX]; |
306 | 0d1a29f9 | bellard | #endif
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307 | 0d1a29f9 | bellard | #ifdef reg_ESP
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308 | 0d1a29f9 | bellard | ESP = env->regs[R_ESP]; |
309 | 0d1a29f9 | bellard | #endif
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310 | 0d1a29f9 | bellard | #ifdef reg_EBP
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311 | 0d1a29f9 | bellard | EBP = env->regs[R_EBP]; |
312 | 0d1a29f9 | bellard | #endif
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313 | 0d1a29f9 | bellard | #ifdef reg_ESI
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314 | 0d1a29f9 | bellard | ESI = env->regs[R_ESI]; |
315 | 0d1a29f9 | bellard | #endif
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316 | 0d1a29f9 | bellard | #ifdef reg_EDI
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317 | 0d1a29f9 | bellard | EDI = env->regs[R_EDI]; |
318 | 0d1a29f9 | bellard | #endif
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319 | 0d1a29f9 | bellard | } |
320 | 0d1a29f9 | bellard | |
321 | 0d1a29f9 | bellard | static inline void regs_to_env(void) |
322 | 0d1a29f9 | bellard | { |
323 | 0d1a29f9 | bellard | #ifdef reg_EAX
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324 | 0d1a29f9 | bellard | env->regs[R_EAX] = EAX; |
325 | 0d1a29f9 | bellard | #endif
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326 | 0d1a29f9 | bellard | #ifdef reg_ECX
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327 | 0d1a29f9 | bellard | env->regs[R_ECX] = ECX; |
328 | 0d1a29f9 | bellard | #endif
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329 | 0d1a29f9 | bellard | #ifdef reg_EDX
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330 | 0d1a29f9 | bellard | env->regs[R_EDX] = EDX; |
331 | 0d1a29f9 | bellard | #endif
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332 | 0d1a29f9 | bellard | #ifdef reg_EBX
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333 | 0d1a29f9 | bellard | env->regs[R_EBX] = EBX; |
334 | 0d1a29f9 | bellard | #endif
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335 | 0d1a29f9 | bellard | #ifdef reg_ESP
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336 | 0d1a29f9 | bellard | env->regs[R_ESP] = ESP; |
337 | 0d1a29f9 | bellard | #endif
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338 | 0d1a29f9 | bellard | #ifdef reg_EBP
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339 | 0d1a29f9 | bellard | env->regs[R_EBP] = EBP; |
340 | 0d1a29f9 | bellard | #endif
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341 | 0d1a29f9 | bellard | #ifdef reg_ESI
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342 | 0d1a29f9 | bellard | env->regs[R_ESI] = ESI; |
343 | 0d1a29f9 | bellard | #endif
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344 | 0d1a29f9 | bellard | #ifdef reg_EDI
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345 | 0d1a29f9 | bellard | env->regs[R_EDI] = EDI; |
346 | 0d1a29f9 | bellard | #endif
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347 | 0d1a29f9 | bellard | } |
348 | bfed01fc | ths | |
349 | 6a4955a8 | aliguori | static inline int cpu_has_work(CPUState *env) |
350 | 6a4955a8 | aliguori | { |
351 | 6a4955a8 | aliguori | int work;
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352 | 6a4955a8 | aliguori | |
353 | 6a4955a8 | aliguori | work = (env->interrupt_request & CPU_INTERRUPT_HARD) && |
354 | 6a4955a8 | aliguori | (env->eflags & IF_MASK); |
355 | 6a4955a8 | aliguori | work |= env->interrupt_request & CPU_INTERRUPT_NMI; |
356 | b09ea7d5 | Gleb Natapov | work |= env->interrupt_request & CPU_INTERRUPT_INIT; |
357 | b09ea7d5 | Gleb Natapov | work |= env->interrupt_request & CPU_INTERRUPT_SIPI; |
358 | 6a4955a8 | aliguori | |
359 | 6a4955a8 | aliguori | return work;
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360 | 6a4955a8 | aliguori | } |
361 | 6a4955a8 | aliguori | |
362 | bfed01fc | ths | static inline int cpu_halted(CPUState *env) { |
363 | bfed01fc | ths | /* handle exit of HALTED state */
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364 | ce5232c5 | bellard | if (!env->halted)
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365 | bfed01fc | ths | return 0; |
366 | bfed01fc | ths | /* disable halt condition */
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367 | 6a4955a8 | aliguori | if (cpu_has_work(env)) {
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368 | ce5232c5 | bellard | env->halted = 0;
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369 | bfed01fc | ths | return 0; |
370 | bfed01fc | ths | } |
371 | bfed01fc | ths | return EXCP_HALTED;
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372 | bfed01fc | ths | } |
373 | 0573fbfc | ths | |
374 | 5efc27bb | bellard | /* load efer and update the corresponding hflags. XXX: do consistency
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375 | 5efc27bb | bellard | checks with cpuid bits ? */
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376 | 5efc27bb | bellard | static inline void cpu_load_efer(CPUState *env, uint64_t val) |
377 | 5efc27bb | bellard | { |
378 | 5efc27bb | bellard | env->efer = val; |
379 | 5efc27bb | bellard | env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK); |
380 | 5efc27bb | bellard | if (env->efer & MSR_EFER_LMA)
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381 | 5efc27bb | bellard | env->hflags |= HF_LMA_MASK; |
382 | 5efc27bb | bellard | if (env->efer & MSR_EFER_SVME)
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383 | 5efc27bb | bellard | env->hflags |= HF_SVME_MASK; |
384 | 5efc27bb | bellard | } |