Revision 6fbe23d5 target-arm/cpu.h
| b/target-arm/cpu.h | ||
|---|---|---|
| 86 | 86 |
/* cpsr flag cache for faster execution */ |
| 87 | 87 |
uint32_t CF; /* 0 or 1 */ |
| 88 | 88 |
uint32_t VF; /* V is the bit 31. All other bits are undefined */ |
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uint32_t NZF; /* N is bit 31. Z is computed from NZF */ |
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| 89 |
uint32_t NF; /* N is bit 31. All other bits are undefined. */ |
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uint32_t ZF; /* Z set if zero. */ |
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| 90 | 91 |
uint32_t QF; /* 0 or 1 */ |
| 91 | 92 |
uint32_t GE; /* cpsr[19:16] */ |
| 92 | 93 |
uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ |
| ... | ... | |
| 254 | 255 |
static inline uint32_t xpsr_read(CPUARMState *env) |
| 255 | 256 |
{
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int ZF; |
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ZF = (env->NZF == 0);
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|
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return (env->NZF & 0x80000000) | (ZF << 30)
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|
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ZF = (env->ZF == 0); |
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return (env->NF & 0x80000000) | (ZF << 30) |
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| 259 | 260 |
| (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) |
| 260 | 261 |
| (env->thumb << 24) | ((env->condexec_bits & 3) << 25) |
| 261 | 262 |
| ((env->condexec_bits & 0xfc) << 8) |
| ... | ... | |
| 265 | 266 |
/* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ |
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static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) |
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{
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/* NOTE: N = 1 and Z = 1 cannot be stored currently */ |
|
| 269 | 269 |
if (mask & CPSR_NZCV) {
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env->NZF = (val & 0xc0000000) ^ 0x40000000; |
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env->ZF = (~val) & CPSR_Z; |
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env->NF = val; |
|
| 271 | 272 |
env->CF = (val >> 29) & 1; |
| 272 | 273 |
env->VF = (val << 3) & 0x80000000; |
| 273 | 274 |
} |
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