Revision 6fbe23d5 target-arm/translate.c
| b/target-arm/translate.c | ||
|---|---|---|
| 423 | 423 |
/* Set N and Z flags from var. */ |
| 424 | 424 |
static inline void gen_logic_CC(TCGv var) |
| 425 | 425 |
{
|
| 426 |
tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, NZF)); |
|
| 426 |
tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, NF)); |
|
| 427 |
tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, ZF)); |
|
| 427 | 428 |
} |
| 428 | 429 |
|
| 429 | 430 |
/* T0 += T1 + CF. */ |
| ... | ... | |
| 679 | 680 |
zero = tcg_const_i32(0); |
| 680 | 681 |
switch (cc) {
|
| 681 | 682 |
case 0: /* eq: Z */ |
| 682 |
tmp = load_cpu_field(NZF);
|
|
| 683 |
tmp = load_cpu_field(ZF); |
|
| 683 | 684 |
tcg_gen_brcond_i32(TCG_COND_EQ, tmp, zero, label); |
| 684 | 685 |
break; |
| 685 | 686 |
case 1: /* ne: !Z */ |
| 686 |
tmp = load_cpu_field(NZF);
|
|
| 687 |
tmp = load_cpu_field(ZF); |
|
| 687 | 688 |
tcg_gen_brcond_i32(TCG_COND_NE, tmp, zero, label); |
| 688 | 689 |
break; |
| 689 | 690 |
case 2: /* cs: C */ |
| ... | ... | |
| 695 | 696 |
tcg_gen_brcond_i32(TCG_COND_EQ, tmp, zero, label); |
| 696 | 697 |
break; |
| 697 | 698 |
case 4: /* mi: N */ |
| 698 |
tmp = load_cpu_field(NZF);
|
|
| 699 |
tmp = load_cpu_field(NF); |
|
| 699 | 700 |
tcg_gen_brcond_i32(TCG_COND_LT, tmp, zero, label); |
| 700 | 701 |
break; |
| 701 | 702 |
case 5: /* pl: !N */ |
| 702 |
tmp = load_cpu_field(NZF);
|
|
| 703 |
tmp = load_cpu_field(NF); |
|
| 703 | 704 |
tcg_gen_brcond_i32(TCG_COND_GE, tmp, zero, label); |
| 704 | 705 |
break; |
| 705 | 706 |
case 6: /* vs: V */ |
| ... | ... | |
| 715 | 716 |
tmp = load_cpu_field(CF); |
| 716 | 717 |
tcg_gen_brcond_i32(TCG_COND_EQ, tmp, zero, inv); |
| 717 | 718 |
dead_tmp(tmp); |
| 718 |
tmp = load_cpu_field(NZF);
|
|
| 719 |
tmp = load_cpu_field(ZF); |
|
| 719 | 720 |
tcg_gen_brcond_i32(TCG_COND_NE, tmp, zero, label); |
| 720 | 721 |
gen_set_label(inv); |
| 721 | 722 |
break; |
| ... | ... | |
| 723 | 724 |
tmp = load_cpu_field(CF); |
| 724 | 725 |
tcg_gen_brcond_i32(TCG_COND_EQ, tmp, zero, label); |
| 725 | 726 |
dead_tmp(tmp); |
| 726 |
tmp = load_cpu_field(NZF);
|
|
| 727 |
tmp = load_cpu_field(ZF); |
|
| 727 | 728 |
tcg_gen_brcond_i32(TCG_COND_EQ, tmp, zero, label); |
| 728 | 729 |
break; |
| 729 | 730 |
case 10: /* ge: N == V -> N ^ V == 0 */ |
| 730 | 731 |
tmp = load_cpu_field(VF); |
| 731 |
tmp2 = load_cpu_field(NZF);
|
|
| 732 |
tmp2 = load_cpu_field(NF); |
|
| 732 | 733 |
tcg_gen_xor_i32(tmp, tmp, tmp2); |
| 733 | 734 |
dead_tmp(tmp2); |
| 734 | 735 |
tcg_gen_brcond_i32(TCG_COND_GE, tmp, zero, label); |
| 735 | 736 |
break; |
| 736 | 737 |
case 11: /* lt: N != V -> N ^ V != 0 */ |
| 737 | 738 |
tmp = load_cpu_field(VF); |
| 738 |
tmp2 = load_cpu_field(NZF);
|
|
| 739 |
tmp2 = load_cpu_field(NF); |
|
| 739 | 740 |
tcg_gen_xor_i32(tmp, tmp, tmp2); |
| 740 | 741 |
dead_tmp(tmp2); |
| 741 | 742 |
tcg_gen_brcond_i32(TCG_COND_LT, tmp, zero, label); |
| 742 | 743 |
break; |
| 743 | 744 |
case 12: /* gt: !Z && N == V */ |
| 744 | 745 |
inv = gen_new_label(); |
| 745 |
tmp = load_cpu_field(NZF);
|
|
| 746 |
tmp = load_cpu_field(ZF); |
|
| 746 | 747 |
tcg_gen_brcond_i32(TCG_COND_EQ, tmp, zero, inv); |
| 747 | 748 |
dead_tmp(tmp); |
| 748 | 749 |
tmp = load_cpu_field(VF); |
| 749 |
tmp2 = load_cpu_field(NZF);
|
|
| 750 |
tmp2 = load_cpu_field(NF); |
|
| 750 | 751 |
tcg_gen_xor_i32(tmp, tmp, tmp2); |
| 751 | 752 |
dead_tmp(tmp2); |
| 752 | 753 |
tcg_gen_brcond_i32(TCG_COND_GE, tmp, zero, label); |
| 753 | 754 |
gen_set_label(inv); |
| 754 | 755 |
break; |
| 755 | 756 |
case 13: /* le: Z || N != V */ |
| 756 |
tmp = load_cpu_field(NZF);
|
|
| 757 |
tmp = load_cpu_field(ZF); |
|
| 757 | 758 |
tcg_gen_brcond_i32(TCG_COND_EQ, tmp, zero, label); |
| 758 | 759 |
dead_tmp(tmp); |
| 759 | 760 |
tmp = load_cpu_field(VF); |
| 760 |
tmp2 = load_cpu_field(NZF);
|
|
| 761 |
tmp2 = load_cpu_field(NF); |
|
| 761 | 762 |
tcg_gen_xor_i32(tmp, tmp, tmp2); |
| 762 | 763 |
dead_tmp(tmp2); |
| 763 | 764 |
tcg_gen_brcond_i32(TCG_COND_LT, tmp, zero, label); |
| ... | ... | |
| 5641 | 5642 |
{
|
| 5642 | 5643 |
TCGv tmp = new_tmp(); |
| 5643 | 5644 |
gen_helper_logicq_cc(tmp, val); |
| 5644 |
store_cpu_field(tmp, NZF); |
|
| 5645 |
gen_logic_CC(tmp); |
|
| 5646 |
dead_tmp(tmp); |
|
| 5645 | 5647 |
} |
| 5646 | 5648 |
|
| 5647 | 5649 |
static void disas_arm_insn(CPUState * env, DisasContext *s) |
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