/ - Diff - qemu - Greek Research and Technology Network's projects

b/hw/ide.c
1047	1047	}
1048	1048	}
1049	1049
1050		static void ide_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
	1050	static void ide_ioport_write(CPUState *env, uint32_t addr, uint32_t val)
1051	1051	{
1052	1052	IDEState *ide_if = get_ide_interface(addr);
1053	1053	IDEState *s = ide_if->cur_drive;
...	...
1198	1198	}
1199	1199	}
1200	1200
1201		static uint32_t ide_ioport_read(CPUX86State *env, uint32_t addr1)
	1201	static uint32_t ide_ioport_read(CPUState *env, uint32_t addr1)
1202	1202	{
1203	1203	IDEState *s = get_ide_interface(addr1)->cur_drive;
1204	1204	uint32_t addr;
...	...
1239	1239	return ret;
1240	1240	}
1241	1241
1242		static uint32_t ide_status_read(CPUX86State *env, uint32_t addr)
	1242	static uint32_t ide_status_read(CPUState *env, uint32_t addr)
1243	1243	{
1244	1244	IDEState *s = get_ide_interface(addr)->cur_drive;
1245	1245	int ret;
...	...
1250	1250	return ret;
1251	1251	}
1252	1252
1253		static void ide_cmd_write(CPUX86State *env, uint32_t addr, uint32_t val)
	1253	static void ide_cmd_write(CPUState *env, uint32_t addr, uint32_t val)
1254	1254	{
1255	1255	IDEState *ide_if = get_ide_interface(addr);
1256	1256	IDEState *s;
...	...
1285	1285	ide_if[1].cmd = val;
1286	1286	}
1287	1287
1288		static void ide_data_writew(CPUX86State *env, uint32_t addr, uint32_t val)
	1288	static void ide_data_writew(CPUState *env, uint32_t addr, uint32_t val)
1289	1289	{
1290	1290	IDEState *s = get_ide_interface(addr)->cur_drive;
1291	1291	uint8_t *p;
...	...
1298	1298	s->end_transfer_func(s);
1299	1299	}
1300	1300
1301		static uint32_t ide_data_readw(CPUX86State *env, uint32_t addr)
	1301	static uint32_t ide_data_readw(CPUState *env, uint32_t addr)
1302	1302	{
1303	1303	IDEState *s = get_ide_interface(addr)->cur_drive;
1304	1304	uint8_t *p;
...	...
1312	1312	return ret;
1313	1313	}
1314	1314
1315		static void ide_data_writel(CPUX86State *env, uint32_t addr, uint32_t val)
	1315	static void ide_data_writel(CPUState *env, uint32_t addr, uint32_t val)
1316	1316	{
1317	1317	IDEState *s = get_ide_interface(addr)->cur_drive;
1318	1318	uint8_t *p;
...	...
1325	1325	s->end_transfer_func(s);
1326	1326	}
1327	1327
1328		static uint32_t ide_data_readl(CPUX86State *env, uint32_t addr)
	1328	static uint32_t ide_data_readl(CPUState *env, uint32_t addr)
1329	1329	{
1330	1330	IDEState *s = get_ide_interface(addr)->cur_drive;
1331	1331	uint8_t *p;

     #endif
     #define IO_READ_PROTO(name) \
         uint32_t name (struct CPUX86State *env, uint32_t nport)
         uint32_t name (struct CPUState *env, uint32_t nport)
     #define IO_WRITE_PROTO(name) \
         void name (struct CPUX86State *env, uint32_t nport, uint32_t val)
         void name (struct CPUState *env, uint32_t nport, uint32_t val)
     static struct {
         int ver_lo;

     VGAState vga_state;
     int vga_io_memory;
     static uint32_t vga_ioport_read(CPUX86State *env, uint32_t addr)
     static uint32_t vga_ioport_read(CPUState *env, uint32_t addr)
+    {
         VGAState *s = &vga_state;
         int val, index;
-...
         return val;
+    }
     static void vga_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
     static void vga_ioport_write(CPUState *env, uint32_t addr, uint32_t val)
+    {
         VGAState *s = &vga_state;
         int index, v;
-...
         vga_mem_writel,
     };
     int vga_init(DisplayState *ds, uint8_t *vga_ram_base,
                  unsigned long vga_ram_offset, int vga_ram_size)
     int vga_initialize(DisplayState *ds, uint8_t *vga_ram_base,
                        unsigned long vga_ram_offset, int vga_ram_size)
+    {
         VGAState *s = &vga_state;
         int i, j, v, b;
-...
         register_ioport_read(0x3da, 1, vga_ioport_read, 1);
         vga_io_memory = cpu_register_io_memory(0, vga_mem_read, vga_mem_write);
         cpu_register_physical_memory(0xa0000, 0x20000, vga_io_memory);
     #if defined (TARGET_I386)
         cpu_register_physical_memory(0x000a0000, 0x20000, vga_io_memory);
     #elif defined (TARGET_PPC)
         cpu_register_physical_memory(0xf00a0000, 0x20000, vga_io_memory);
     #endif
         return 0;
+    }

     #define VL_H
     /* vl.c */
     struct CPUX86State;
     struct CPUState;
     extern int reset_requested;
     extern int64_t ticks_per_sec;
     typedef void (IOPortWriteFunc)(struct CPUX86State *env, uint32_t address, uint32_t data);
     typedef uint32_t (IOPortReadFunc)(struct CPUX86State *env, uint32_t address);
     typedef void (IOPortWriteFunc)(struct CPUState *env, uint32_t address, uint32_t data);
     typedef uint32_t (IOPortReadFunc)(struct CPUState *env, uint32_t address);
     void *get_mmap_addr(unsigned long size);
     int register_ioport_read(int start, int length, IOPortReadFunc *func, int size);
-...
         s->dpy_resize(s, w, h);
+    }
     int vga_init(DisplayState *ds, uint8_t *vga_ram_base,
                  unsigned long vga_ram_offset, int vga_ram_size);
     int vga_initialize(DisplayState *ds, uint8_t *vga_ram_base,
                        unsigned long vga_ram_offset, int vga_ram_size);
     void vga_update_display(void);
     /* sdl.c */
-...
     void SB16_run (void);
     void SB16_init (void);
     /* fdc.c */
     #define MAX_FD 2
     extern BlockDriverState *fd_table[MAX_FD];
     void cmos_register_fd (uint8_t fd0, uint8_t fd1);
     void fdctrl_init (int irq_lvl, int dma_chann, int mem_mapped, uint32_t base,
                       char boot_device);
     int fdctrl_disk_change (int idx, const unsigned char *filename, int ro);
     #endif /* VL_H */

Archipelago » qemu

Revision 7138fcfb