Revision 71817e48
b/target-sparc/translate.c | ||
---|---|---|
4178 | 4178 |
unsigned int xop = GET_FIELD(insn, 7, 12); |
4179 | 4179 |
|
4180 | 4180 |
cpu_src1 = get_src1(insn, cpu_src1); |
4181 |
if (xop == 0x3c || xop == 0x3e) |
|
4182 |
{ |
|
4181 |
if (xop == 0x3c || xop == 0x3e) { // V9 casa/casxa |
|
4183 | 4182 |
rs2 = GET_FIELD(insn, 27, 31); |
4184 | 4183 |
gen_movl_reg_TN(rs2, cpu_src2); |
4185 |
}
|
|
4186 |
else if (IS_IMM) { /* immediate */
|
|
4184 |
tcg_gen_mov_tl(cpu_addr, cpu_src1);
|
|
4185 |
} else if (IS_IMM) { /* immediate */
|
|
4187 | 4186 |
rs2 = GET_FIELDs(insn, 19, 31); |
4188 | 4187 |
tcg_gen_addi_tl(cpu_addr, cpu_src1, (int)rs2); |
4189 | 4188 |
} else { /* register */ |
... | ... | |
4615 | 4614 |
gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd)); |
4616 | 4615 |
break; |
4617 | 4616 |
case 0x3c: /* V9 casa */ |
4618 |
gen_cas_asi(cpu_val, cpu_addr, cpu_val, insn, rd);
|
|
4617 |
gen_cas_asi(cpu_val, cpu_addr, cpu_src2, insn, rd);
|
|
4619 | 4618 |
gen_movl_TN_reg(rd, cpu_val); |
4620 | 4619 |
break; |
4621 | 4620 |
case 0x3e: /* V9 casxa */ |
4622 |
gen_casx_asi(cpu_val, cpu_addr, cpu_val, insn, rd);
|
|
4621 |
gen_casx_asi(cpu_val, cpu_addr, cpu_src2, insn, rd);
|
|
4623 | 4622 |
gen_movl_TN_reg(rd, cpu_val); |
4624 | 4623 |
break; |
4625 | 4624 |
#else |
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