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1
/*
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   SPARC translation
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4
   Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
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   Copyright (C) 2003-2005 Fabrice Bellard
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   This library is free software; you can redistribute it and/or
8
   modify it under the terms of the GNU Lesser General Public
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   License as published by the Free Software Foundation; either
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   version 2 of the License, or (at your option) any later version.
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   This library is distributed in the hope that it will be useful,
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   but WITHOUT ANY WARRANTY; without even the implied warranty of
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   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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   Lesser General Public License for more details.
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   You should have received a copy of the GNU Lesser General Public
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   License along with this library; if not, write to the Free Software
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   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
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#include <stdarg.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <inttypes.h>
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#include "cpu.h"
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#include "exec-all.h"
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#include "disas.h"
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#include "helper.h"
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#include "tcg-op.h"
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34
#define DEBUG_DISAS
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#define DYNAMIC_PC  1 /* dynamic pc value */
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#define JUMP_PC     2 /* dynamic pc value which takes only two values
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                         according to jump_pc[T2] */
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/* global register indexes */
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static TCGv cpu_env, cpu_regwptr;
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static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
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static TCGv cpu_psr, cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8];
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static TCGv cpu_cond, cpu_src1, cpu_src2, cpu_dst, cpu_addr, cpu_val;
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#ifdef TARGET_SPARC64
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static TCGv cpu_xcc;
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#endif
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/* local register indexes (only used inside old micro ops) */
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static TCGv cpu_tmp0, cpu_tmp32, cpu_tmp64;
50

    
51
#include "gen-icount.h"
52

    
53
typedef struct DisasContext {
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    target_ulong pc;    /* current Program Counter: integer or DYNAMIC_PC */
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    target_ulong npc;   /* next PC: integer or DYNAMIC_PC or JUMP_PC */
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    target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
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    int is_br;
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    int mem_idx;
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    int fpu_enabled;
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    struct TranslationBlock *tb;
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    uint32_t features;
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} DisasContext;
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// This function uses non-native bit order
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#define GET_FIELD(X, FROM, TO) \
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  ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
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// This function uses the order in the manuals, i.e. bit 0 is 2^0
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#define GET_FIELD_SP(X, FROM, TO) \
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    GET_FIELD(X, 31 - (TO), 31 - (FROM))
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#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
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#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
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75
#ifdef TARGET_SPARC64
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#define FFPREG(r) (r)
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#define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
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#define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
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#else
80
#define FFPREG(r) (r)
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#define DFPREG(r) (r & 0x1e)
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#define QFPREG(r) (r & 0x1c)
83
#endif
84

    
85
static int sign_extend(int x, int len)
86
{
87
    len = 32 - len;
88
    return (x << len) >> len;
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}
90

    
91
#define IS_IMM (insn & (1<<13))
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93
/* floating point registers moves */
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static void gen_op_load_fpr_FT0(unsigned int src)
95
{
96
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0));
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}
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100
static void gen_op_load_fpr_FT1(unsigned int src)
101
{
102
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft1));
104
}
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106
static void gen_op_store_FT0_fpr(unsigned int dst)
107
{
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    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
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}
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static void gen_op_load_fpr_DT0(unsigned int src)
113
{
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    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
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                   offsetof(CPU_DoubleU, l.upper));
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    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
119
                   offsetof(CPU_DoubleU, l.lower));
120
}
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122
static void gen_op_load_fpr_DT1(unsigned int src)
123
{
124
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) +
126
                   offsetof(CPU_DoubleU, l.upper));
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    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
128
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) +
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                   offsetof(CPU_DoubleU, l.lower));
130
}
131

    
132
static void gen_op_store_DT0_fpr(unsigned int dst)
133
{
134
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
135
                   offsetof(CPU_DoubleU, l.upper));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
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    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
138
                   offsetof(CPU_DoubleU, l.lower));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
140
}
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static void gen_op_load_fpr_QT0(unsigned int src)
143
{
144
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
146
                   offsetof(CPU_QuadU, l.upmost));
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    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
148
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
149
                   offsetof(CPU_QuadU, l.upper));
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    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
152
                   offsetof(CPU_QuadU, l.lower));
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    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
155
                   offsetof(CPU_QuadU, l.lowest));
156
}
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158
static void gen_op_load_fpr_QT1(unsigned int src)
159
{
160
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
161
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
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                   offsetof(CPU_QuadU, l.upmost));
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    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
164
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
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                   offsetof(CPU_QuadU, l.upper));
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    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
167
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
168
                   offsetof(CPU_QuadU, l.lower));
169
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
170
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
171
                   offsetof(CPU_QuadU, l.lowest));
172
}
173

    
174
static void gen_op_store_QT0_fpr(unsigned int dst)
175
{
176
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
177
                   offsetof(CPU_QuadU, l.upmost));
178
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
179
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
180
                   offsetof(CPU_QuadU, l.upper));
181
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
182
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
183
                   offsetof(CPU_QuadU, l.lower));
184
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 2]));
185
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
186
                   offsetof(CPU_QuadU, l.lowest));
187
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 3]));
188
}
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190
/* moves */
191
#ifdef CONFIG_USER_ONLY
192
#define supervisor(dc) 0
193
#ifdef TARGET_SPARC64
194
#define hypervisor(dc) 0
195
#endif
196
#else
197
#define supervisor(dc) (dc->mem_idx >= 1)
198
#ifdef TARGET_SPARC64
199
#define hypervisor(dc) (dc->mem_idx == 2)
200
#else
201
#endif
202
#endif
203

    
204
#ifdef TARGET_ABI32
205
#define ABI32_MASK(addr) tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
206
#else
207
#define ABI32_MASK(addr)
208
#endif
209

    
210
static inline void gen_movl_reg_TN(int reg, TCGv tn)
211
{
212
    if (reg == 0)
213
        tcg_gen_movi_tl(tn, 0);
214
    else if (reg < 8)
215
        tcg_gen_mov_tl(tn, cpu_gregs[reg]);
216
    else {
217
        tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
218
    }
219
}
220

    
221
static inline void gen_movl_TN_reg(int reg, TCGv tn)
222
{
223
    if (reg == 0)
224
        return;
225
    else if (reg < 8)
226
        tcg_gen_mov_tl(cpu_gregs[reg], tn);
227
    else {
228
        tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
229
    }
230
}
231

    
232
static inline void gen_goto_tb(DisasContext *s, int tb_num,
233
                               target_ulong pc, target_ulong npc)
234
{
235
    TranslationBlock *tb;
236

    
237
    tb = s->tb;
238
    if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
239
        (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK))  {
240
        /* jump to same page: we can use a direct jump */
241
        tcg_gen_goto_tb(tb_num);
242
        tcg_gen_movi_tl(cpu_pc, pc);
243
        tcg_gen_movi_tl(cpu_npc, npc);
244
        tcg_gen_exit_tb((long)tb + tb_num);
245
    } else {
246
        /* jump to another page: currently not optimized */
247
        tcg_gen_movi_tl(cpu_pc, pc);
248
        tcg_gen_movi_tl(cpu_npc, npc);
249
        tcg_gen_exit_tb(0);
250
    }
251
}
252

    
253
// XXX suboptimal
254
static inline void gen_mov_reg_N(TCGv reg, TCGv src)
255
{
256
    tcg_gen_extu_i32_tl(reg, src);
257
    tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT);
258
    tcg_gen_andi_tl(reg, reg, 0x1);
259
}
260

    
261
static inline void gen_mov_reg_Z(TCGv reg, TCGv src)
262
{
263
    tcg_gen_extu_i32_tl(reg, src);
264
    tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT);
265
    tcg_gen_andi_tl(reg, reg, 0x1);
266
}
267

    
268
static inline void gen_mov_reg_V(TCGv reg, TCGv src)
269
{
270
    tcg_gen_extu_i32_tl(reg, src);
271
    tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT);
272
    tcg_gen_andi_tl(reg, reg, 0x1);
273
}
274

    
275
static inline void gen_mov_reg_C(TCGv reg, TCGv src)
276
{
277
    tcg_gen_extu_i32_tl(reg, src);
278
    tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT);
279
    tcg_gen_andi_tl(reg, reg, 0x1);
280
}
281

    
282
static inline void gen_cc_clear_icc(void)
283
{
284
    tcg_gen_movi_i32(cpu_psr, 0);
285
}
286

    
287
#ifdef TARGET_SPARC64
288
static inline void gen_cc_clear_xcc(void)
289
{
290
    tcg_gen_movi_i32(cpu_xcc, 0);
291
}
292
#endif
293

    
294
/* old op:
295
    if (!T0)
296
        env->psr |= PSR_ZERO;
297
    if ((int32_t) T0 < 0)
298
        env->psr |= PSR_NEG;
299
*/
300
static inline void gen_cc_NZ_icc(TCGv dst)
301
{
302
    TCGv r_temp;
303
    int l1, l2;
304

    
305
    l1 = gen_new_label();
306
    l2 = gen_new_label();
307
    r_temp = tcg_temp_new(TCG_TYPE_TL);
308
    tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
309
    tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1);
310
    tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO);
311
    gen_set_label(l1);
312
    tcg_gen_ext_i32_tl(r_temp, dst);
313
    tcg_gen_brcondi_tl(TCG_COND_GE, r_temp, 0, l2);
314
    tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG);
315
    gen_set_label(l2);
316
    tcg_temp_free(r_temp);
317
}
318

    
319
#ifdef TARGET_SPARC64
320
static inline void gen_cc_NZ_xcc(TCGv dst)
321
{
322
    int l1, l2;
323

    
324
    l1 = gen_new_label();
325
    l2 = gen_new_label();
326
    tcg_gen_brcondi_tl(TCG_COND_NE, dst, 0, l1);
327
    tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_ZERO);
328
    gen_set_label(l1);
329
    tcg_gen_brcondi_tl(TCG_COND_GE, dst, 0, l2);
330
    tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_NEG);
331
    gen_set_label(l2);
332
}
333
#endif
334

    
335
/* old op:
336
    if (T0 < src1)
337
        env->psr |= PSR_CARRY;
338
*/
339
static inline void gen_cc_C_add_icc(TCGv dst, TCGv src1)
340
{
341
    TCGv r_temp;
342
    int l1;
343

    
344
    l1 = gen_new_label();
345
    r_temp = tcg_temp_new(TCG_TYPE_TL);
346
    tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
347
    tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1);
348
    tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
349
    gen_set_label(l1);
350
    tcg_temp_free(r_temp);
351
}
352

    
353
#ifdef TARGET_SPARC64
354
static inline void gen_cc_C_add_xcc(TCGv dst, TCGv src1)
355
{
356
    int l1;
357

    
358
    l1 = gen_new_label();
359
    tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1);
360
    tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
361
    gen_set_label(l1);
362
}
363
#endif
364

    
365
/* old op:
366
    if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
367
        env->psr |= PSR_OVF;
368
*/
369
static inline void gen_cc_V_add_icc(TCGv dst, TCGv src1, TCGv src2)
370
{
371
    TCGv r_temp;
372

    
373
    r_temp = tcg_temp_new(TCG_TYPE_TL);
374
    tcg_gen_xor_tl(r_temp, src1, src2);
375
    tcg_gen_xori_tl(r_temp, r_temp, -1);
376
    tcg_gen_xor_tl(cpu_tmp0, src1, dst);
377
    tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
378
    tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
379
    tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
380
    tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
381
    tcg_temp_free(r_temp);
382
    tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);
383
}
384

    
385
#ifdef TARGET_SPARC64
386
static inline void gen_cc_V_add_xcc(TCGv dst, TCGv src1, TCGv src2)
387
{
388
    TCGv r_temp;
389

    
390
    r_temp = tcg_temp_new(TCG_TYPE_TL);
391
    tcg_gen_xor_tl(r_temp, src1, src2);
392
    tcg_gen_xori_tl(r_temp, r_temp, -1);
393
    tcg_gen_xor_tl(cpu_tmp0, src1, dst);
394
    tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
395
    tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
396
    tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
397
    tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
398
    tcg_temp_free(r_temp);
399
    tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);
400
}
401
#endif
402

    
403
static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2)
404
{
405
    TCGv r_temp, r_const;
406
    int l1;
407

    
408
    l1 = gen_new_label();
409

    
410
    r_temp = tcg_temp_new(TCG_TYPE_TL);
411
    tcg_gen_xor_tl(r_temp, src1, src2);
412
    tcg_gen_xori_tl(r_temp, r_temp, -1);
413
    tcg_gen_xor_tl(cpu_tmp0, src1, dst);
414
    tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
415
    tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
416
    tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
417
    r_const = tcg_const_i32(TT_TOVF);
418
    tcg_gen_helper_0_1(raise_exception, r_const);
419
    tcg_temp_free(r_const);
420
    gen_set_label(l1);
421
    tcg_temp_free(r_temp);
422
}
423

    
424
static inline void gen_cc_V_tag(TCGv src1, TCGv src2)
425
{
426
    int l1;
427

    
428
    l1 = gen_new_label();
429
    tcg_gen_or_tl(cpu_tmp0, src1, src2);
430
    tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
431
    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
432
    tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
433
    gen_set_label(l1);
434
}
435

    
436
static inline void gen_tag_tv(TCGv src1, TCGv src2)
437
{
438
    int l1;
439
    TCGv r_const;
440

    
441
    l1 = gen_new_label();
442
    tcg_gen_or_tl(cpu_tmp0, src1, src2);
443
    tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
444
    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
445
    r_const = tcg_const_i32(TT_TOVF);
446
    tcg_gen_helper_0_1(raise_exception, r_const);
447
    tcg_temp_free(r_const);
448
    gen_set_label(l1);
449
}
450

    
451
static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
452
{
453
    tcg_gen_mov_tl(cpu_cc_src, src1);
454
    tcg_gen_mov_tl(cpu_cc_src2, src2);
455
    tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
456
    gen_cc_clear_icc();
457
    gen_cc_NZ_icc(cpu_cc_dst);
458
    gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
459
    gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
460
#ifdef TARGET_SPARC64
461
    gen_cc_clear_xcc();
462
    gen_cc_NZ_xcc(cpu_cc_dst);
463
    gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
464
    gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
465
#endif
466
    tcg_gen_mov_tl(dst, cpu_cc_dst);
467
}
468

    
469
static inline void gen_op_addx_cc(TCGv dst, TCGv src1, TCGv src2)
470
{
471
    tcg_gen_mov_tl(cpu_cc_src, src1);
472
    tcg_gen_mov_tl(cpu_cc_src2, src2);
473
    gen_mov_reg_C(cpu_tmp0, cpu_psr);
474
    tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
475
    gen_cc_clear_icc();
476
    gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
477
#ifdef TARGET_SPARC64
478
    gen_cc_clear_xcc();
479
    gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
480
#endif
481
    tcg_gen_add_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2);
482
    gen_cc_NZ_icc(cpu_cc_dst);
483
    gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
484
    gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
485
#ifdef TARGET_SPARC64
486
    gen_cc_NZ_xcc(cpu_cc_dst);
487
    gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
488
    gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
489
#endif
490
    tcg_gen_mov_tl(dst, cpu_cc_dst);
491
}
492

    
493
static inline void gen_op_tadd_cc(TCGv dst, TCGv src1, TCGv src2)
494
{
495
    tcg_gen_mov_tl(cpu_cc_src, src1);
496
    tcg_gen_mov_tl(cpu_cc_src2, src2);
497
    tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
498
    gen_cc_clear_icc();
499
    gen_cc_NZ_icc(cpu_cc_dst);
500
    gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
501
    gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
502
    gen_cc_V_tag(cpu_cc_src, cpu_cc_src2);
503
#ifdef TARGET_SPARC64
504
    gen_cc_clear_xcc();
505
    gen_cc_NZ_xcc(cpu_cc_dst);
506
    gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
507
    gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
508
#endif
509
    tcg_gen_mov_tl(dst, cpu_cc_dst);
510
}
511

    
512
static inline void gen_op_tadd_ccTV(TCGv dst, TCGv src1, TCGv src2)
513
{
514
    tcg_gen_mov_tl(cpu_cc_src, src1);
515
    tcg_gen_mov_tl(cpu_cc_src2, src2);
516
    gen_tag_tv(cpu_cc_src, cpu_cc_src2);
517
    tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
518
    gen_add_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
519
    gen_cc_clear_icc();
520
    gen_cc_NZ_icc(cpu_cc_dst);
521
    gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
522
#ifdef TARGET_SPARC64
523
    gen_cc_clear_xcc();
524
    gen_cc_NZ_xcc(cpu_cc_dst);
525
    gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
526
    gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
527
#endif
528
    tcg_gen_mov_tl(dst, cpu_cc_dst);
529
}
530

    
531
/* old op:
532
    if (src1 < T1)
533
        env->psr |= PSR_CARRY;
534
*/
535
static inline void gen_cc_C_sub_icc(TCGv src1, TCGv src2)
536
{
537
    TCGv r_temp1, r_temp2;
538
    int l1;
539

    
540
    l1 = gen_new_label();
541
    r_temp1 = tcg_temp_new(TCG_TYPE_TL);
542
    r_temp2 = tcg_temp_new(TCG_TYPE_TL);
543
    tcg_gen_andi_tl(r_temp1, src1, 0xffffffffULL);
544
    tcg_gen_andi_tl(r_temp2, src2, 0xffffffffULL);
545
    tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1);
546
    tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
547
    gen_set_label(l1);
548
    tcg_temp_free(r_temp1);
549
    tcg_temp_free(r_temp2);
550
}
551

    
552
#ifdef TARGET_SPARC64
553
static inline void gen_cc_C_sub_xcc(TCGv src1, TCGv src2)
554
{
555
    int l1;
556

    
557
    l1 = gen_new_label();
558
    tcg_gen_brcond_tl(TCG_COND_GEU, src1, src2, l1);
559
    tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
560
    gen_set_label(l1);
561
}
562
#endif
563

    
564
/* old op:
565
    if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
566
        env->psr |= PSR_OVF;
567
*/
568
static inline void gen_cc_V_sub_icc(TCGv dst, TCGv src1, TCGv src2)
569
{
570
    TCGv r_temp;
571

    
572
    r_temp = tcg_temp_new(TCG_TYPE_TL);
573
    tcg_gen_xor_tl(r_temp, src1, src2);
574
    tcg_gen_xor_tl(cpu_tmp0, src1, dst);
575
    tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
576
    tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
577
    tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
578
    tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
579
    tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);
580
    tcg_temp_free(r_temp);
581
}
582

    
583
#ifdef TARGET_SPARC64
584
static inline void gen_cc_V_sub_xcc(TCGv dst, TCGv src1, TCGv src2)
585
{
586
    TCGv r_temp;
587

    
588
    r_temp = tcg_temp_new(TCG_TYPE_TL);
589
    tcg_gen_xor_tl(r_temp, src1, src2);
590
    tcg_gen_xor_tl(cpu_tmp0, src1, dst);
591
    tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
592
    tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
593
    tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
594
    tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
595
    tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);
596
    tcg_temp_free(r_temp);
597
}
598
#endif
599

    
600
static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2)
601
{
602
    TCGv r_temp, r_const;
603
    int l1;
604

    
605
    l1 = gen_new_label();
606

    
607
    r_temp = tcg_temp_new(TCG_TYPE_TL);
608
    tcg_gen_xor_tl(r_temp, src1, src2);
609
    tcg_gen_xor_tl(cpu_tmp0, src1, dst);
610
    tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
611
    tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
612
    tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
613
    r_const = tcg_const_i32(TT_TOVF);
614
    tcg_gen_helper_0_1(raise_exception, r_const);
615
    tcg_temp_free(r_const);
616
    gen_set_label(l1);
617
    tcg_temp_free(r_temp);
618
}
619

    
620
static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
621
{
622
    tcg_gen_mov_tl(cpu_cc_src, src1);
623
    tcg_gen_mov_tl(cpu_cc_src2, src2);
624
    tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
625
    gen_cc_clear_icc();
626
    gen_cc_NZ_icc(cpu_cc_dst);
627
    gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
628
    gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
629
#ifdef TARGET_SPARC64
630
    gen_cc_clear_xcc();
631
    gen_cc_NZ_xcc(cpu_cc_dst);
632
    gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
633
    gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
634
#endif
635
    tcg_gen_mov_tl(dst, cpu_cc_dst);
636
}
637

    
638
static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2)
639
{
640
    tcg_gen_mov_tl(cpu_cc_src, src1);
641
    tcg_gen_mov_tl(cpu_cc_src2, src2);
642
    gen_mov_reg_C(cpu_tmp0, cpu_psr);
643
    tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
644
    gen_cc_clear_icc();
645
    gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src);
646
#ifdef TARGET_SPARC64
647
    gen_cc_clear_xcc();
648
    gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src);
649
#endif
650
    tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2);
651
    gen_cc_NZ_icc(cpu_cc_dst);
652
    gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src);
653
    gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
654
#ifdef TARGET_SPARC64
655
    gen_cc_NZ_xcc(cpu_cc_dst);
656
    gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src);
657
    gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
658
#endif
659
    tcg_gen_mov_tl(dst, cpu_cc_dst);
660
}
661

    
662
static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2)
663
{
664
    tcg_gen_mov_tl(cpu_cc_src, src1);
665
    tcg_gen_mov_tl(cpu_cc_src2, src2);
666
    tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
667
    gen_cc_clear_icc();
668
    gen_cc_NZ_icc(cpu_cc_dst);
669
    gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
670
    gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
671
    gen_cc_V_tag(cpu_cc_src, cpu_cc_src2);
672
#ifdef TARGET_SPARC64
673
    gen_cc_clear_xcc();
674
    gen_cc_NZ_xcc(cpu_cc_dst);
675
    gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
676
    gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
677
#endif
678
    tcg_gen_mov_tl(dst, cpu_cc_dst);
679
}
680

    
681
static inline void gen_op_tsub_ccTV(TCGv dst, TCGv src1, TCGv src2)
682
{
683
    tcg_gen_mov_tl(cpu_cc_src, src1);
684
    tcg_gen_mov_tl(cpu_cc_src2, src2);
685
    gen_tag_tv(cpu_cc_src, cpu_cc_src2);
686
    tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
687
    gen_sub_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
688
    gen_cc_clear_icc();
689
    gen_cc_NZ_icc(cpu_cc_dst);
690
    gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
691
#ifdef TARGET_SPARC64
692
    gen_cc_clear_xcc();
693
    gen_cc_NZ_xcc(cpu_cc_dst);
694
    gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
695
    gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
696
#endif
697
    tcg_gen_mov_tl(dst, cpu_cc_dst);
698
}
699

    
700
static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
701
{
702
    TCGv r_temp, r_temp2;
703
    int l1;
704

    
705
    l1 = gen_new_label();
706
    r_temp = tcg_temp_new(TCG_TYPE_TL);
707
    r_temp2 = tcg_temp_new(TCG_TYPE_I32);
708

    
709
    /* old op:
710
    if (!(env->y & 1))
711
        T1 = 0;
712
    */
713
    tcg_gen_mov_tl(cpu_cc_src, src1);
714
    tcg_gen_ld32u_tl(r_temp, cpu_env, offsetof(CPUSPARCState, y));
715
    tcg_gen_trunc_tl_i32(r_temp2, r_temp);
716
    tcg_gen_andi_i32(r_temp2, r_temp2, 0x1);
717
    tcg_gen_mov_tl(cpu_cc_src2, src2);
718
    tcg_gen_brcondi_i32(TCG_COND_NE, r_temp2, 0, l1);
719
    tcg_gen_movi_tl(cpu_cc_src2, 0);
720
    gen_set_label(l1);
721

    
722
    // b2 = T0 & 1;
723
    // env->y = (b2 << 31) | (env->y >> 1);
724
    tcg_gen_trunc_tl_i32(r_temp2, cpu_cc_src);
725
    tcg_gen_andi_i32(r_temp2, r_temp2, 0x1);
726
    tcg_gen_shli_i32(r_temp2, r_temp2, 31);
727
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y));
728
    tcg_gen_shri_i32(cpu_tmp32, cpu_tmp32, 1);
729
    tcg_gen_or_i32(cpu_tmp32, cpu_tmp32, r_temp2);
730
    tcg_temp_free(r_temp2);
731
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y));
732

    
733
    // b1 = N ^ V;
734
    gen_mov_reg_N(cpu_tmp0, cpu_psr);
735
    gen_mov_reg_V(r_temp, cpu_psr);
736
    tcg_gen_xor_tl(cpu_tmp0, cpu_tmp0, r_temp);
737
    tcg_temp_free(r_temp);
738

    
739
    // T0 = (b1 << 31) | (T0 >> 1);
740
    // src1 = T0;
741
    tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, 31);
742
    tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1);
743
    tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
744

    
745
    /* do addition and update flags */
746
    tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
747

    
748
    gen_cc_clear_icc();
749
    gen_cc_NZ_icc(cpu_cc_dst);
750
    gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
751
    gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
752
    tcg_gen_mov_tl(dst, cpu_cc_dst);
753
}
754

    
755
static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
756
{
757
    TCGv r_temp, r_temp2;
758

    
759
    r_temp = tcg_temp_new(TCG_TYPE_I64);
760
    r_temp2 = tcg_temp_new(TCG_TYPE_I64);
761

    
762
    tcg_gen_extu_tl_i64(r_temp, src2);
763
    tcg_gen_extu_tl_i64(r_temp2, src1);
764
    tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
765

    
766
    tcg_gen_shri_i64(r_temp, r_temp2, 32);
767
    tcg_gen_trunc_i64_i32(r_temp, r_temp);
768
    tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y));
769
    tcg_temp_free(r_temp);
770
#ifdef TARGET_SPARC64
771
    tcg_gen_mov_i64(dst, r_temp2);
772
#else
773
    tcg_gen_trunc_i64_tl(dst, r_temp2);
774
#endif
775
    tcg_temp_free(r_temp2);
776
}
777

    
778
static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
779
{
780
    TCGv r_temp, r_temp2;
781

    
782
    r_temp = tcg_temp_new(TCG_TYPE_I64);
783
    r_temp2 = tcg_temp_new(TCG_TYPE_I64);
784

    
785
    tcg_gen_ext_tl_i64(r_temp, src2);
786
    tcg_gen_ext_tl_i64(r_temp2, src1);
787
    tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
788

    
789
    tcg_gen_shri_i64(r_temp, r_temp2, 32);
790
    tcg_gen_trunc_i64_i32(r_temp, r_temp);
791
    tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y));
792
    tcg_temp_free(r_temp);
793
#ifdef TARGET_SPARC64
794
    tcg_gen_mov_i64(dst, r_temp2);
795
#else
796
    tcg_gen_trunc_i64_tl(dst, r_temp2);
797
#endif
798
    tcg_temp_free(r_temp2);
799
}
800

    
801
#ifdef TARGET_SPARC64
802
static inline void gen_trap_ifdivzero_tl(TCGv divisor)
803
{
804
    TCGv r_const;
805
    int l1;
806

    
807
    l1 = gen_new_label();
808
    tcg_gen_brcondi_tl(TCG_COND_NE, divisor, 0, l1);
809
    r_const = tcg_const_i32(TT_DIV_ZERO);
810
    tcg_gen_helper_0_1(raise_exception, r_const);
811
    tcg_temp_free(r_const);
812
    gen_set_label(l1);
813
}
814

    
815
static inline void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2)
816
{
817
    int l1, l2;
818

    
819
    l1 = gen_new_label();
820
    l2 = gen_new_label();
821
    tcg_gen_mov_tl(cpu_cc_src, src1);
822
    tcg_gen_mov_tl(cpu_cc_src2, src2);
823
    gen_trap_ifdivzero_tl(cpu_cc_src2);
824
    tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src, INT64_MIN, l1);
825
    tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src2, -1, l1);
826
    tcg_gen_movi_i64(dst, INT64_MIN);
827
    tcg_gen_br(l2);
828
    gen_set_label(l1);
829
    tcg_gen_div_i64(dst, cpu_cc_src, cpu_cc_src2);
830
    gen_set_label(l2);
831
}
832
#endif
833

    
834
static inline void gen_op_div_cc(TCGv dst)
835
{
836
    int l1;
837

    
838
    tcg_gen_mov_tl(cpu_cc_dst, dst);
839
    gen_cc_clear_icc();
840
    gen_cc_NZ_icc(cpu_cc_dst);
841
    l1 = gen_new_label();
842
    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cc_src2, 0, l1);
843
    tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
844
    gen_set_label(l1);
845
}
846

    
847
static inline void gen_op_logic_cc(TCGv dst)
848
{
849
    tcg_gen_mov_tl(cpu_cc_dst, dst);
850

    
851
    gen_cc_clear_icc();
852
    gen_cc_NZ_icc(cpu_cc_dst);
853
#ifdef TARGET_SPARC64
854
    gen_cc_clear_xcc();
855
    gen_cc_NZ_xcc(cpu_cc_dst);
856
#endif
857
}
858

    
859
// 1
860
static inline void gen_op_eval_ba(TCGv dst)
861
{
862
    tcg_gen_movi_tl(dst, 1);
863
}
864

    
865
// Z
866
static inline void gen_op_eval_be(TCGv dst, TCGv src)
867
{
868
    gen_mov_reg_Z(dst, src);
869
}
870

    
871
// Z | (N ^ V)
872
static inline void gen_op_eval_ble(TCGv dst, TCGv src)
873
{
874
    gen_mov_reg_N(cpu_tmp0, src);
875
    gen_mov_reg_V(dst, src);
876
    tcg_gen_xor_tl(dst, dst, cpu_tmp0);
877
    gen_mov_reg_Z(cpu_tmp0, src);
878
    tcg_gen_or_tl(dst, dst, cpu_tmp0);
879
}
880

    
881
// N ^ V
882
static inline void gen_op_eval_bl(TCGv dst, TCGv src)
883
{
884
    gen_mov_reg_V(cpu_tmp0, src);
885
    gen_mov_reg_N(dst, src);
886
    tcg_gen_xor_tl(dst, dst, cpu_tmp0);
887
}
888

    
889
// C | Z
890
static inline void gen_op_eval_bleu(TCGv dst, TCGv src)
891
{
892
    gen_mov_reg_Z(cpu_tmp0, src);
893
    gen_mov_reg_C(dst, src);
894
    tcg_gen_or_tl(dst, dst, cpu_tmp0);
895
}
896

    
897
// C
898
static inline void gen_op_eval_bcs(TCGv dst, TCGv src)
899
{
900
    gen_mov_reg_C(dst, src);
901
}
902

    
903
// V
904
static inline void gen_op_eval_bvs(TCGv dst, TCGv src)
905
{
906
    gen_mov_reg_V(dst, src);
907
}
908

    
909
// 0
910
static inline void gen_op_eval_bn(TCGv dst)
911
{
912
    tcg_gen_movi_tl(dst, 0);
913
}
914

    
915
// N
916
static inline void gen_op_eval_bneg(TCGv dst, TCGv src)
917
{
918
    gen_mov_reg_N(dst, src);
919
}
920

    
921
// !Z
922
static inline void gen_op_eval_bne(TCGv dst, TCGv src)
923
{
924
    gen_mov_reg_Z(dst, src);
925
    tcg_gen_xori_tl(dst, dst, 0x1);
926
}
927

    
928
// !(Z | (N ^ V))
929
static inline void gen_op_eval_bg(TCGv dst, TCGv src)
930
{
931
    gen_mov_reg_N(cpu_tmp0, src);
932
    gen_mov_reg_V(dst, src);
933
    tcg_gen_xor_tl(dst, dst, cpu_tmp0);
934
    gen_mov_reg_Z(cpu_tmp0, src);
935
    tcg_gen_or_tl(dst, dst, cpu_tmp0);
936
    tcg_gen_xori_tl(dst, dst, 0x1);
937
}
938

    
939
// !(N ^ V)
940
static inline void gen_op_eval_bge(TCGv dst, TCGv src)
941
{
942
    gen_mov_reg_V(cpu_tmp0, src);
943
    gen_mov_reg_N(dst, src);
944
    tcg_gen_xor_tl(dst, dst, cpu_tmp0);
945
    tcg_gen_xori_tl(dst, dst, 0x1);
946
}
947

    
948
// !(C | Z)
949
static inline void gen_op_eval_bgu(TCGv dst, TCGv src)
950
{
951
    gen_mov_reg_Z(cpu_tmp0, src);
952
    gen_mov_reg_C(dst, src);
953
    tcg_gen_or_tl(dst, dst, cpu_tmp0);
954
    tcg_gen_xori_tl(dst, dst, 0x1);
955
}
956

    
957
// !C
958
static inline void gen_op_eval_bcc(TCGv dst, TCGv src)
959
{
960
    gen_mov_reg_C(dst, src);
961
    tcg_gen_xori_tl(dst, dst, 0x1);
962
}
963

    
964
// !N
965
static inline void gen_op_eval_bpos(TCGv dst, TCGv src)
966
{
967
    gen_mov_reg_N(dst, src);
968
    tcg_gen_xori_tl(dst, dst, 0x1);
969
}
970

    
971
// !V
972
static inline void gen_op_eval_bvc(TCGv dst, TCGv src)
973
{
974
    gen_mov_reg_V(dst, src);
975
    tcg_gen_xori_tl(dst, dst, 0x1);
976
}
977

    
978
/*
979
  FPSR bit field FCC1 | FCC0:
980
   0 =
981
   1 <
982
   2 >
983
   3 unordered
984
*/
985
static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,
986
                                    unsigned int fcc_offset)
987
{
988
    tcg_gen_extu_i32_tl(reg, src);
989
    tcg_gen_shri_tl(reg, reg, FSR_FCC0_SHIFT + fcc_offset);
990
    tcg_gen_andi_tl(reg, reg, 0x1);
991
}
992

    
993
static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,
994
                                    unsigned int fcc_offset)
995
{
996
    tcg_gen_extu_i32_tl(reg, src);
997
    tcg_gen_shri_tl(reg, reg, FSR_FCC1_SHIFT + fcc_offset);
998
    tcg_gen_andi_tl(reg, reg, 0x1);
999
}
1000

    
1001
// !0: FCC0 | FCC1
1002
static inline void gen_op_eval_fbne(TCGv dst, TCGv src,
1003
                                    unsigned int fcc_offset)
1004
{
1005
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1006
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1007
    tcg_gen_or_tl(dst, dst, cpu_tmp0);
1008
}
1009

    
1010
// 1 or 2: FCC0 ^ FCC1
1011
static inline void gen_op_eval_fblg(TCGv dst, TCGv src,
1012
                                    unsigned int fcc_offset)
1013
{
1014
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1015
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1016
    tcg_gen_xor_tl(dst, dst, cpu_tmp0);
1017
}
1018

    
1019
// 1 or 3: FCC0
1020
static inline void gen_op_eval_fbul(TCGv dst, TCGv src,
1021
                                    unsigned int fcc_offset)
1022
{
1023
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1024
}
1025

    
1026
// 1: FCC0 & !FCC1
1027
static inline void gen_op_eval_fbl(TCGv dst, TCGv src,
1028
                                    unsigned int fcc_offset)
1029
{
1030
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1031
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1032
    tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
1033
    tcg_gen_and_tl(dst, dst, cpu_tmp0);
1034
}
1035

    
1036
// 2 or 3: FCC1
1037
static inline void gen_op_eval_fbug(TCGv dst, TCGv src,
1038
                                    unsigned int fcc_offset)
1039
{
1040
    gen_mov_reg_FCC1(dst, src, fcc_offset);
1041
}
1042

    
1043
// 2: !FCC0 & FCC1
1044
static inline void gen_op_eval_fbg(TCGv dst, TCGv src,
1045
                                    unsigned int fcc_offset)
1046
{
1047
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1048
    tcg_gen_xori_tl(dst, dst, 0x1);
1049
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1050
    tcg_gen_and_tl(dst, dst, cpu_tmp0);
1051
}
1052

    
1053
// 3: FCC0 & FCC1
1054
static inline void gen_op_eval_fbu(TCGv dst, TCGv src,
1055
                                    unsigned int fcc_offset)
1056
{
1057
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1058
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1059
    tcg_gen_and_tl(dst, dst, cpu_tmp0);
1060
}
1061

    
1062
// 0: !(FCC0 | FCC1)
1063
static inline void gen_op_eval_fbe(TCGv dst, TCGv src,
1064
                                    unsigned int fcc_offset)
1065
{
1066
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1067
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1068
    tcg_gen_or_tl(dst, dst, cpu_tmp0);
1069
    tcg_gen_xori_tl(dst, dst, 0x1);
1070
}
1071

    
1072
// 0 or 3: !(FCC0 ^ FCC1)
1073
static inline void gen_op_eval_fbue(TCGv dst, TCGv src,
1074
                                    unsigned int fcc_offset)
1075
{
1076
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1077
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1078
    tcg_gen_xor_tl(dst, dst, cpu_tmp0);
1079
    tcg_gen_xori_tl(dst, dst, 0x1);
1080
}
1081

    
1082
// 0 or 2: !FCC0
1083
static inline void gen_op_eval_fbge(TCGv dst, TCGv src,
1084
                                    unsigned int fcc_offset)
1085
{
1086
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1087
    tcg_gen_xori_tl(dst, dst, 0x1);
1088
}
1089

    
1090
// !1: !(FCC0 & !FCC1)
1091
static inline void gen_op_eval_fbuge(TCGv dst, TCGv src,
1092
                                    unsigned int fcc_offset)
1093
{
1094
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1095
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1096
    tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
1097
    tcg_gen_and_tl(dst, dst, cpu_tmp0);
1098
    tcg_gen_xori_tl(dst, dst, 0x1);
1099
}
1100

    
1101
// 0 or 1: !FCC1
1102
static inline void gen_op_eval_fble(TCGv dst, TCGv src,
1103
                                    unsigned int fcc_offset)
1104
{
1105
    gen_mov_reg_FCC1(dst, src, fcc_offset);
1106
    tcg_gen_xori_tl(dst, dst, 0x1);
1107
}
1108

    
1109
// !2: !(!FCC0 & FCC1)
1110
static inline void gen_op_eval_fbule(TCGv dst, TCGv src,
1111
                                    unsigned int fcc_offset)
1112
{
1113
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1114
    tcg_gen_xori_tl(dst, dst, 0x1);
1115
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1116
    tcg_gen_and_tl(dst, dst, cpu_tmp0);
1117
    tcg_gen_xori_tl(dst, dst, 0x1);
1118
}
1119

    
1120
// !3: !(FCC0 & FCC1)
1121
static inline void gen_op_eval_fbo(TCGv dst, TCGv src,
1122
                                    unsigned int fcc_offset)
1123
{
1124
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1125
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1126
    tcg_gen_and_tl(dst, dst, cpu_tmp0);
1127
    tcg_gen_xori_tl(dst, dst, 0x1);
1128
}
1129

    
1130
static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
1131
                               target_ulong pc2, TCGv r_cond)
1132
{
1133
    int l1;
1134

    
1135
    l1 = gen_new_label();
1136

    
1137
    tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1138

    
1139
    gen_goto_tb(dc, 0, pc1, pc1 + 4);
1140

    
1141
    gen_set_label(l1);
1142
    gen_goto_tb(dc, 1, pc2, pc2 + 4);
1143
}
1144

    
1145
static inline void gen_branch_a(DisasContext *dc, target_ulong pc1,
1146
                                target_ulong pc2, TCGv r_cond)
1147
{
1148
    int l1;
1149

    
1150
    l1 = gen_new_label();
1151

    
1152
    tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1153

    
1154
    gen_goto_tb(dc, 0, pc2, pc1);
1155

    
1156
    gen_set_label(l1);
1157
    gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
1158
}
1159

    
1160
static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2,
1161
                                      TCGv r_cond)
1162
{
1163
    int l1, l2;
1164

    
1165
    l1 = gen_new_label();
1166
    l2 = gen_new_label();
1167

    
1168
    tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1169

    
1170
    tcg_gen_movi_tl(cpu_npc, npc1);
1171
    tcg_gen_br(l2);
1172

    
1173
    gen_set_label(l1);
1174
    tcg_gen_movi_tl(cpu_npc, npc2);
1175
    gen_set_label(l2);
1176
}
1177

    
1178
/* call this function before using the condition register as it may
1179
   have been set for a jump */
1180
static inline void flush_cond(DisasContext *dc, TCGv cond)
1181
{
1182
    if (dc->npc == JUMP_PC) {
1183
        gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1184
        dc->npc = DYNAMIC_PC;
1185
    }
1186
}
1187

    
1188
static inline void save_npc(DisasContext *dc, TCGv cond)
1189
{
1190
    if (dc->npc == JUMP_PC) {
1191
        gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1192
        dc->npc = DYNAMIC_PC;
1193
    } else if (dc->npc != DYNAMIC_PC) {
1194
        tcg_gen_movi_tl(cpu_npc, dc->npc);
1195
    }
1196
}
1197

    
1198
static inline void save_state(DisasContext *dc, TCGv cond)
1199
{
1200
    tcg_gen_movi_tl(cpu_pc, dc->pc);
1201
    save_npc(dc, cond);
1202
}
1203

    
1204
static inline void gen_mov_pc_npc(DisasContext *dc, TCGv cond)
1205
{
1206
    if (dc->npc == JUMP_PC) {
1207
        gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1208
        tcg_gen_mov_tl(cpu_pc, cpu_npc);
1209
        dc->pc = DYNAMIC_PC;
1210
    } else if (dc->npc == DYNAMIC_PC) {
1211
        tcg_gen_mov_tl(cpu_pc, cpu_npc);
1212
        dc->pc = DYNAMIC_PC;
1213
    } else {
1214
        dc->pc = dc->npc;
1215
    }
1216
}
1217

    
1218
static inline void gen_op_next_insn(void)
1219
{
1220
    tcg_gen_mov_tl(cpu_pc, cpu_npc);
1221
    tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
1222
}
1223

    
1224
static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond)
1225
{
1226
    TCGv r_src;
1227

    
1228
#ifdef TARGET_SPARC64
1229
    if (cc)
1230
        r_src = cpu_xcc;
1231
    else
1232
        r_src = cpu_psr;
1233
#else
1234
    r_src = cpu_psr;
1235
#endif
1236
    switch (cond) {
1237
    case 0x0:
1238
        gen_op_eval_bn(r_dst);
1239
        break;
1240
    case 0x1:
1241
        gen_op_eval_be(r_dst, r_src);
1242
        break;
1243
    case 0x2:
1244
        gen_op_eval_ble(r_dst, r_src);
1245
        break;
1246
    case 0x3:
1247
        gen_op_eval_bl(r_dst, r_src);
1248
        break;
1249
    case 0x4:
1250
        gen_op_eval_bleu(r_dst, r_src);
1251
        break;
1252
    case 0x5:
1253
        gen_op_eval_bcs(r_dst, r_src);
1254
        break;
1255
    case 0x6:
1256
        gen_op_eval_bneg(r_dst, r_src);
1257
        break;
1258
    case 0x7:
1259
        gen_op_eval_bvs(r_dst, r_src);
1260
        break;
1261
    case 0x8:
1262
        gen_op_eval_ba(r_dst);
1263
        break;
1264
    case 0x9:
1265
        gen_op_eval_bne(r_dst, r_src);
1266
        break;
1267
    case 0xa:
1268
        gen_op_eval_bg(r_dst, r_src);
1269
        break;
1270
    case 0xb:
1271
        gen_op_eval_bge(r_dst, r_src);
1272
        break;
1273
    case 0xc:
1274
        gen_op_eval_bgu(r_dst, r_src);
1275
        break;
1276
    case 0xd:
1277
        gen_op_eval_bcc(r_dst, r_src);
1278
        break;
1279
    case 0xe:
1280
        gen_op_eval_bpos(r_dst, r_src);
1281
        break;
1282
    case 0xf:
1283
        gen_op_eval_bvc(r_dst, r_src);
1284
        break;
1285
    }
1286
}
1287

    
1288
static inline void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond)
1289
{
1290
    unsigned int offset;
1291

    
1292
    switch (cc) {
1293
    default:
1294
    case 0x0:
1295
        offset = 0;
1296
        break;
1297
    case 0x1:
1298
        offset = 32 - 10;
1299
        break;
1300
    case 0x2:
1301
        offset = 34 - 10;
1302
        break;
1303
    case 0x3:
1304
        offset = 36 - 10;
1305
        break;
1306
    }
1307

    
1308
    switch (cond) {
1309
    case 0x0:
1310
        gen_op_eval_bn(r_dst);
1311
        break;
1312
    case 0x1:
1313
        gen_op_eval_fbne(r_dst, cpu_fsr, offset);
1314
        break;
1315
    case 0x2:
1316
        gen_op_eval_fblg(r_dst, cpu_fsr, offset);
1317
        break;
1318
    case 0x3:
1319
        gen_op_eval_fbul(r_dst, cpu_fsr, offset);
1320
        break;
1321
    case 0x4:
1322
        gen_op_eval_fbl(r_dst, cpu_fsr, offset);
1323
        break;
1324
    case 0x5:
1325
        gen_op_eval_fbug(r_dst, cpu_fsr, offset);
1326
        break;
1327
    case 0x6:
1328
        gen_op_eval_fbg(r_dst, cpu_fsr, offset);
1329
        break;
1330
    case 0x7:
1331
        gen_op_eval_fbu(r_dst, cpu_fsr, offset);
1332
        break;
1333
    case 0x8:
1334
        gen_op_eval_ba(r_dst);
1335
        break;
1336
    case 0x9:
1337
        gen_op_eval_fbe(r_dst, cpu_fsr, offset);
1338
        break;
1339
    case 0xa:
1340
        gen_op_eval_fbue(r_dst, cpu_fsr, offset);
1341
        break;
1342
    case 0xb:
1343
        gen_op_eval_fbge(r_dst, cpu_fsr, offset);
1344
        break;
1345
    case 0xc:
1346
        gen_op_eval_fbuge(r_dst, cpu_fsr, offset);
1347
        break;
1348
    case 0xd:
1349
        gen_op_eval_fble(r_dst, cpu_fsr, offset);
1350
        break;
1351
    case 0xe:
1352
        gen_op_eval_fbule(r_dst, cpu_fsr, offset);
1353
        break;
1354
    case 0xf:
1355
        gen_op_eval_fbo(r_dst, cpu_fsr, offset);
1356
        break;
1357
    }
1358
}
1359

    
1360
#ifdef TARGET_SPARC64
1361
// Inverted logic
1362
static const int gen_tcg_cond_reg[8] = {
1363
    -1,
1364
    TCG_COND_NE,
1365
    TCG_COND_GT,
1366
    TCG_COND_GE,
1367
    -1,
1368
    TCG_COND_EQ,
1369
    TCG_COND_LE,
1370
    TCG_COND_LT,
1371
};
1372

    
1373
static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src)
1374
{
1375
    int l1;
1376

    
1377
    l1 = gen_new_label();
1378
    tcg_gen_movi_tl(r_dst, 0);
1379
    tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], r_src, 0, l1);
1380
    tcg_gen_movi_tl(r_dst, 1);
1381
    gen_set_label(l1);
1382
}
1383
#endif
1384

    
1385
/* XXX: potentially incorrect if dynamic npc */
1386
static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1387
                      TCGv r_cond)
1388
{
1389
    unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1390
    target_ulong target = dc->pc + offset;
1391

    
1392
    if (cond == 0x0) {
1393
        /* unconditional not taken */
1394
        if (a) {
1395
            dc->pc = dc->npc + 4;
1396
            dc->npc = dc->pc + 4;
1397
        } else {
1398
            dc->pc = dc->npc;
1399
            dc->npc = dc->pc + 4;
1400
        }
1401
    } else if (cond == 0x8) {
1402
        /* unconditional taken */
1403
        if (a) {
1404
            dc->pc = target;
1405
            dc->npc = dc->pc + 4;
1406
        } else {
1407
            dc->pc = dc->npc;
1408
            dc->npc = target;
1409
        }
1410
    } else {
1411
        flush_cond(dc, r_cond);
1412
        gen_cond(r_cond, cc, cond);
1413
        if (a) {
1414
            gen_branch_a(dc, target, dc->npc, r_cond);
1415
            dc->is_br = 1;
1416
        } else {
1417
            dc->pc = dc->npc;
1418
            dc->jump_pc[0] = target;
1419
            dc->jump_pc[1] = dc->npc + 4;
1420
            dc->npc = JUMP_PC;
1421
        }
1422
    }
1423
}
1424

    
1425
/* XXX: potentially incorrect if dynamic npc */
1426
static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1427
                      TCGv r_cond)
1428
{
1429
    unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1430
    target_ulong target = dc->pc + offset;
1431

    
1432
    if (cond == 0x0) {
1433
        /* unconditional not taken */
1434
        if (a) {
1435
            dc->pc = dc->npc + 4;
1436
            dc->npc = dc->pc + 4;
1437
        } else {
1438
            dc->pc = dc->npc;
1439
            dc->npc = dc->pc + 4;
1440
        }
1441
    } else if (cond == 0x8) {
1442
        /* unconditional taken */
1443
        if (a) {
1444
            dc->pc = target;
1445
            dc->npc = dc->pc + 4;
1446
        } else {
1447
            dc->pc = dc->npc;
1448
            dc->npc = target;
1449
        }
1450
    } else {
1451
        flush_cond(dc, r_cond);
1452
        gen_fcond(r_cond, cc, cond);
1453
        if (a) {
1454
            gen_branch_a(dc, target, dc->npc, r_cond);
1455
            dc->is_br = 1;
1456
        } else {
1457
            dc->pc = dc->npc;
1458
            dc->jump_pc[0] = target;
1459
            dc->jump_pc[1] = dc->npc + 4;
1460
            dc->npc = JUMP_PC;
1461
        }
1462
    }
1463
}
1464

    
1465
#ifdef TARGET_SPARC64
1466
/* XXX: potentially incorrect if dynamic npc */
1467
static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn,
1468
                          TCGv r_cond, TCGv r_reg)
1469
{
1470
    unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
1471
    target_ulong target = dc->pc + offset;
1472

    
1473
    flush_cond(dc, r_cond);
1474
    gen_cond_reg(r_cond, cond, r_reg);
1475
    if (a) {
1476
        gen_branch_a(dc, target, dc->npc, r_cond);
1477
        dc->is_br = 1;
1478
    } else {
1479
        dc->pc = dc->npc;
1480
        dc->jump_pc[0] = target;
1481
        dc->jump_pc[1] = dc->npc + 4;
1482
        dc->npc = JUMP_PC;
1483
    }
1484
}
1485

    
1486
static GenOpFunc * const gen_fcmps[4] = {
1487
    helper_fcmps,
1488
    helper_fcmps_fcc1,
1489
    helper_fcmps_fcc2,
1490
    helper_fcmps_fcc3,
1491
};
1492

    
1493
static GenOpFunc * const gen_fcmpd[4] = {
1494
    helper_fcmpd,
1495
    helper_fcmpd_fcc1,
1496
    helper_fcmpd_fcc2,
1497
    helper_fcmpd_fcc3,
1498
};
1499

    
1500
static GenOpFunc * const gen_fcmpq[4] = {
1501
    helper_fcmpq,
1502
    helper_fcmpq_fcc1,
1503
    helper_fcmpq_fcc2,
1504
    helper_fcmpq_fcc3,
1505
};
1506

    
1507
static GenOpFunc * const gen_fcmpes[4] = {
1508
    helper_fcmpes,
1509
    helper_fcmpes_fcc1,
1510
    helper_fcmpes_fcc2,
1511
    helper_fcmpes_fcc3,
1512
};
1513

    
1514
static GenOpFunc * const gen_fcmped[4] = {
1515
    helper_fcmped,
1516
    helper_fcmped_fcc1,
1517
    helper_fcmped_fcc2,
1518
    helper_fcmped_fcc3,
1519
};
1520

    
1521
static GenOpFunc * const gen_fcmpeq[4] = {
1522
    helper_fcmpeq,
1523
    helper_fcmpeq_fcc1,
1524
    helper_fcmpeq_fcc2,
1525
    helper_fcmpeq_fcc3,
1526
};
1527

    
1528
static inline void gen_op_fcmps(int fccno)
1529
{
1530
    tcg_gen_helper_0_0(gen_fcmps[fccno]);
1531
}
1532

    
1533
static inline void gen_op_fcmpd(int fccno)
1534
{
1535
    tcg_gen_helper_0_0(gen_fcmpd[fccno]);
1536
}
1537

    
1538
static inline void gen_op_fcmpq(int fccno)
1539
{
1540
    tcg_gen_helper_0_0(gen_fcmpq[fccno]);
1541
}
1542

    
1543
static inline void gen_op_fcmpes(int fccno)
1544
{
1545
    tcg_gen_helper_0_0(gen_fcmpes[fccno]);
1546
}
1547

    
1548
static inline void gen_op_fcmped(int fccno)
1549
{
1550
    tcg_gen_helper_0_0(gen_fcmped[fccno]);
1551
}
1552

    
1553
static inline void gen_op_fcmpeq(int fccno)
1554
{
1555
    tcg_gen_helper_0_0(gen_fcmpeq[fccno]);
1556
}
1557

    
1558
#else
1559

    
1560
static inline void gen_op_fcmps(int fccno)
1561
{
1562
    tcg_gen_helper_0_0(helper_fcmps);
1563
}
1564

    
1565
static inline void gen_op_fcmpd(int fccno)
1566
{
1567
    tcg_gen_helper_0_0(helper_fcmpd);
1568
}
1569

    
1570
static inline void gen_op_fcmpq(int fccno)
1571
{
1572
    tcg_gen_helper_0_0(helper_fcmpq);
1573
}
1574

    
1575
static inline void gen_op_fcmpes(int fccno)
1576
{
1577
    tcg_gen_helper_0_0(helper_fcmpes);
1578
}
1579

    
1580
static inline void gen_op_fcmped(int fccno)
1581
{
1582
    tcg_gen_helper_0_0(helper_fcmped);
1583
}
1584

    
1585
static inline void gen_op_fcmpeq(int fccno)
1586
{
1587
    tcg_gen_helper_0_0(helper_fcmpeq);
1588
}
1589
#endif
1590

    
1591
static inline void gen_op_fpexception_im(int fsr_flags)
1592
{
1593
    TCGv r_const;
1594

    
1595
    tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~FSR_FTT_MASK);
1596
    tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);
1597
    r_const = tcg_const_i32(TT_FP_EXCP);
1598
    tcg_gen_helper_0_1(raise_exception, r_const);
1599
    tcg_temp_free(r_const);
1600
}
1601

    
1602
static int gen_trap_ifnofpu(DisasContext *dc, TCGv r_cond)
1603
{
1604
#if !defined(CONFIG_USER_ONLY)
1605
    if (!dc->fpu_enabled) {
1606
        TCGv r_const;
1607

    
1608
        save_state(dc, r_cond);
1609
        r_const = tcg_const_i32(TT_NFPU_INSN);
1610
        tcg_gen_helper_0_1(raise_exception, r_const);
1611
        tcg_temp_free(r_const);
1612
        dc->is_br = 1;
1613
        return 1;
1614
    }
1615
#endif
1616
    return 0;
1617
}
1618

    
1619
static inline void gen_op_clear_ieee_excp_and_FTT(void)
1620
{
1621
    tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~(FSR_FTT_MASK | FSR_CEXC_MASK));
1622
}
1623

    
1624
static inline void gen_clear_float_exceptions(void)
1625
{
1626
    tcg_gen_helper_0_0(helper_clear_float_exceptions);
1627
}
1628

    
1629
/* asi moves */
1630
#ifdef TARGET_SPARC64
1631
static inline TCGv gen_get_asi(int insn, TCGv r_addr)
1632
{
1633
    int asi, offset;
1634
    TCGv r_asi;
1635

    
1636
    if (IS_IMM) {
1637
        r_asi = tcg_temp_new(TCG_TYPE_I32);
1638
        offset = GET_FIELD(insn, 25, 31);
1639
        tcg_gen_addi_tl(r_addr, r_addr, offset);
1640
        tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
1641
    } else {
1642
        asi = GET_FIELD(insn, 19, 26);
1643
        r_asi = tcg_const_i32(asi);
1644
    }
1645
    return r_asi;
1646
}
1647

    
1648
static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
1649
                              int sign)
1650
{
1651
    TCGv r_asi, r_size, r_sign;
1652

    
1653
    r_asi = gen_get_asi(insn, addr);
1654
    r_size = tcg_const_i32(size);
1655
    r_sign = tcg_const_i32(sign);
1656
    tcg_gen_helper_1_4(helper_ld_asi, dst, addr, r_asi, r_size, r_sign);
1657
    tcg_temp_free(r_sign);
1658
    tcg_temp_free(r_size);
1659
    tcg_temp_free(r_asi);
1660
}
1661

    
1662
static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1663
{
1664
    TCGv r_asi, r_size;
1665

    
1666
    r_asi = gen_get_asi(insn, addr);
1667
    r_size = tcg_const_i32(size);
1668
    tcg_gen_helper_0_4(helper_st_asi, addr, src, r_asi, r_size);
1669
    tcg_temp_free(r_size);
1670
    tcg_temp_free(r_asi);
1671
}
1672

    
1673
static inline void gen_ldf_asi(TCGv addr, int insn, int size, int rd)
1674
{
1675
    TCGv r_asi, r_size, r_rd;
1676

    
1677
    r_asi = gen_get_asi(insn, addr);
1678
    r_size = tcg_const_i32(size);
1679
    r_rd = tcg_const_i32(rd);
1680
    tcg_gen_helper_0_4(helper_ldf_asi, addr, r_asi, r_size, r_rd);
1681
    tcg_temp_free(r_rd);
1682
    tcg_temp_free(r_size);
1683
    tcg_temp_free(r_asi);
1684
}
1685

    
1686
static inline void gen_stf_asi(TCGv addr, int insn, int size, int rd)
1687
{
1688
    TCGv r_asi, r_size, r_rd;
1689

    
1690
    r_asi = gen_get_asi(insn, addr);
1691
    r_size = tcg_const_i32(size);
1692
    r_rd = tcg_const_i32(rd);
1693
    tcg_gen_helper_0_4(helper_stf_asi, addr, r_asi, r_size, r_rd);
1694
    tcg_temp_free(r_rd);
1695
    tcg_temp_free(r_size);
1696
    tcg_temp_free(r_asi);
1697
}
1698

    
1699
static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1700
{
1701
    TCGv r_asi, r_size, r_sign;
1702

    
1703
    r_asi = gen_get_asi(insn, addr);
1704
    r_size = tcg_const_i32(4);
1705
    r_sign = tcg_const_i32(0);
1706
    tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1707
    tcg_temp_free(r_sign);
1708
    tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi, r_size);
1709
    tcg_temp_free(r_size);
1710
    tcg_temp_free(r_asi);
1711
    tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1712
}
1713

    
1714
static inline void gen_ldda_asi(TCGv lo, TCGv hi, TCGv addr, int insn)
1715
{
1716
    TCGv r_asi, r_size, r_sign;
1717

    
1718
    r_asi = gen_get_asi(insn, addr);
1719
    r_size = tcg_const_i32(8);
1720
    r_sign = tcg_const_i32(0);
1721
    tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1722
    tcg_temp_free(r_sign);
1723
    tcg_temp_free(r_size);
1724
    tcg_temp_free(r_asi);
1725
    tcg_gen_andi_i64(lo, cpu_tmp64, 0xffffffffULL);
1726
    tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
1727
    tcg_gen_andi_i64(hi, cpu_tmp64, 0xffffffffULL);
1728
}
1729

    
1730
static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
1731
{
1732
    TCGv r_temp, r_asi, r_size;
1733

    
1734
    r_temp = tcg_temp_new(TCG_TYPE_TL);
1735
    gen_movl_reg_TN(rd + 1, r_temp);
1736
    tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi,
1737
                       r_temp);
1738
    tcg_temp_free(r_temp);
1739
    r_asi = gen_get_asi(insn, addr);
1740
    r_size = tcg_const_i32(8);
1741
    tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size);
1742
    tcg_temp_free(r_size);
1743
    tcg_temp_free(r_asi);
1744
}
1745

    
1746
static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn,
1747
                               int rd)
1748
{
1749
    TCGv r_val1, r_asi;
1750

    
1751
    r_val1 = tcg_temp_new(TCG_TYPE_TL);
1752
    gen_movl_reg_TN(rd, r_val1);
1753
    r_asi = gen_get_asi(insn, addr);
1754
    tcg_gen_helper_1_4(helper_cas_asi, dst, addr, r_val1, val2, r_asi);
1755
    tcg_temp_free(r_asi);
1756
    tcg_temp_free(r_val1);
1757
}
1758

    
1759
static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn,
1760
                                int rd)
1761
{
1762
    TCGv r_asi;
1763

    
1764
    gen_movl_reg_TN(rd, cpu_tmp64);
1765
    r_asi = gen_get_asi(insn, addr);
1766
    tcg_gen_helper_1_4(helper_casx_asi, dst, addr, cpu_tmp64, val2, r_asi);
1767
    tcg_temp_free(r_asi);
1768
}
1769

    
1770
#elif !defined(CONFIG_USER_ONLY)
1771

    
1772
static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
1773
                              int sign)
1774
{
1775
    TCGv r_asi, r_size, r_sign;
1776

    
1777
    r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1778
    r_size = tcg_const_i32(size);
1779
    r_sign = tcg_const_i32(sign);
1780
    tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1781
    tcg_temp_free(r_sign);
1782
    tcg_temp_free(r_size);
1783
    tcg_temp_free(r_asi);
1784
    tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1785
}
1786

    
1787
static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1788
{
1789
    TCGv r_asi, r_size;
1790

    
1791
    tcg_gen_extu_tl_i64(cpu_tmp64, src);
1792
    r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1793
    r_size = tcg_const_i32(size);
1794
    tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size);
1795
    tcg_temp_free(r_size);
1796
    tcg_temp_free(r_asi);
1797
}
1798

    
1799
static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1800
{
1801
    TCGv r_asi, r_size, r_sign;
1802

    
1803
    r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1804
    r_size = tcg_const_i32(4);
1805
    r_sign = tcg_const_i32(0);
1806
    tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1807
    tcg_temp_free(r_sign);
1808
    tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi, r_size);
1809
    tcg_temp_free(r_size);
1810
    tcg_temp_free(r_asi);
1811
    tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1812
}
1813

    
1814
static inline void gen_ldda_asi(TCGv lo, TCGv hi, TCGv addr, int insn)
1815
{
1816
    TCGv r_asi, r_size, r_sign;
1817

    
1818
    r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1819
    r_size = tcg_const_i32(8);
1820
    r_sign = tcg_const_i32(0);
1821
    tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1822
    tcg_temp_free(r_sign);
1823
    tcg_temp_free(r_size);
1824
    tcg_temp_free(r_asi);
1825
    tcg_gen_trunc_i64_tl(lo, cpu_tmp64);
1826
    tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
1827
    tcg_gen_trunc_i64_tl(hi, cpu_tmp64);
1828
}
1829

    
1830
static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
1831
{
1832
    TCGv r_temp, r_asi, r_size;
1833

    
1834
    r_temp = tcg_temp_new(TCG_TYPE_TL);
1835
    gen_movl_reg_TN(rd + 1, r_temp);
1836
    tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi, r_temp);
1837
    tcg_temp_free(r_temp);
1838
    r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1839
    r_size = tcg_const_i32(8);
1840
    tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size);
1841
    tcg_temp_free(r_size);
1842
    tcg_temp_free(r_asi);
1843
}
1844
#endif
1845

    
1846
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
1847
static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn)
1848
{
1849
    TCGv r_val, r_asi, r_size;
1850

    
1851
    gen_ld_asi(dst, addr, insn, 1, 0);
1852

    
1853
    r_val = tcg_const_i64(0xffULL);
1854
    r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1855
    r_size = tcg_const_i32(1);
1856
    tcg_gen_helper_0_4(helper_st_asi, addr, r_val, r_asi, r_size);
1857
    tcg_temp_free(r_size);
1858
    tcg_temp_free(r_asi);
1859
    tcg_temp_free(r_val);
1860
}
1861
#endif
1862

    
1863
static inline TCGv get_src1(unsigned int insn, TCGv def)
1864
{
1865
    TCGv r_rs1 = def;
1866
    unsigned int rs1;
1867

    
1868
    rs1 = GET_FIELD(insn, 13, 17);
1869
    if (rs1 == 0)
1870
        r_rs1 = tcg_const_tl(0); // XXX how to free?
1871
    else if (rs1 < 8)
1872
        r_rs1 = cpu_gregs[rs1];
1873
    else
1874
        tcg_gen_ld_tl(def, cpu_regwptr, (rs1 - 8) * sizeof(target_ulong));
1875
    return r_rs1;
1876
}
1877

    
1878
static inline TCGv get_src2(unsigned int insn, TCGv def)
1879
{
1880
    TCGv r_rs2 = def;
1881
    unsigned int rs2;
1882

    
1883
    if (IS_IMM) { /* immediate */
1884
        rs2 = GET_FIELDs(insn, 19, 31);
1885
        r_rs2 = tcg_const_tl((int)rs2); // XXX how to free?
1886
    } else { /* register */
1887
        rs2 = GET_FIELD(insn, 27, 31);
1888
        if (rs2 == 0)
1889
            r_rs2 = tcg_const_tl(0); // XXX how to free?
1890
        else if (rs2 < 8)
1891
            r_rs2 = cpu_gregs[rs2];
1892
        else
1893
            tcg_gen_ld_tl(def, cpu_regwptr, (rs2 - 8) * sizeof(target_ulong));
1894
    }
1895
    return r_rs2;
1896
}
1897

    
1898
#define CHECK_IU_FEATURE(dc, FEATURE)                      \
1899
    if (!((dc)->features & CPU_FEATURE_ ## FEATURE))       \
1900
        goto illegal_insn;
1901
#define CHECK_FPU_FEATURE(dc, FEATURE)                     \
1902
    if (!((dc)->features & CPU_FEATURE_ ## FEATURE))       \
1903
        goto nfpu_insn;
1904

    
1905
/* before an instruction, dc->pc must be static */
1906
static void disas_sparc_insn(DisasContext * dc)
1907
{
1908
    unsigned int insn, opc, rs1, rs2, rd;
1909

    
1910
    if (unlikely(loglevel & CPU_LOG_TB_OP))
1911
        tcg_gen_debug_insn_start(dc->pc);
1912
    insn = ldl_code(dc->pc);
1913
    opc = GET_FIELD(insn, 0, 1);
1914

    
1915
    rd = GET_FIELD(insn, 2, 6);
1916

    
1917
    cpu_src1 = tcg_temp_new(TCG_TYPE_TL); // const
1918
    cpu_src2 = tcg_temp_new(TCG_TYPE_TL); // const
1919

    
1920
    switch (opc) {
1921
    case 0:                     /* branches/sethi */
1922
        {
1923
            unsigned int xop = GET_FIELD(insn, 7, 9);
1924
            int32_t target;
1925
            switch (xop) {
1926
#ifdef TARGET_SPARC64
1927
            case 0x1:           /* V9 BPcc */
1928
                {
1929
                    int cc;
1930

    
1931
                    target = GET_FIELD_SP(insn, 0, 18);
1932
                    target = sign_extend(target, 18);
1933
                    target <<= 2;
1934
                    cc = GET_FIELD_SP(insn, 20, 21);
1935
                    if (cc == 0)
1936
                        do_branch(dc, target, insn, 0, cpu_cond);
1937
                    else if (cc == 2)
1938
                        do_branch(dc, target, insn, 1, cpu_cond);
1939
                    else
1940
                        goto illegal_insn;
1941
                    goto jmp_insn;
1942
                }
1943
            case 0x3:           /* V9 BPr */
1944
                {
1945
                    target = GET_FIELD_SP(insn, 0, 13) |
1946
                        (GET_FIELD_SP(insn, 20, 21) << 14);
1947
                    target = sign_extend(target, 16);
1948
                    target <<= 2;
1949
                    cpu_src1 = get_src1(insn, cpu_src1);
1950
                    do_branch_reg(dc, target, insn, cpu_cond, cpu_src1);
1951
                    goto jmp_insn;
1952
                }
1953
            case 0x5:           /* V9 FBPcc */
1954
                {
1955
                    int cc = GET_FIELD_SP(insn, 20, 21);
1956
                    if (gen_trap_ifnofpu(dc, cpu_cond))
1957
                        goto jmp_insn;
1958
                    target = GET_FIELD_SP(insn, 0, 18);
1959
                    target = sign_extend(target, 19);
1960
                    target <<= 2;
1961
                    do_fbranch(dc, target, insn, cc, cpu_cond);
1962
                    goto jmp_insn;
1963
                }
1964
#else
1965
            case 0x7:           /* CBN+x */
1966
                {
1967
                    goto ncp_insn;
1968
                }
1969
#endif
1970
            case 0x2:           /* BN+x */
1971
                {
1972
                    target = GET_FIELD(insn, 10, 31);
1973
                    target = sign_extend(target, 22);
1974
                    target <<= 2;
1975
                    do_branch(dc, target, insn, 0, cpu_cond);
1976
                    goto jmp_insn;
1977
                }
1978
            case 0x6:           /* FBN+x */
1979
                {
1980
                    if (gen_trap_ifnofpu(dc, cpu_cond))
1981
                        goto jmp_insn;
1982
                    target = GET_FIELD(insn, 10, 31);
1983
                    target = sign_extend(target, 22);
1984
                    target <<= 2;
1985
                    do_fbranch(dc, target, insn, 0, cpu_cond);
1986
                    goto jmp_insn;
1987
                }
1988
            case 0x4:           /* SETHI */
1989
                if (rd) { // nop
1990
                    uint32_t value = GET_FIELD(insn, 10, 31);
1991
                    TCGv r_const;
1992

    
1993
                    r_const = tcg_const_tl(value << 10);
1994
                    gen_movl_TN_reg(rd, r_const);
1995
                    tcg_temp_free(r_const);
1996
                }
1997
                break;
1998
            case 0x0:           /* UNIMPL */
1999
            default:
2000
                goto illegal_insn;
2001
            }
2002
            break;
2003
        }
2004
        break;
2005
    case 1:
2006
        /*CALL*/ {
2007
            target_long target = GET_FIELDs(insn, 2, 31) << 2;
2008
            TCGv r_const;
2009

    
2010
            r_const = tcg_const_tl(dc->pc);
2011
            gen_movl_TN_reg(15, r_const);
2012
            tcg_temp_free(r_const);
2013
            target += dc->pc;
2014
            gen_mov_pc_npc(dc, cpu_cond);
2015
            dc->npc = target;
2016
        }
2017
        goto jmp_insn;
2018
    case 2:                     /* FPU & Logical Operations */
2019
        {
2020
            unsigned int xop = GET_FIELD(insn, 7, 12);
2021
            if (xop == 0x3a) {  /* generate trap */
2022
                int cond;
2023

    
2024
                cpu_src1 = get_src1(insn, cpu_src1);
2025
                if (IS_IMM) {
2026
                    rs2 = GET_FIELD(insn, 25, 31);
2027
                    tcg_gen_addi_tl(cpu_dst, cpu_src1, rs2);
2028
                } else {
2029
                    rs2 = GET_FIELD(insn, 27, 31);
2030
                    if (rs2 != 0) {
2031
                        gen_movl_reg_TN(rs2, cpu_src2);
2032
                        tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
2033
                    } else
2034
                        tcg_gen_mov_tl(cpu_dst, cpu_src1);
2035
                }
2036
                cond = GET_FIELD(insn, 3, 6);
2037
                if (cond == 0x8) {
2038
                    save_state(dc, cpu_cond);
2039
                    tcg_gen_helper_0_1(helper_trap, cpu_dst);
2040
                } else if (cond != 0) {
2041
                    TCGv r_cond = tcg_temp_new(TCG_TYPE_TL);
2042
#ifdef TARGET_SPARC64
2043
                    /* V9 icc/xcc */
2044
                    int cc = GET_FIELD_SP(insn, 11, 12);
2045

    
2046
                    save_state(dc, cpu_cond);
2047
                    if (cc == 0)
2048
                        gen_cond(r_cond, 0, cond);
2049
                    else if (cc == 2)
2050
                        gen_cond(r_cond, 1, cond);
2051
                    else
2052
                        goto illegal_insn;
2053
#else
2054
                    save_state(dc, cpu_cond);
2055
                    gen_cond(r_cond, 0, cond);
2056
#endif
2057
                    tcg_gen_helper_0_2(helper_trapcc, cpu_dst, r_cond);
2058
                    tcg_temp_free(r_cond);
2059
                }
2060
                gen_op_next_insn();
2061
                tcg_gen_exit_tb(0);
2062
                dc->is_br = 1;
2063
                goto jmp_insn;
2064
            } else if (xop == 0x28) {
2065
                rs1 = GET_FIELD(insn, 13, 17);
2066
                switch(rs1) {
2067
                case 0: /* rdy */
2068
#ifndef TARGET_SPARC64
2069
                case 0x01 ... 0x0e: /* undefined in the SPARCv8
2070
                                       manual, rdy on the microSPARC
2071
                                       II */
2072
                case 0x0f:          /* stbar in the SPARCv8 manual,
2073
                                       rdy on the microSPARC II */
2074
                case 0x10 ... 0x1f: /* implementation-dependent in the
2075
                                       SPARCv8 manual, rdy on the
2076
                                       microSPARC II */
2077
#endif
2078
                    tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2079
                                  offsetof(CPUSPARCState, y));
2080
                    gen_movl_TN_reg(rd, cpu_tmp0);
2081
                    break;
2082
#ifdef TARGET_SPARC64
2083
                case 0x2: /* V9 rdccr */
2084
                    tcg_gen_helper_1_0(helper_rdccr, cpu_dst);
2085
                    gen_movl_TN_reg(rd, cpu_dst);
2086
                    break;
2087
                case 0x3: /* V9 rdasi */
2088
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2089
                                   offsetof(CPUSPARCState, asi));
2090
                    tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2091
                    gen_movl_TN_reg(rd, cpu_dst);
2092
                    break;
2093
                case 0x4: /* V9 rdtick */
2094
                    {
2095
                        TCGv r_tickptr;
2096

    
2097
                        r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2098
                        tcg_gen_ld_ptr(r_tickptr, cpu_env,
2099
                                       offsetof(CPUState, tick));
2100
                        tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
2101
                                           r_tickptr);
2102
                        tcg_temp_free(r_tickptr);
2103
                        gen_movl_TN_reg(rd, cpu_dst);
2104
                    }
2105
                    break;
2106
                case 0x5: /* V9 rdpc */
2107
                    {
2108
                        TCGv r_const;
2109

    
2110
                        r_const = tcg_const_tl(dc->pc);
2111
                        gen_movl_TN_reg(rd, r_const);
2112
                        tcg_temp_free(r_const);
2113
                    }
2114
                    break;
2115
                case 0x6: /* V9 rdfprs */
2116
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2117
                                   offsetof(CPUSPARCState, fprs));
2118
                    tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2119
                    gen_movl_TN_reg(rd, cpu_dst);
2120
                    break;
2121
                case 0xf: /* V9 membar */
2122
                    break; /* no effect */
2123
                case 0x13: /* Graphics Status */
2124
                    if (gen_trap_ifnofpu(dc, cpu_cond))
2125
                        goto jmp_insn;
2126
                    tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2127
                                  offsetof(CPUSPARCState, gsr));
2128
                    gen_movl_TN_reg(rd, cpu_tmp0);
2129
                    break;
2130
                case 0x17: /* Tick compare */
2131
                    tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2132
                                  offsetof(CPUSPARCState, tick_cmpr));
2133
                    gen_movl_TN_reg(rd, cpu_tmp0);
2134
                    break;
2135
                case 0x18: /* System tick */
2136
                    {
2137
                        TCGv r_tickptr;
2138

    
2139
                        r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2140
                        tcg_gen_ld_ptr(r_tickptr, cpu_env,
2141
                                       offsetof(CPUState, stick));
2142
                        tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
2143
                                           r_tickptr);
2144
                        tcg_temp_free(r_tickptr);
2145
                        gen_movl_TN_reg(rd, cpu_dst);
2146
                    }
2147
                    break;
2148
                case 0x19: /* System tick compare */
2149
                    tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2150
                                  offsetof(CPUSPARCState, stick_cmpr));
2151
                    gen_movl_TN_reg(rd, cpu_tmp0);
2152
                    break;
2153
                case 0x10: /* Performance Control */
2154
                case 0x11: /* Performance Instrumentation Counter */
2155
                case 0x12: /* Dispatch Control */
2156
                case 0x14: /* Softint set, WO */
2157
                case 0x15: /* Softint clear, WO */
2158
                case 0x16: /* Softint write */
2159
#endif
2160
                default:
2161
                    goto illegal_insn;
2162
                }
2163
#if !defined(CONFIG_USER_ONLY)
2164
            } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
2165
#ifndef TARGET_SPARC64
2166
                if (!supervisor(dc))
2167
                    goto priv_insn;
2168
                tcg_gen_helper_1_0(helper_rdpsr, cpu_dst);
2169
#else
2170
                if (!hypervisor(dc))
2171
                    goto priv_insn;
2172
                rs1 = GET_FIELD(insn, 13, 17);
2173
                switch (rs1) {
2174
                case 0: // hpstate
2175
                    // gen_op_rdhpstate();
2176
                    break;
2177
                case 1: // htstate
2178
                    // gen_op_rdhtstate();
2179
                    break;
2180
                case 3: // hintp
2181
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2182
                                   offsetof(CPUSPARCState, hintp));
2183
                    tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2184
                    break;
2185
                case 5: // htba
2186
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2187
                                   offsetof(CPUSPARCState, htba));
2188
                    tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2189
                    break;
2190
                case 6: // hver
2191
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2192
                                   offsetof(CPUSPARCState, hver));
2193
                    tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2194
                    break;
2195
                case 31: // hstick_cmpr
2196
                    tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
2197
                    tcg_gen_st_i32(cpu_tmp32, cpu_env,
2198
                                   offsetof(CPUSPARCState, hstick_cmpr));
2199
                    break;
2200
                default:
2201
                    goto illegal_insn;
2202
                }
2203
#endif
2204
                gen_movl_TN_reg(rd, cpu_dst);
2205
                break;
2206
            } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
2207
                if (!supervisor(dc))
2208
                    goto priv_insn;
2209
#ifdef TARGET_SPARC64
2210
                rs1 = GET_FIELD(insn, 13, 17);
2211
                switch (rs1) {
2212
                case 0: // tpc
2213
                    {
2214
                        TCGv r_tsptr;
2215

    
2216
                        r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2217
                        tcg_gen_ld_ptr(r_tsptr, cpu_env,
2218
                                       offsetof(CPUState, tsptr));
2219
                        tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
2220
                                      offsetof(trap_state, tpc));
2221
                        tcg_temp_free(r_tsptr);
2222
                    }
2223
                    break;
2224
                case 1: // tnpc
2225
                    {
2226
                        TCGv r_tsptr;
2227

    
2228
                        r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2229
                        tcg_gen_ld_ptr(r_tsptr, cpu_env,
2230
                                       offsetof(CPUState, tsptr));
2231
                        tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
2232
                                      offsetof(trap_state, tnpc));
2233
                        tcg_temp_free(r_tsptr);
2234
                    }
2235
                    break;
2236
                case 2: // tstate
2237
                    {
2238
                        TCGv r_tsptr;
2239

    
2240
                        r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2241
                        tcg_gen_ld_ptr(r_tsptr, cpu_env,
2242
                                       offsetof(CPUState, tsptr));
2243
                        tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
2244
                                      offsetof(trap_state, tstate));
2245
                        tcg_temp_free(r_tsptr);
2246
                    }
2247
                    break;
2248
                case 3: // tt
2249
                    {
2250
                        TCGv r_tsptr;
2251

    
2252
                        r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2253
                        tcg_gen_ld_ptr(r_tsptr, cpu_env,
2254
                                       offsetof(CPUState, tsptr));
2255
                        tcg_gen_ld_i32(cpu_tmp0, r_tsptr,
2256
                                       offsetof(trap_state, tt));
2257
                        tcg_temp_free(r_tsptr);
2258
                    }
2259
                    break;
2260
                case 4: // tick
2261
                    {
2262
                        TCGv r_tickptr;
2263

    
2264
                        r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2265
                        tcg_gen_ld_ptr(r_tickptr, cpu_env,
2266
                                       offsetof(CPUState, tick));
2267
                        tcg_gen_helper_1_1(helper_tick_get_count, cpu_tmp0,
2268
                                           r_tickptr);
2269
                        gen_movl_TN_reg(rd, cpu_tmp0);
2270
                        tcg_temp_free(r_tickptr);
2271
                    }
2272
                    break;
2273
                case 5: // tba
2274
                    tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2275
                                  offsetof(CPUSPARCState, tbr));
2276
                    break;
2277
                case 6: // pstate
2278
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2279
                                   offsetof(CPUSPARCState, pstate));
2280
                    tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2281
                    break;
2282
                case 7: // tl
2283
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2284
                                   offsetof(CPUSPARCState, tl));
2285
                    tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2286
                    break;
2287
                case 8: // pil
2288
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2289
                                   offsetof(CPUSPARCState, psrpil));
2290
                    tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2291
                    break;
2292
                case 9: // cwp
2293
                    tcg_gen_helper_1_0(helper_rdcwp, cpu_tmp0);
2294
                    break;
2295
                case 10: // cansave
2296
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2297
                                   offsetof(CPUSPARCState, cansave));
2298
                    tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2299
                    break;
2300
                case 11: // canrestore
2301
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2302
                                   offsetof(CPUSPARCState, canrestore));
2303
                    tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2304
                    break;
2305
                case 12: // cleanwin
2306
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2307
                                   offsetof(CPUSPARCState, cleanwin));
2308
                    tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2309
                    break;
2310
                case 13: // otherwin
2311
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2312
                                   offsetof(CPUSPARCState, otherwin));
2313
                    tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2314
                    break;
2315
                case 14: // wstate
2316
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2317
                                   offsetof(CPUSPARCState, wstate));
2318
                    tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2319
                    break;
2320
                case 16: // UA2005 gl
2321
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2322
                                   offsetof(CPUSPARCState, gl));
2323
                    tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2324
                    break;
2325
                case 26: // UA2005 strand status
2326
                    if (!hypervisor(dc))
2327
                        goto priv_insn;
2328
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2329
                                   offsetof(CPUSPARCState, ssr));
2330
                    tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2331
                    break;
2332
                case 31: // ver
2333
                    tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2334
                                  offsetof(CPUSPARCState, version));
2335
                    break;
2336
                case 15: // fq
2337
                default:
2338
                    goto illegal_insn;
2339
                }
2340
#else
2341
                tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2342
                               offsetof(CPUSPARCState, wim));
2343
                tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2344
#endif
2345
                gen_movl_TN_reg(rd, cpu_tmp0);
2346
                break;
2347
            } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
2348
#ifdef TARGET_SPARC64
2349
                tcg_gen_helper_0_0(helper_flushw);
2350
#else
2351
                if (!supervisor(dc))
2352
                    goto priv_insn;
2353
                tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, tbr));
2354
                gen_movl_TN_reg(rd, cpu_tmp0);
2355
#endif
2356
                break;
2357
#endif
2358
            } else if (xop == 0x34) {   /* FPU Operations */
2359
                if (gen_trap_ifnofpu(dc, cpu_cond))
2360
                    goto jmp_insn;
2361
                gen_op_clear_ieee_excp_and_FTT();
2362
                rs1 = GET_FIELD(insn, 13, 17);
2363
                rs2 = GET_FIELD(insn, 27, 31);
2364
                xop = GET_FIELD(insn, 18, 26);
2365
                switch (xop) {
2366
                    case 0x1: /* fmovs */
2367
                        gen_op_load_fpr_FT0(rs2);
2368
                        gen_op_store_FT0_fpr(rd);
2369
                        break;
2370
                    case 0x5: /* fnegs */
2371
                        gen_op_load_fpr_FT1(rs2);
2372
                        tcg_gen_helper_0_0(helper_fnegs);
2373
                        gen_op_store_FT0_fpr(rd);
2374
                        break;
2375
                    case 0x9: /* fabss */
2376
                        gen_op_load_fpr_FT1(rs2);
2377
                        tcg_gen_helper_0_0(helper_fabss);
2378
                        gen_op_store_FT0_fpr(rd);
2379
                        break;
2380
                    case 0x29: /* fsqrts */
2381
                        CHECK_FPU_FEATURE(dc, FSQRT);
2382
                        gen_op_load_fpr_FT1(rs2);
2383
                        gen_clear_float_exceptions();
2384
                        tcg_gen_helper_0_0(helper_fsqrts);
2385
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2386
                        gen_op_store_FT0_fpr(rd);
2387
                        break;
2388
                    case 0x2a: /* fsqrtd */
2389
                        CHECK_FPU_FEATURE(dc, FSQRT);
2390
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2391
                        gen_clear_float_exceptions();
2392
                        tcg_gen_helper_0_0(helper_fsqrtd);
2393
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2394
                        gen_op_store_DT0_fpr(DFPREG(rd));
2395
                        break;
2396
                    case 0x2b: /* fsqrtq */
2397
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2398
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2399
                        gen_clear_float_exceptions();
2400
                        tcg_gen_helper_0_0(helper_fsqrtq);
2401
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2402
                        gen_op_store_QT0_fpr(QFPREG(rd));
2403
                        break;
2404
                    case 0x41:
2405
                        gen_op_load_fpr_FT0(rs1);
2406
                        gen_op_load_fpr_FT1(rs2);
2407
                        gen_clear_float_exceptions();
2408
                        tcg_gen_helper_0_0(helper_fadds);
2409
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2410
                        gen_op_store_FT0_fpr(rd);
2411
                        break;
2412
                    case 0x42:
2413
                        gen_op_load_fpr_DT0(DFPREG(rs1));
2414
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2415
                        gen_clear_float_exceptions();
2416
                        tcg_gen_helper_0_0(helper_faddd);
2417
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2418
                        gen_op_store_DT0_fpr(DFPREG(rd));
2419
                        break;
2420
                    case 0x43: /* faddq */
2421
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2422
                        gen_op_load_fpr_QT0(QFPREG(rs1));
2423
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2424
                        gen_clear_float_exceptions();
2425
                        tcg_gen_helper_0_0(helper_faddq);
2426
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2427
                        gen_op_store_QT0_fpr(QFPREG(rd));
2428
                        break;
2429
                    case 0x45:
2430
                        gen_op_load_fpr_FT0(rs1);
2431
                        gen_op_load_fpr_FT1(rs2);
2432
                        gen_clear_float_exceptions();
2433
                        tcg_gen_helper_0_0(helper_fsubs);
2434
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2435
                        gen_op_store_FT0_fpr(rd);
2436
                        break;
2437
                    case 0x46:
2438
                        gen_op_load_fpr_DT0(DFPREG(rs1));
2439
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2440
                        gen_clear_float_exceptions();
2441
                        tcg_gen_helper_0_0(helper_fsubd);
2442
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2443
                        gen_op_store_DT0_fpr(DFPREG(rd));
2444
                        break;
2445
                    case 0x47: /* fsubq */
2446
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2447
                        gen_op_load_fpr_QT0(QFPREG(rs1));
2448
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2449
                        gen_clear_float_exceptions();
2450
                        tcg_gen_helper_0_0(helper_fsubq);
2451
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2452
                        gen_op_store_QT0_fpr(QFPREG(rd));
2453
                        break;
2454
                    case 0x49: /* fmuls */
2455
                        CHECK_FPU_FEATURE(dc, FMUL);
2456
                        gen_op_load_fpr_FT0(rs1);
2457
                        gen_op_load_fpr_FT1(rs2);
2458
                        gen_clear_float_exceptions();
2459
                        tcg_gen_helper_0_0(helper_fmuls);
2460
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2461
                        gen_op_store_FT0_fpr(rd);
2462
                        break;
2463
                    case 0x4a: /* fmuld */
2464
                        CHECK_FPU_FEATURE(dc, FMUL);
2465
                        gen_op_load_fpr_DT0(DFPREG(rs1));
2466
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2467
                        gen_clear_float_exceptions();
2468
                        tcg_gen_helper_0_0(helper_fmuld);
2469
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2470
                        gen_op_store_DT0_fpr(DFPREG(rd));
2471
                        break;
2472
                    case 0x4b: /* fmulq */
2473
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2474
                        CHECK_FPU_FEATURE(dc, FMUL);
2475
                        gen_op_load_fpr_QT0(QFPREG(rs1));
2476
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2477
                        gen_clear_float_exceptions();
2478
                        tcg_gen_helper_0_0(helper_fmulq);
2479
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2480
                        gen_op_store_QT0_fpr(QFPREG(rd));
2481
                        break;
2482
                    case 0x4d:
2483
                        gen_op_load_fpr_FT0(rs1);
2484
                        gen_op_load_fpr_FT1(rs2);
2485
                        gen_clear_float_exceptions();
2486
                        tcg_gen_helper_0_0(helper_fdivs);
2487
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2488
                        gen_op_store_FT0_fpr(rd);
2489
                        break;
2490
                    case 0x4e:
2491
                        gen_op_load_fpr_DT0(DFPREG(rs1));
2492
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2493
                        gen_clear_float_exceptions();
2494
                        tcg_gen_helper_0_0(helper_fdivd);
2495
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2496
                        gen_op_store_DT0_fpr(DFPREG(rd));
2497
                        break;
2498
                    case 0x4f: /* fdivq */
2499
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2500
                        gen_op_load_fpr_QT0(QFPREG(rs1));
2501
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2502
                        gen_clear_float_exceptions();
2503
                        tcg_gen_helper_0_0(helper_fdivq);
2504
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2505
                        gen_op_store_QT0_fpr(QFPREG(rd));
2506
                        break;
2507
                    case 0x69:
2508
                        CHECK_FPU_FEATURE(dc, FSMULD);
2509
                        gen_op_load_fpr_FT0(rs1);
2510
                        gen_op_load_fpr_FT1(rs2);
2511
                        gen_clear_float_exceptions();
2512
                        tcg_gen_helper_0_0(helper_fsmuld);
2513
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2514
                        gen_op_store_DT0_fpr(DFPREG(rd));
2515
                        break;
2516
                    case 0x6e: /* fdmulq */
2517
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2518
                        gen_op_load_fpr_DT0(DFPREG(rs1));
2519
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2520
                        gen_clear_float_exceptions();
2521
                        tcg_gen_helper_0_0(helper_fdmulq);
2522
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2523
                        gen_op_store_QT0_fpr(QFPREG(rd));
2524
                        break;
2525
                    case 0xc4:
2526
                        gen_op_load_fpr_FT1(rs2);
2527
                        gen_clear_float_exceptions();
2528
                        tcg_gen_helper_0_0(helper_fitos);
2529
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2530
                        gen_op_store_FT0_fpr(rd);
2531
                        break;
2532
                    case 0xc6:
2533
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2534
                        gen_clear_float_exceptions();
2535
                        tcg_gen_helper_0_0(helper_fdtos);
2536
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2537
                        gen_op_store_FT0_fpr(rd);
2538
                        break;
2539
                    case 0xc7: /* fqtos */
2540
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2541
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2542
                        gen_clear_float_exceptions();
2543
                        tcg_gen_helper_0_0(helper_fqtos);
2544
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2545
                        gen_op_store_FT0_fpr(rd);
2546
                        break;
2547
                    case 0xc8:
2548
                        gen_op_load_fpr_FT1(rs2);
2549
                        tcg_gen_helper_0_0(helper_fitod);
2550
                        gen_op_store_DT0_fpr(DFPREG(rd));
2551
                        break;
2552
                    case 0xc9:
2553
                        gen_op_load_fpr_FT1(rs2);
2554
                        tcg_gen_helper_0_0(helper_fstod);
2555
                        gen_op_store_DT0_fpr(DFPREG(rd));
2556
                        break;
2557
                    case 0xcb: /* fqtod */
2558
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2559
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2560
                        gen_clear_float_exceptions();
2561
                        tcg_gen_helper_0_0(helper_fqtod);
2562
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2563
                        gen_op_store_DT0_fpr(DFPREG(rd));
2564
                        break;
2565
                    case 0xcc: /* fitoq */
2566
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2567
                        gen_op_load_fpr_FT1(rs2);
2568
                        tcg_gen_helper_0_0(helper_fitoq);
2569
                        gen_op_store_QT0_fpr(QFPREG(rd));
2570
                        break;
2571
                    case 0xcd: /* fstoq */
2572
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2573
                        gen_op_load_fpr_FT1(rs2);
2574
                        tcg_gen_helper_0_0(helper_fstoq);
2575
                        gen_op_store_QT0_fpr(QFPREG(rd));
2576
                        break;
2577
                    case 0xce: /* fdtoq */
2578
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2579
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2580
                        tcg_gen_helper_0_0(helper_fdtoq);
2581
                        gen_op_store_QT0_fpr(QFPREG(rd));
2582
                        break;
2583
                    case 0xd1:
2584
                        gen_op_load_fpr_FT1(rs2);
2585
                        gen_clear_float_exceptions();
2586
                        tcg_gen_helper_0_0(helper_fstoi);
2587
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2588
                        gen_op_store_FT0_fpr(rd);
2589
                        break;
2590
                    case 0xd2:
2591
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2592
                        gen_clear_float_exceptions();
2593
                        tcg_gen_helper_0_0(helper_fdtoi);
2594
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2595
                        gen_op_store_FT0_fpr(rd);
2596
                        break;
2597
                    case 0xd3: /* fqtoi */
2598
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2599
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2600
                        gen_clear_float_exceptions();
2601
                        tcg_gen_helper_0_0(helper_fqtoi);
2602
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2603
                        gen_op_store_FT0_fpr(rd);
2604
                        break;
2605
#ifdef TARGET_SPARC64
2606
                    case 0x2: /* V9 fmovd */
2607
                        gen_op_load_fpr_DT0(DFPREG(rs2));
2608
                        gen_op_store_DT0_fpr(DFPREG(rd));
2609
                        break;
2610
                    case 0x3: /* V9 fmovq */
2611
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2612
                        gen_op_load_fpr_QT0(QFPREG(rs2));
2613
                        gen_op_store_QT0_fpr(QFPREG(rd));
2614
                        break;
2615
                    case 0x6: /* V9 fnegd */
2616
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2617
                        tcg_gen_helper_0_0(helper_fnegd);
2618
                        gen_op_store_DT0_fpr(DFPREG(rd));
2619
                        break;
2620
                    case 0x7: /* V9 fnegq */
2621
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2622
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2623
                        tcg_gen_helper_0_0(helper_fnegq);
2624
                        gen_op_store_QT0_fpr(QFPREG(rd));
2625
                        break;
2626
                    case 0xa: /* V9 fabsd */
2627
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2628
                        tcg_gen_helper_0_0(helper_fabsd);
2629
                        gen_op_store_DT0_fpr(DFPREG(rd));
2630
                        break;
2631
                    case 0xb: /* V9 fabsq */
2632
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2633
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2634
                        tcg_gen_helper_0_0(helper_fabsq);
2635
                        gen_op_store_QT0_fpr(QFPREG(rd));
2636
                        break;
2637
                    case 0x81: /* V9 fstox */
2638
                        gen_op_load_fpr_FT1(rs2);
2639
                        gen_clear_float_exceptions();
2640
                        tcg_gen_helper_0_0(helper_fstox);
2641
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2642
                        gen_op_store_DT0_fpr(DFPREG(rd));
2643
                        break;
2644
                    case 0x82: /* V9 fdtox */
2645
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2646
                        gen_clear_float_exceptions();
2647
                        tcg_gen_helper_0_0(helper_fdtox);
2648
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2649
                        gen_op_store_DT0_fpr(DFPREG(rd));
2650
                        break;
2651
                    case 0x83: /* V9 fqtox */
2652
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2653
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2654
                        gen_clear_float_exceptions();
2655
                        tcg_gen_helper_0_0(helper_fqtox);
2656
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2657
                        gen_op_store_DT0_fpr(DFPREG(rd));
2658
                        break;
2659
                    case 0x84: /* V9 fxtos */
2660
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2661
                        gen_clear_float_exceptions();
2662
                        tcg_gen_helper_0_0(helper_fxtos);
2663
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2664
                        gen_op_store_FT0_fpr(rd);
2665
                        break;
2666
                    case 0x88: /* V9 fxtod */
2667
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2668
                        gen_clear_float_exceptions();
2669
                        tcg_gen_helper_0_0(helper_fxtod);
2670
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2671
                        gen_op_store_DT0_fpr(DFPREG(rd));
2672
                        break;
2673
                    case 0x8c: /* V9 fxtoq */
2674
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2675
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2676
                        gen_clear_float_exceptions();
2677
                        tcg_gen_helper_0_0(helper_fxtoq);
2678
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2679
                        gen_op_store_QT0_fpr(QFPREG(rd));
2680
                        break;
2681
#endif
2682
                    default:
2683
                        goto illegal_insn;
2684
                }
2685
            } else if (xop == 0x35) {   /* FPU Operations */
2686
#ifdef TARGET_SPARC64
2687
                int cond;
2688
#endif
2689
                if (gen_trap_ifnofpu(dc, cpu_cond))
2690
                    goto jmp_insn;
2691
                gen_op_clear_ieee_excp_and_FTT();
2692
                rs1 = GET_FIELD(insn, 13, 17);
2693
                rs2 = GET_FIELD(insn, 27, 31);
2694
                xop = GET_FIELD(insn, 18, 26);
2695
#ifdef TARGET_SPARC64
2696
                if ((xop & 0x11f) == 0x005) { // V9 fmovsr
2697
                    int l1;
2698

    
2699
                    l1 = gen_new_label();
2700
                    cond = GET_FIELD_SP(insn, 14, 17);
2701
                    cpu_src1 = get_src1(insn, cpu_src1);
2702
                    tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2703
                                       0, l1);
2704
                    gen_op_load_fpr_FT0(rs2);
2705
                    gen_op_store_FT0_fpr(rd);
2706
                    gen_set_label(l1);
2707
                    break;
2708
                } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
2709
                    int l1;
2710

    
2711
                    l1 = gen_new_label();
2712
                    cond = GET_FIELD_SP(insn, 14, 17);
2713
                    cpu_src1 = get_src1(insn, cpu_src1);
2714
                    tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2715
                                       0, l1);
2716
                    gen_op_load_fpr_DT0(DFPREG(rs2));
2717
                    gen_op_store_DT0_fpr(DFPREG(rd));
2718
                    gen_set_label(l1);
2719
                    break;
2720
                } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
2721
                    int l1;
2722

    
2723
                    CHECK_FPU_FEATURE(dc, FLOAT128);
2724
                    l1 = gen_new_label();
2725
                    cond = GET_FIELD_SP(insn, 14, 17);
2726
                    cpu_src1 = get_src1(insn, cpu_src1);
2727
                    tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2728
                                       0, l1);
2729
                    gen_op_load_fpr_QT0(QFPREG(rs2));
2730
                    gen_op_store_QT0_fpr(QFPREG(rd));
2731
                    gen_set_label(l1);
2732
                    break;
2733
                }
2734
#endif
2735
                switch (xop) {
2736
#ifdef TARGET_SPARC64
2737
#define FMOVCC(size_FDQ, fcc)                                           \
2738
                    {                                                   \
2739
                        TCGv r_cond;                                    \
2740
                        int l1;                                         \
2741
                                                                        \
2742
                        l1 = gen_new_label();                           \
2743
                        r_cond = tcg_temp_new(TCG_TYPE_TL);             \
2744
                        cond = GET_FIELD_SP(insn, 14, 17);              \
2745
                        gen_fcond(r_cond, fcc, cond);                   \
2746
                        tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond,         \
2747
                                           0, l1);                      \
2748
                        glue(glue(gen_op_load_fpr_, size_FDQ), T0)      \
2749
                            (glue(size_FDQ, FPREG(rs2)));               \
2750
                        glue(glue(gen_op_store_, size_FDQ), T0_fpr)     \
2751
                            (glue(size_FDQ, FPREG(rd)));                \
2752
                        gen_set_label(l1);                              \
2753
                        tcg_temp_free(r_cond);                          \
2754
                    }
2755
                    case 0x001: /* V9 fmovscc %fcc0 */
2756
                        FMOVCC(F, 0);
2757
                        break;
2758
                    case 0x002: /* V9 fmovdcc %fcc0 */
2759
                        FMOVCC(D, 0);
2760
                        break;
2761
                    case 0x003: /* V9 fmovqcc %fcc0 */
2762
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2763
                        FMOVCC(Q, 0);
2764
                        break;
2765
                    case 0x041: /* V9 fmovscc %fcc1 */
2766
                        FMOVCC(F, 1);
2767
                        break;
2768
                    case 0x042: /* V9 fmovdcc %fcc1 */
2769
                        FMOVCC(D, 1);
2770
                        break;
2771
                    case 0x043: /* V9 fmovqcc %fcc1 */
2772
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2773
                        FMOVCC(Q, 1);
2774
                        break;
2775
                    case 0x081: /* V9 fmovscc %fcc2 */
2776
                        FMOVCC(F, 2);
2777
                        break;
2778
                    case 0x082: /* V9 fmovdcc %fcc2 */
2779
                        FMOVCC(D, 2);
2780
                        break;
2781
                    case 0x083: /* V9 fmovqcc %fcc2 */
2782
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2783
                        FMOVCC(Q, 2);
2784
                        break;
2785
                    case 0x0c1: /* V9 fmovscc %fcc3 */
2786
                        FMOVCC(F, 3);
2787
                        break;
2788
                    case 0x0c2: /* V9 fmovdcc %fcc3 */
2789
                        FMOVCC(D, 3);
2790
                        break;
2791
                    case 0x0c3: /* V9 fmovqcc %fcc3 */
2792
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2793
                        FMOVCC(Q, 3);
2794
                        break;
2795
#undef FMOVCC
2796
#define FMOVCC(size_FDQ, icc)                                           \
2797
                    {                                                   \
2798
                        TCGv r_cond;                                    \
2799
                        int l1;                                         \
2800
                                                                        \
2801
                        l1 = gen_new_label();                           \
2802
                        r_cond = tcg_temp_new(TCG_TYPE_TL);             \
2803
                        cond = GET_FIELD_SP(insn, 14, 17);              \
2804
                        gen_cond(r_cond, icc, cond);                    \
2805
                        tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond,         \
2806
                                           0, l1);                      \
2807
                        glue(glue(gen_op_load_fpr_, size_FDQ), T0)      \
2808
                            (glue(size_FDQ, FPREG(rs2)));               \
2809
                        glue(glue(gen_op_store_, size_FDQ), T0_fpr)     \
2810
                            (glue(size_FDQ, FPREG(rd)));                \
2811
                        gen_set_label(l1);                              \
2812
                        tcg_temp_free(r_cond);                          \
2813
                    }
2814

    
2815
                    case 0x101: /* V9 fmovscc %icc */
2816
                        FMOVCC(F, 0);
2817
                        break;
2818
                    case 0x102: /* V9 fmovdcc %icc */
2819
                        FMOVCC(D, 0);
2820
                    case 0x103: /* V9 fmovqcc %icc */
2821
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2822
                        FMOVCC(Q, 0);
2823
                        break;
2824
                    case 0x181: /* V9 fmovscc %xcc */
2825
                        FMOVCC(F, 1);
2826
                        break;
2827
                    case 0x182: /* V9 fmovdcc %xcc */
2828
                        FMOVCC(D, 1);
2829
                        break;
2830
                    case 0x183: /* V9 fmovqcc %xcc */
2831
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2832
                        FMOVCC(Q, 1);
2833
                        break;
2834
#undef FMOVCC
2835
#endif
2836
                    case 0x51: /* fcmps, V9 %fcc */
2837
                        gen_op_load_fpr_FT0(rs1);
2838
                        gen_op_load_fpr_FT1(rs2);
2839
                        gen_op_fcmps(rd & 3);
2840
                        break;
2841
                    case 0x52: /* fcmpd, V9 %fcc */
2842
                        gen_op_load_fpr_DT0(DFPREG(rs1));
2843
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2844
                        gen_op_fcmpd(rd & 3);
2845
                        break;
2846
                    case 0x53: /* fcmpq, V9 %fcc */
2847
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2848
                        gen_op_load_fpr_QT0(QFPREG(rs1));
2849
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2850
                        gen_op_fcmpq(rd & 3);
2851
                        break;
2852
                    case 0x55: /* fcmpes, V9 %fcc */
2853
                        gen_op_load_fpr_FT0(rs1);
2854
                        gen_op_load_fpr_FT1(rs2);
2855
                        gen_op_fcmpes(rd & 3);
2856
                        break;
2857
                    case 0x56: /* fcmped, V9 %fcc */
2858
                        gen_op_load_fpr_DT0(DFPREG(rs1));
2859
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2860
                        gen_op_fcmped(rd & 3);
2861
                        break;
2862
                    case 0x57: /* fcmpeq, V9 %fcc */
2863
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2864
                        gen_op_load_fpr_QT0(QFPREG(rs1));
2865
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2866
                        gen_op_fcmpeq(rd & 3);
2867
                        break;
2868
                    default:
2869
                        goto illegal_insn;
2870
                }
2871
            } else if (xop == 0x2) {
2872
                // clr/mov shortcut
2873

    
2874
                rs1 = GET_FIELD(insn, 13, 17);
2875
                if (rs1 == 0) {
2876
                    // or %g0, x, y -> mov T0, x; mov y, T0
2877
                    if (IS_IMM) {       /* immediate */
2878
                        TCGv r_const;
2879

    
2880
                        rs2 = GET_FIELDs(insn, 19, 31);
2881
                        r_const = tcg_const_tl((int)rs2);
2882
                        gen_movl_TN_reg(rd, r_const);
2883
                        tcg_temp_free(r_const);
2884
                    } else {            /* register */
2885
                        rs2 = GET_FIELD(insn, 27, 31);
2886
                        gen_movl_reg_TN(rs2, cpu_dst);
2887
                        gen_movl_TN_reg(rd, cpu_dst);
2888
                    }
2889
                } else {
2890
                    cpu_src1 = get_src1(insn, cpu_src1);
2891
                    if (IS_IMM) {       /* immediate */
2892
                        rs2 = GET_FIELDs(insn, 19, 31);
2893
                        tcg_gen_ori_tl(cpu_dst, cpu_src1, (int)rs2);
2894
                        gen_movl_TN_reg(rd, cpu_dst);
2895
                    } else {            /* register */
2896
                        // or x, %g0, y -> mov T1, x; mov y, T1
2897
                        rs2 = GET_FIELD(insn, 27, 31);
2898
                        if (rs2 != 0) {
2899
                            gen_movl_reg_TN(rs2, cpu_src2);
2900
                            tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
2901
                            gen_movl_TN_reg(rd, cpu_dst);
2902
                        } else
2903
                            gen_movl_TN_reg(rd, cpu_src1);
2904
                    }
2905
                }
2906
#ifdef TARGET_SPARC64
2907
            } else if (xop == 0x25) { /* sll, V9 sllx */
2908
                cpu_src1 = get_src1(insn, cpu_src1);
2909
                if (IS_IMM) {   /* immediate */
2910
                    rs2 = GET_FIELDs(insn, 20, 31);
2911
                    if (insn & (1 << 12)) {
2912
                        tcg_gen_shli_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2913
                    } else {
2914
                        tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2915
                        tcg_gen_shli_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2916
                    }
2917
                } else {                /* register */
2918
                    rs2 = GET_FIELD(insn, 27, 31);
2919
                    gen_movl_reg_TN(rs2, cpu_src2);
2920
                    if (insn & (1 << 12)) {
2921
                        tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2922
                        tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0);
2923
                    } else {
2924
                        tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2925
                        tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2926
                        tcg_gen_shl_i64(cpu_dst, cpu_dst, cpu_tmp0);
2927
                    }
2928
                }
2929
                gen_movl_TN_reg(rd, cpu_dst);
2930
            } else if (xop == 0x26) { /* srl, V9 srlx */
2931
                cpu_src1 = get_src1(insn, cpu_src1);
2932
                if (IS_IMM) {   /* immediate */
2933
                    rs2 = GET_FIELDs(insn, 20, 31);
2934
                    if (insn & (1 << 12)) {
2935
                        tcg_gen_shri_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2936
                    } else {
2937
                        tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2938
                        tcg_gen_shri_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2939
                    }
2940
                } else {                /* register */
2941
                    rs2 = GET_FIELD(insn, 27, 31);
2942
                    gen_movl_reg_TN(rs2, cpu_src2);
2943
                    if (insn & (1 << 12)) {
2944
                        tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2945
                        tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0);
2946
                    } else {
2947
                        tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2948
                        tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2949
                        tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0);
2950
                    }
2951
                }
2952
                gen_movl_TN_reg(rd, cpu_dst);
2953
            } else if (xop == 0x27) { /* sra, V9 srax */
2954
                cpu_src1 = get_src1(insn, cpu_src1);
2955
                if (IS_IMM) {   /* immediate */
2956
                    rs2 = GET_FIELDs(insn, 20, 31);
2957
                    if (insn & (1 << 12)) {
2958
                        tcg_gen_sari_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2959
                    } else {
2960
                        tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2961
                        tcg_gen_ext_i32_i64(cpu_dst, cpu_dst);
2962
                        tcg_gen_sari_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2963
                    }
2964
                } else {                /* register */
2965
                    rs2 = GET_FIELD(insn, 27, 31);
2966
                    gen_movl_reg_TN(rs2, cpu_src2);
2967
                    if (insn & (1 << 12)) {
2968
                        tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2969
                        tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0);
2970
                    } else {
2971
                        tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2972
                        tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2973
                        tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0);
2974
                    }
2975
                }
2976
                gen_movl_TN_reg(rd, cpu_dst);
2977
#endif
2978
            } else if (xop < 0x36) {
2979
                cpu_src1 = get_src1(insn, cpu_src1);
2980
                cpu_src2 = get_src2(insn, cpu_src2);
2981
                if (xop < 0x20) {
2982
                    switch (xop & ~0x10) {
2983
                    case 0x0:
2984
                        if (xop & 0x10)
2985
                            gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
2986
                        else
2987
                            tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
2988
                        break;
2989
                    case 0x1:
2990
                        tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2);
2991
                        if (xop & 0x10)
2992
                            gen_op_logic_cc(cpu_dst);
2993
                        break;
2994
                    case 0x2:
2995
                        tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
2996
                        if (xop & 0x10)
2997
                            gen_op_logic_cc(cpu_dst);
2998
                        break;
2999
                    case 0x3:
3000
                        tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3001
                        if (xop & 0x10)
3002
                            gen_op_logic_cc(cpu_dst);
3003
                        break;
3004
                    case 0x4:
3005
                        if (xop & 0x10)
3006
                            gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
3007
                        else
3008
                            tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
3009
                        break;
3010
                    case 0x5:
3011
                        tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
3012
                        tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_tmp0);
3013
                        if (xop & 0x10)
3014
                            gen_op_logic_cc(cpu_dst);
3015
                        break;
3016
                    case 0x6:
3017
                        tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
3018
                        tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_tmp0);
3019
                        if (xop & 0x10)
3020
                            gen_op_logic_cc(cpu_dst);
3021
                        break;
3022
                    case 0x7:
3023
                        tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
3024
                        tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_tmp0);
3025
                        if (xop & 0x10)
3026
                            gen_op_logic_cc(cpu_dst);
3027
                        break;
3028
                    case 0x8:
3029
                        if (xop & 0x10)
3030
                            gen_op_addx_cc(cpu_dst, cpu_src1, cpu_src2);
3031
                        else {
3032
                            gen_mov_reg_C(cpu_tmp0, cpu_psr);
3033
                            tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
3034
                            tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_tmp0);
3035
                        }
3036
                        break;
3037
#ifdef TARGET_SPARC64
3038
                    case 0x9: /* V9 mulx */
3039
                        tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2);
3040
                        break;
3041
#endif
3042
                    case 0xa:
3043
                        CHECK_IU_FEATURE(dc, MUL);
3044
                        gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
3045
                        if (xop & 0x10)
3046
                            gen_op_logic_cc(cpu_dst);
3047
                        break;
3048
                    case 0xb:
3049
                        CHECK_IU_FEATURE(dc, MUL);
3050
                        gen_op_smul(cpu_dst, cpu_src1, cpu_src2);
3051
                        if (xop & 0x10)
3052
                            gen_op_logic_cc(cpu_dst);
3053
                        break;
3054
                    case 0xc:
3055
                        if (xop & 0x10)
3056
                            gen_op_subx_cc(cpu_dst, cpu_src1, cpu_src2);
3057
                        else {
3058
                            gen_mov_reg_C(cpu_tmp0, cpu_psr);
3059
                            tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
3060
                            tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_tmp0);
3061
                        }
3062
                        break;
3063
#ifdef TARGET_SPARC64
3064
                    case 0xd: /* V9 udivx */
3065
                        tcg_gen_mov_tl(cpu_cc_src, cpu_src1);
3066
                        tcg_gen_mov_tl(cpu_cc_src2, cpu_src2);
3067
                        gen_trap_ifdivzero_tl(cpu_cc_src2);
3068
                        tcg_gen_divu_i64(cpu_dst, cpu_cc_src, cpu_cc_src2);
3069
                        break;
3070
#endif
3071
                    case 0xe:
3072
                        CHECK_IU_FEATURE(dc, DIV);
3073
                        tcg_gen_helper_1_2(helper_udiv, cpu_dst, cpu_src1,
3074
                                           cpu_src2);
3075
                        if (xop & 0x10)
3076
                            gen_op_div_cc(cpu_dst);
3077
                        break;
3078
                    case 0xf:
3079
                        CHECK_IU_FEATURE(dc, DIV);
3080
                        tcg_gen_helper_1_2(helper_sdiv, cpu_dst, cpu_src1,
3081
                                           cpu_src2);
3082
                        if (xop & 0x10)
3083
                            gen_op_div_cc(cpu_dst);
3084
                        break;
3085
                    default:
3086
                        goto illegal_insn;
3087
                    }
3088
                    gen_movl_TN_reg(rd, cpu_dst);
3089
                } else {
3090
                    switch (xop) {
3091
                    case 0x20: /* taddcc */
3092
                        gen_op_tadd_cc(cpu_dst, cpu_src1, cpu_src2);
3093
                        gen_movl_TN_reg(rd, cpu_dst);
3094
                        break;
3095
                    case 0x21: /* tsubcc */
3096
                        gen_op_tsub_cc(cpu_dst, cpu_src1, cpu_src2);
3097
                        gen_movl_TN_reg(rd, cpu_dst);
3098
                        break;
3099
                    case 0x22: /* taddcctv */
3100
                        save_state(dc, cpu_cond);
3101
                        gen_op_tadd_ccTV(cpu_dst, cpu_src1, cpu_src2);
3102
                        gen_movl_TN_reg(rd, cpu_dst);
3103
                        break;
3104
                    case 0x23: /* tsubcctv */
3105
                        save_state(dc, cpu_cond);
3106
                        gen_op_tsub_ccTV(cpu_dst, cpu_src1, cpu_src2);
3107
                        gen_movl_TN_reg(rd, cpu_dst);
3108
                        break;
3109
                    case 0x24: /* mulscc */
3110
                        gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2);
3111
                        gen_movl_TN_reg(rd, cpu_dst);
3112
                        break;
3113
#ifndef TARGET_SPARC64
3114
                    case 0x25:  /* sll */
3115
                        if (IS_IMM) { /* immediate */
3116
                            rs2 = GET_FIELDs(insn, 20, 31);
3117
                            tcg_gen_shli_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3118
                        } else { /* register */
3119
                            tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3120
                            tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0);
3121
                        }
3122
                        gen_movl_TN_reg(rd, cpu_dst);
3123
                        break;
3124
                    case 0x26:  /* srl */
3125
                        if (IS_IMM) { /* immediate */
3126
                            rs2 = GET_FIELDs(insn, 20, 31);
3127
                            tcg_gen_shri_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3128
                        } else { /* register */
3129
                            tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3130
                            tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0);
3131
                        }
3132
                        gen_movl_TN_reg(rd, cpu_dst);
3133
                        break;
3134
                    case 0x27:  /* sra */
3135
                        if (IS_IMM) { /* immediate */
3136
                            rs2 = GET_FIELDs(insn, 20, 31);
3137
                            tcg_gen_sari_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3138
                        } else { /* register */
3139
                            tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3140
                            tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0);
3141
                        }
3142
                        gen_movl_TN_reg(rd, cpu_dst);
3143
                        break;
3144
#endif
3145
                    case 0x30:
3146
                        {
3147
                            switch(rd) {
3148
                            case 0: /* wry */
3149
                                tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3150
                                tcg_gen_st_tl(cpu_tmp0, cpu_env,
3151
                                              offsetof(CPUSPARCState, y));
3152
                                break;
3153
#ifndef TARGET_SPARC64
3154
                            case 0x01 ... 0x0f: /* undefined in the
3155
                                                   SPARCv8 manual, nop
3156
                                                   on the microSPARC
3157
                                                   II */
3158
                            case 0x10 ... 0x1f: /* implementation-dependent
3159
                                                   in the SPARCv8
3160
                                                   manual, nop on the
3161
                                                   microSPARC II */
3162
                                break;
3163
#else
3164
                            case 0x2: /* V9 wrccr */
3165
                                tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3166
                                tcg_gen_helper_0_1(helper_wrccr, cpu_dst);
3167
                                break;
3168
                            case 0x3: /* V9 wrasi */
3169
                                tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3170
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3171
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3172
                                               offsetof(CPUSPARCState, asi));
3173
                                break;
3174
                            case 0x6: /* V9 wrfprs */
3175
                                tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3176
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3177
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3178
                                               offsetof(CPUSPARCState, fprs));
3179
                                save_state(dc, cpu_cond);
3180
                                gen_op_next_insn();
3181
                                tcg_gen_exit_tb(0);
3182
                                dc->is_br = 1;
3183
                                break;
3184
                            case 0xf: /* V9 sir, nop if user */
3185
#if !defined(CONFIG_USER_ONLY)
3186
                                if (supervisor(dc))
3187
                                    ; // XXX
3188
#endif
3189
                                break;
3190
                            case 0x13: /* Graphics Status */
3191
                                if (gen_trap_ifnofpu(dc, cpu_cond))
3192
                                    goto jmp_insn;
3193
                                tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3194
                                tcg_gen_st_tl(cpu_tmp0, cpu_env,
3195
                                              offsetof(CPUSPARCState, gsr));
3196
                                break;
3197
                            case 0x17: /* Tick compare */
3198
#if !defined(CONFIG_USER_ONLY)
3199
                                if (!supervisor(dc))
3200
                                    goto illegal_insn;
3201
#endif
3202
                                {
3203
                                    TCGv r_tickptr;
3204

    
3205
                                    tcg_gen_xor_tl(cpu_tmp0, cpu_src1,
3206
                                                   cpu_src2);
3207
                                    tcg_gen_st_tl(cpu_tmp0, cpu_env,
3208
                                                  offsetof(CPUSPARCState,
3209
                                                           tick_cmpr));
3210
                                    r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3211
                                    tcg_gen_ld_ptr(r_tickptr, cpu_env,
3212
                                                   offsetof(CPUState, tick));
3213
                                    tcg_gen_helper_0_2(helper_tick_set_limit,
3214
                                                       r_tickptr, cpu_tmp0);
3215
                                    tcg_temp_free(r_tickptr);
3216
                                }
3217
                                break;
3218
                            case 0x18: /* System tick */
3219
#if !defined(CONFIG_USER_ONLY)
3220
                                if (!supervisor(dc))
3221
                                    goto illegal_insn;
3222
#endif
3223
                                {
3224
                                    TCGv r_tickptr;
3225

    
3226
                                    tcg_gen_xor_tl(cpu_dst, cpu_src1,
3227
                                                   cpu_src2);
3228
                                    r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3229
                                    tcg_gen_ld_ptr(r_tickptr, cpu_env,
3230
                                                   offsetof(CPUState, stick));
3231
                                    tcg_gen_helper_0_2(helper_tick_set_count,
3232
                                                       r_tickptr, cpu_dst);
3233
                                    tcg_temp_free(r_tickptr);
3234
                                }
3235
                                break;
3236
                            case 0x19: /* System tick compare */
3237
#if !defined(CONFIG_USER_ONLY)
3238
                                if (!supervisor(dc))
3239
                                    goto illegal_insn;
3240
#endif
3241
                                {
3242
                                    TCGv r_tickptr;
3243

    
3244
                                    tcg_gen_xor_tl(cpu_tmp0, cpu_src1,
3245
                                                   cpu_src2);
3246
                                    tcg_gen_st_tl(cpu_tmp0, cpu_env,
3247
                                                  offsetof(CPUSPARCState,
3248
                                                           stick_cmpr));
3249
                                    r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3250
                                    tcg_gen_ld_ptr(r_tickptr, cpu_env,
3251
                                                   offsetof(CPUState, stick));
3252
                                    tcg_gen_helper_0_2(helper_tick_set_limit,
3253
                                                       r_tickptr, cpu_tmp0);
3254
                                    tcg_temp_free(r_tickptr);
3255
                                }
3256
                                break;
3257

    
3258
                            case 0x10: /* Performance Control */
3259
                            case 0x11: /* Performance Instrumentation
3260
                                          Counter */
3261
                            case 0x12: /* Dispatch Control */
3262
                            case 0x14: /* Softint set */
3263
                            case 0x15: /* Softint clear */
3264
                            case 0x16: /* Softint write */
3265
#endif
3266
                            default:
3267
                                goto illegal_insn;
3268
                            }
3269
                        }
3270
                        break;
3271
#if !defined(CONFIG_USER_ONLY)
3272
                    case 0x31: /* wrpsr, V9 saved, restored */
3273
                        {
3274
                            if (!supervisor(dc))
3275
                                goto priv_insn;
3276
#ifdef TARGET_SPARC64
3277
                            switch (rd) {
3278
                            case 0:
3279
                                tcg_gen_helper_0_0(helper_saved);
3280
                                break;
3281
                            case 1:
3282
                                tcg_gen_helper_0_0(helper_restored);
3283
                                break;
3284
                            case 2: /* UA2005 allclean */
3285
                            case 3: /* UA2005 otherw */
3286
                            case 4: /* UA2005 normalw */
3287
                            case 5: /* UA2005 invalw */
3288
                                // XXX
3289
                            default:
3290
                                goto illegal_insn;
3291
                            }
3292
#else
3293
                            tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3294
                            tcg_gen_helper_0_1(helper_wrpsr, cpu_dst);
3295
                            save_state(dc, cpu_cond);
3296
                            gen_op_next_insn();
3297
                            tcg_gen_exit_tb(0);
3298
                            dc->is_br = 1;
3299
#endif
3300
                        }
3301
                        break;
3302
                    case 0x32: /* wrwim, V9 wrpr */
3303
                        {
3304
                            if (!supervisor(dc))
3305
                                goto priv_insn;
3306
                            tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3307
#ifdef TARGET_SPARC64
3308
                            switch (rd) {
3309
                            case 0: // tpc
3310
                                {
3311
                                    TCGv r_tsptr;
3312

    
3313
                                    r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3314
                                    tcg_gen_ld_ptr(r_tsptr, cpu_env,
3315
                                                   offsetof(CPUState, tsptr));
3316
                                    tcg_gen_st_tl(cpu_tmp0, r_tsptr,
3317
                                                  offsetof(trap_state, tpc));
3318
                                    tcg_temp_free(r_tsptr);
3319
                                }
3320
                                break;
3321
                            case 1: // tnpc
3322
                                {
3323
                                    TCGv r_tsptr;
3324

    
3325
                                    r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3326
                                    tcg_gen_ld_ptr(r_tsptr, cpu_env,
3327
                                                   offsetof(CPUState, tsptr));
3328
                                    tcg_gen_st_tl(cpu_tmp0, r_tsptr,
3329
                                                  offsetof(trap_state, tnpc));
3330
                                    tcg_temp_free(r_tsptr);
3331
                                }
3332
                                break;
3333
                            case 2: // tstate
3334
                                {
3335
                                    TCGv r_tsptr;
3336

    
3337
                                    r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3338
                                    tcg_gen_ld_ptr(r_tsptr, cpu_env,
3339
                                                   offsetof(CPUState, tsptr));
3340
                                    tcg_gen_st_tl(cpu_tmp0, r_tsptr,
3341
                                                  offsetof(trap_state,
3342
                                                           tstate));
3343
                                    tcg_temp_free(r_tsptr);
3344
                                }
3345
                                break;
3346
                            case 3: // tt
3347
                                {
3348
                                    TCGv r_tsptr;
3349

    
3350
                                    r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3351
                                    tcg_gen_ld_ptr(r_tsptr, cpu_env,
3352
                                                   offsetof(CPUState, tsptr));
3353
                                    tcg_gen_st_i32(cpu_tmp0, r_tsptr,
3354
                                                   offsetof(trap_state, tt));
3355
                                    tcg_temp_free(r_tsptr);
3356
                                }
3357
                                break;
3358
                            case 4: // tick
3359
                                {
3360
                                    TCGv r_tickptr;
3361

    
3362
                                    r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3363
                                    tcg_gen_ld_ptr(r_tickptr, cpu_env,
3364
                                                   offsetof(CPUState, tick));
3365
                                    tcg_gen_helper_0_2(helper_tick_set_count,
3366
                                                       r_tickptr, cpu_tmp0);
3367
                                    tcg_temp_free(r_tickptr);
3368
                                }
3369
                                break;
3370
                            case 5: // tba
3371
                                tcg_gen_st_tl(cpu_tmp0, cpu_env,
3372
                                              offsetof(CPUSPARCState, tbr));
3373
                                break;
3374
                            case 6: // pstate
3375
                                save_state(dc, cpu_cond);
3376
                                tcg_gen_helper_0_1(helper_wrpstate, cpu_tmp0);
3377
                                gen_op_next_insn();
3378
                                tcg_gen_exit_tb(0);
3379
                                dc->is_br = 1;
3380
                                break;
3381
                            case 7: // tl
3382
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3383
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3384
                                               offsetof(CPUSPARCState, tl));
3385
                                break;
3386
                            case 8: // pil
3387
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3388
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3389
                                               offsetof(CPUSPARCState,
3390
                                                        psrpil));
3391
                                break;
3392
                            case 9: // cwp
3393
                                tcg_gen_helper_0_1(helper_wrcwp, cpu_tmp0);
3394
                                break;
3395
                            case 10: // cansave
3396
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3397
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3398
                                               offsetof(CPUSPARCState,
3399
                                                        cansave));
3400
                                break;
3401
                            case 11: // canrestore
3402
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3403
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3404
                                               offsetof(CPUSPARCState,
3405
                                                        canrestore));
3406
                                break;
3407
                            case 12: // cleanwin
3408
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3409
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3410
                                               offsetof(CPUSPARCState,
3411
                                                        cleanwin));
3412
                                break;
3413
                            case 13: // otherwin
3414
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3415
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3416
                                               offsetof(CPUSPARCState,
3417
                                                        otherwin));
3418
                                break;
3419
                            case 14: // wstate
3420
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3421
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3422
                                               offsetof(CPUSPARCState,
3423
                                                        wstate));
3424
                                break;
3425
                            case 16: // UA2005 gl
3426
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3427
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3428
                                               offsetof(CPUSPARCState, gl));
3429
                                break;
3430
                            case 26: // UA2005 strand status
3431
                                if (!hypervisor(dc))
3432
                                    goto priv_insn;
3433
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3434
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3435
                                               offsetof(CPUSPARCState, ssr));
3436
                                break;
3437
                            default:
3438
                                goto illegal_insn;
3439
                            }
3440
#else
3441
                            tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3442
                            tcg_gen_st_i32(cpu_tmp32, cpu_env,
3443
                                           offsetof(CPUSPARCState, wim));
3444
#endif
3445
                        }
3446
                        break;
3447
                    case 0x33: /* wrtbr, UA2005 wrhpr */
3448
                        {
3449
#ifndef TARGET_SPARC64
3450
                            if (!supervisor(dc))
3451
                                goto priv_insn;
3452
                            tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3453
                            tcg_gen_st_tl(cpu_tmp0, cpu_env,
3454
                                          offsetof(CPUSPARCState, tbr));
3455
#else
3456
                            if (!hypervisor(dc))
3457
                                goto priv_insn;
3458
                            tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3459
                            switch (rd) {
3460
                            case 0: // hpstate
3461
                                // XXX gen_op_wrhpstate();
3462
                                save_state(dc, cpu_cond);
3463
                                gen_op_next_insn();
3464
                                tcg_gen_exit_tb(0);
3465
                                dc->is_br = 1;
3466
                                break;
3467
                            case 1: // htstate
3468
                                // XXX gen_op_wrhtstate();
3469
                                break;
3470
                            case 3: // hintp
3471
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3472
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3473
                                               offsetof(CPUSPARCState, hintp));
3474
                                break;
3475
                            case 5: // htba
3476
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3477
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3478
                                               offsetof(CPUSPARCState, htba));
3479
                                break;
3480
                            case 31: // hstick_cmpr
3481
                                {
3482
                                    TCGv r_tickptr;
3483

    
3484
                                    tcg_gen_st_tl(cpu_tmp0, cpu_env,
3485
                                                  offsetof(CPUSPARCState,
3486
                                                           hstick_cmpr));
3487
                                    r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3488
                                    tcg_gen_ld_ptr(r_tickptr, cpu_env,
3489
                                                   offsetof(CPUState, hstick));
3490
                                    tcg_gen_helper_0_2(helper_tick_set_limit,
3491
                                                       r_tickptr, cpu_tmp0);
3492
                                    tcg_temp_free(r_tickptr);
3493
                                }
3494
                                break;
3495
                            case 6: // hver readonly
3496
                            default:
3497
                                goto illegal_insn;
3498
                            }
3499
#endif
3500
                        }
3501
                        break;
3502
#endif
3503
#ifdef TARGET_SPARC64
3504
                    case 0x2c: /* V9 movcc */
3505
                        {
3506
                            int cc = GET_FIELD_SP(insn, 11, 12);
3507
                            int cond = GET_FIELD_SP(insn, 14, 17);
3508
                            TCGv r_cond;
3509
                            int l1;
3510

    
3511
                            r_cond = tcg_temp_new(TCG_TYPE_TL);
3512
                            if (insn & (1 << 18)) {
3513
                                if (cc == 0)
3514
                                    gen_cond(r_cond, 0, cond);
3515
                                else if (cc == 2)
3516
                                    gen_cond(r_cond, 1, cond);
3517
                                else
3518
                                    goto illegal_insn;
3519
                            } else {
3520
                                gen_fcond(r_cond, cc, cond);
3521
                            }
3522

    
3523
                            l1 = gen_new_label();
3524

    
3525
                            tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
3526
                            if (IS_IMM) {       /* immediate */
3527
                                TCGv r_const;
3528

    
3529
                                rs2 = GET_FIELD_SPs(insn, 0, 10);
3530
                                r_const = tcg_const_tl((int)rs2);
3531
                                gen_movl_TN_reg(rd, r_const);
3532
                                tcg_temp_free(r_const);
3533
                            } else {
3534
                                rs2 = GET_FIELD_SP(insn, 0, 4);
3535
                                gen_movl_reg_TN(rs2, cpu_tmp0);
3536
                                gen_movl_TN_reg(rd, cpu_tmp0);
3537
                            }
3538
                            gen_set_label(l1);
3539
                            tcg_temp_free(r_cond);
3540
                            break;
3541
                        }
3542
                    case 0x2d: /* V9 sdivx */
3543
                        gen_op_sdivx(cpu_dst, cpu_src1, cpu_src2);
3544
                        gen_movl_TN_reg(rd, cpu_dst);
3545
                        break;
3546
                    case 0x2e: /* V9 popc */
3547
                        {
3548
                            cpu_src2 = get_src2(insn, cpu_src2);
3549
                            tcg_gen_helper_1_1(helper_popc, cpu_dst,
3550
                                               cpu_src2);
3551
                            gen_movl_TN_reg(rd, cpu_dst);
3552
                        }
3553
                    case 0x2f: /* V9 movr */
3554
                        {
3555
                            int cond = GET_FIELD_SP(insn, 10, 12);
3556
                            int l1;
3557

    
3558
                            cpu_src1 = get_src1(insn, cpu_src1);
3559

    
3560
                            l1 = gen_new_label();
3561

    
3562
                            tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond],
3563
                                              cpu_src1, 0, l1);
3564
                            if (IS_IMM) {       /* immediate */
3565
                                TCGv r_const;
3566

    
3567
                                rs2 = GET_FIELD_SPs(insn, 0, 9);
3568
                                r_const = tcg_const_tl((int)rs2);
3569
                                gen_movl_TN_reg(rd, r_const);
3570
                                tcg_temp_free(r_const);
3571
                            } else {
3572
                                rs2 = GET_FIELD_SP(insn, 0, 4);
3573
                                gen_movl_reg_TN(rs2, cpu_tmp0);
3574
                                gen_movl_TN_reg(rd, cpu_tmp0);
3575
                            }
3576
                            gen_set_label(l1);
3577
                            break;
3578
                        }
3579
#endif
3580
                    default:
3581
                        goto illegal_insn;
3582
                    }
3583
                }
3584
            } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
3585
#ifdef TARGET_SPARC64
3586
                int opf = GET_FIELD_SP(insn, 5, 13);
3587
                rs1 = GET_FIELD(insn, 13, 17);
3588
                rs2 = GET_FIELD(insn, 27, 31);
3589
                if (gen_trap_ifnofpu(dc, cpu_cond))
3590
                    goto jmp_insn;
3591

    
3592
                switch (opf) {
3593
                case 0x000: /* VIS I edge8cc */
3594
                case 0x001: /* VIS II edge8n */
3595
                case 0x002: /* VIS I edge8lcc */
3596
                case 0x003: /* VIS II edge8ln */
3597
                case 0x004: /* VIS I edge16cc */
3598
                case 0x005: /* VIS II edge16n */
3599
                case 0x006: /* VIS I edge16lcc */
3600
                case 0x007: /* VIS II edge16ln */
3601
                case 0x008: /* VIS I edge32cc */
3602
                case 0x009: /* VIS II edge32n */
3603
                case 0x00a: /* VIS I edge32lcc */
3604
                case 0x00b: /* VIS II edge32ln */
3605
                    // XXX
3606
                    goto illegal_insn;
3607
                case 0x010: /* VIS I array8 */
3608
                    CHECK_FPU_FEATURE(dc, VIS1);
3609
                    cpu_src1 = get_src1(insn, cpu_src1);
3610
                    gen_movl_reg_TN(rs2, cpu_src2);
3611
                    tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3612
                                       cpu_src2);
3613
                    gen_movl_TN_reg(rd, cpu_dst);
3614
                    break;
3615
                case 0x012: /* VIS I array16 */
3616
                    CHECK_FPU_FEATURE(dc, VIS1);
3617
                    cpu_src1 = get_src1(insn, cpu_src1);
3618
                    gen_movl_reg_TN(rs2, cpu_src2);
3619
                    tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3620
                                       cpu_src2);
3621
                    tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
3622
                    gen_movl_TN_reg(rd, cpu_dst);
3623
                    break;
3624
                case 0x014: /* VIS I array32 */
3625
                    CHECK_FPU_FEATURE(dc, VIS1);
3626
                    cpu_src1 = get_src1(insn, cpu_src1);
3627
                    gen_movl_reg_TN(rs2, cpu_src2);
3628
                    tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3629
                                       cpu_src2);
3630
                    tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
3631
                    gen_movl_TN_reg(rd, cpu_dst);
3632
                    break;
3633
                case 0x018: /* VIS I alignaddr */
3634
                    CHECK_FPU_FEATURE(dc, VIS1);
3635
                    cpu_src1 = get_src1(insn, cpu_src1);
3636
                    gen_movl_reg_TN(rs2, cpu_src2);
3637
                    tcg_gen_helper_1_2(helper_alignaddr, cpu_dst, cpu_src1,
3638
                                       cpu_src2);
3639
                    gen_movl_TN_reg(rd, cpu_dst);
3640
                    break;
3641
                case 0x019: /* VIS II bmask */
3642
                case 0x01a: /* VIS I alignaddrl */
3643
                    // XXX
3644
                    goto illegal_insn;
3645
                case 0x020: /* VIS I fcmple16 */
3646
                    CHECK_FPU_FEATURE(dc, VIS1);
3647
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3648
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3649
                    tcg_gen_helper_0_0(helper_fcmple16);
3650
                    gen_op_store_DT0_fpr(DFPREG(rd));
3651
                    break;
3652
                case 0x022: /* VIS I fcmpne16 */
3653
                    CHECK_FPU_FEATURE(dc, VIS1);
3654
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3655
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3656
                    tcg_gen_helper_0_0(helper_fcmpne16);
3657
                    gen_op_store_DT0_fpr(DFPREG(rd));
3658
                    break;
3659
                case 0x024: /* VIS I fcmple32 */
3660
                    CHECK_FPU_FEATURE(dc, VIS1);
3661
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3662
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3663
                    tcg_gen_helper_0_0(helper_fcmple32);
3664
                    gen_op_store_DT0_fpr(DFPREG(rd));
3665
                    break;
3666
                case 0x026: /* VIS I fcmpne32 */
3667
                    CHECK_FPU_FEATURE(dc, VIS1);
3668
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3669
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3670
                    tcg_gen_helper_0_0(helper_fcmpne32);
3671
                    gen_op_store_DT0_fpr(DFPREG(rd));
3672
                    break;
3673
                case 0x028: /* VIS I fcmpgt16 */
3674
                    CHECK_FPU_FEATURE(dc, VIS1);
3675
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3676
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3677
                    tcg_gen_helper_0_0(helper_fcmpgt16);
3678
                    gen_op_store_DT0_fpr(DFPREG(rd));
3679
                    break;
3680
                case 0x02a: /* VIS I fcmpeq16 */
3681
                    CHECK_FPU_FEATURE(dc, VIS1);
3682
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3683
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3684
                    tcg_gen_helper_0_0(helper_fcmpeq16);
3685
                    gen_op_store_DT0_fpr(DFPREG(rd));
3686
                    break;
3687
                case 0x02c: /* VIS I fcmpgt32 */
3688
                    CHECK_FPU_FEATURE(dc, VIS1);
3689
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3690
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3691
                    tcg_gen_helper_0_0(helper_fcmpgt32);
3692
                    gen_op_store_DT0_fpr(DFPREG(rd));
3693
                    break;
3694
                case 0x02e: /* VIS I fcmpeq32 */
3695
                    CHECK_FPU_FEATURE(dc, VIS1);
3696
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3697
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3698
                    tcg_gen_helper_0_0(helper_fcmpeq32);
3699
                    gen_op_store_DT0_fpr(DFPREG(rd));
3700
                    break;
3701
                case 0x031: /* VIS I fmul8x16 */
3702
                    CHECK_FPU_FEATURE(dc, VIS1);
3703
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3704
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3705
                    tcg_gen_helper_0_0(helper_fmul8x16);
3706
                    gen_op_store_DT0_fpr(DFPREG(rd));
3707
                    break;
3708
                case 0x033: /* VIS I fmul8x16au */
3709
                    CHECK_FPU_FEATURE(dc, VIS1);
3710
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3711
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3712
                    tcg_gen_helper_0_0(helper_fmul8x16au);
3713
                    gen_op_store_DT0_fpr(DFPREG(rd));
3714
                    break;
3715
                case 0x035: /* VIS I fmul8x16al */
3716
                    CHECK_FPU_FEATURE(dc, VIS1);
3717
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3718
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3719
                    tcg_gen_helper_0_0(helper_fmul8x16al);
3720
                    gen_op_store_DT0_fpr(DFPREG(rd));
3721
                    break;
3722
                case 0x036: /* VIS I fmul8sux16 */
3723
                    CHECK_FPU_FEATURE(dc, VIS1);
3724
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3725
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3726
                    tcg_gen_helper_0_0(helper_fmul8sux16);
3727
                    gen_op_store_DT0_fpr(DFPREG(rd));
3728
                    break;
3729
                case 0x037: /* VIS I fmul8ulx16 */
3730
                    CHECK_FPU_FEATURE(dc, VIS1);
3731
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3732
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3733
                    tcg_gen_helper_0_0(helper_fmul8ulx16);
3734
                    gen_op_store_DT0_fpr(DFPREG(rd));
3735
                    break;
3736
                case 0x038: /* VIS I fmuld8sux16 */
3737
                    CHECK_FPU_FEATURE(dc, VIS1);
3738
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3739
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3740
                    tcg_gen_helper_0_0(helper_fmuld8sux16);
3741
                    gen_op_store_DT0_fpr(DFPREG(rd));
3742
                    break;
3743
                case 0x039: /* VIS I fmuld8ulx16 */
3744
                    CHECK_FPU_FEATURE(dc, VIS1);
3745
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3746
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3747
                    tcg_gen_helper_0_0(helper_fmuld8ulx16);
3748
                    gen_op_store_DT0_fpr(DFPREG(rd));
3749
                    break;
3750
                case 0x03a: /* VIS I fpack32 */
3751
                case 0x03b: /* VIS I fpack16 */
3752
                case 0x03d: /* VIS I fpackfix */
3753
                case 0x03e: /* VIS I pdist */
3754
                    // XXX
3755
                    goto illegal_insn;
3756
                case 0x048: /* VIS I faligndata */
3757
                    CHECK_FPU_FEATURE(dc, VIS1);
3758
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3759
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3760
                    tcg_gen_helper_0_0(helper_faligndata);
3761
                    gen_op_store_DT0_fpr(DFPREG(rd));
3762
                    break;
3763
                case 0x04b: /* VIS I fpmerge */
3764
                    CHECK_FPU_FEATURE(dc, VIS1);
3765
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3766
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3767
                    tcg_gen_helper_0_0(helper_fpmerge);
3768
                    gen_op_store_DT0_fpr(DFPREG(rd));
3769
                    break;
3770
                case 0x04c: /* VIS II bshuffle */
3771
                    // XXX
3772
                    goto illegal_insn;
3773
                case 0x04d: /* VIS I fexpand */
3774
                    CHECK_FPU_FEATURE(dc, VIS1);
3775
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3776
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3777
                    tcg_gen_helper_0_0(helper_fexpand);
3778
                    gen_op_store_DT0_fpr(DFPREG(rd));
3779
                    break;
3780
                case 0x050: /* VIS I fpadd16 */
3781
                    CHECK_FPU_FEATURE(dc, VIS1);
3782
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3783
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3784
                    tcg_gen_helper_0_0(helper_fpadd16);
3785
                    gen_op_store_DT0_fpr(DFPREG(rd));
3786
                    break;
3787
                case 0x051: /* VIS I fpadd16s */
3788
                    CHECK_FPU_FEATURE(dc, VIS1);
3789
                    gen_op_load_fpr_FT0(rs1);
3790
                    gen_op_load_fpr_FT1(rs2);
3791
                    tcg_gen_helper_0_0(helper_fpadd16s);
3792
                    gen_op_store_FT0_fpr(rd);
3793
                    break;
3794
                case 0x052: /* VIS I fpadd32 */
3795
                    CHECK_FPU_FEATURE(dc, VIS1);
3796
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3797
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3798
                    tcg_gen_helper_0_0(helper_fpadd32);
3799
                    gen_op_store_DT0_fpr(DFPREG(rd));
3800
                    break;
3801
                case 0x053: /* VIS I fpadd32s */
3802
                    CHECK_FPU_FEATURE(dc, VIS1);
3803
                    gen_op_load_fpr_FT0(rs1);
3804
                    gen_op_load_fpr_FT1(rs2);
3805
                    tcg_gen_helper_0_0(helper_fpadd32s);
3806
                    gen_op_store_FT0_fpr(rd);
3807
                    break;
3808
                case 0x054: /* VIS I fpsub16 */
3809
                    CHECK_FPU_FEATURE(dc, VIS1);
3810
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3811
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3812
                    tcg_gen_helper_0_0(helper_fpsub16);
3813
                    gen_op_store_DT0_fpr(DFPREG(rd));
3814
                    break;
3815
                case 0x055: /* VIS I fpsub16s */
3816
                    CHECK_FPU_FEATURE(dc, VIS1);
3817
                    gen_op_load_fpr_FT0(rs1);
3818
                    gen_op_load_fpr_FT1(rs2);
3819
                    tcg_gen_helper_0_0(helper_fpsub16s);
3820
                    gen_op_store_FT0_fpr(rd);
3821
                    break;
3822
                case 0x056: /* VIS I fpsub32 */
3823
                    CHECK_FPU_FEATURE(dc, VIS1);
3824
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3825
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3826
                    tcg_gen_helper_0_0(helper_fpadd32);
3827
                    gen_op_store_DT0_fpr(DFPREG(rd));
3828
                    break;
3829
                case 0x057: /* VIS I fpsub32s */
3830
                    CHECK_FPU_FEATURE(dc, VIS1);
3831
                    gen_op_load_fpr_FT0(rs1);
3832
                    gen_op_load_fpr_FT1(rs2);
3833
                    tcg_gen_helper_0_0(helper_fpsub32s);
3834
                    gen_op_store_FT0_fpr(rd);
3835
                    break;
3836
                case 0x060: /* VIS I fzero */
3837
                    CHECK_FPU_FEATURE(dc, VIS1);
3838
                    tcg_gen_helper_0_0(helper_movl_DT0_0);
3839
                    gen_op_store_DT0_fpr(DFPREG(rd));
3840
                    break;
3841
                case 0x061: /* VIS I fzeros */
3842
                    CHECK_FPU_FEATURE(dc, VIS1);
3843
                    tcg_gen_helper_0_0(helper_movl_FT0_0);
3844
                    gen_op_store_FT0_fpr(rd);
3845
                    break;
3846
                case 0x062: /* VIS I fnor */
3847
                    CHECK_FPU_FEATURE(dc, VIS1);
3848
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3849
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3850
                    tcg_gen_helper_0_0(helper_fnor);
3851
                    gen_op_store_DT0_fpr(DFPREG(rd));
3852
                    break;
3853
                case 0x063: /* VIS I fnors */
3854
                    CHECK_FPU_FEATURE(dc, VIS1);
3855
                    gen_op_load_fpr_FT0(rs1);
3856
                    gen_op_load_fpr_FT1(rs2);
3857
                    tcg_gen_helper_0_0(helper_fnors);
3858
                    gen_op_store_FT0_fpr(rd);
3859
                    break;
3860
                case 0x064: /* VIS I fandnot2 */
3861
                    CHECK_FPU_FEATURE(dc, VIS1);
3862
                    gen_op_load_fpr_DT1(DFPREG(rs1));
3863
                    gen_op_load_fpr_DT0(DFPREG(rs2));
3864
                    tcg_gen_helper_0_0(helper_fandnot);
3865
                    gen_op_store_DT0_fpr(DFPREG(rd));
3866
                    break;
3867
                case 0x065: /* VIS I fandnot2s */
3868
                    CHECK_FPU_FEATURE(dc, VIS1);
3869
                    gen_op_load_fpr_FT1(rs1);
3870
                    gen_op_load_fpr_FT0(rs2);
3871
                    tcg_gen_helper_0_0(helper_fandnots);
3872
                    gen_op_store_FT0_fpr(rd);
3873
                    break;
3874
                case 0x066: /* VIS I fnot2 */
3875
                    CHECK_FPU_FEATURE(dc, VIS1);
3876
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3877
                    tcg_gen_helper_0_0(helper_fnot);
3878
                    gen_op_store_DT0_fpr(DFPREG(rd));
3879
                    break;
3880
                case 0x067: /* VIS I fnot2s */
3881
                    CHECK_FPU_FEATURE(dc, VIS1);
3882
                    gen_op_load_fpr_FT1(rs2);
3883
                    tcg_gen_helper_0_0(helper_fnot);
3884
                    gen_op_store_FT0_fpr(rd);
3885
                    break;
3886
                case 0x068: /* VIS I fandnot1 */
3887
                    CHECK_FPU_FEATURE(dc, VIS1);
3888
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3889
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3890
                    tcg_gen_helper_0_0(helper_fandnot);
3891
                    gen_op_store_DT0_fpr(DFPREG(rd));
3892
                    break;
3893
                case 0x069: /* VIS I fandnot1s */
3894
                    CHECK_FPU_FEATURE(dc, VIS1);
3895
                    gen_op_load_fpr_FT0(rs1);
3896
                    gen_op_load_fpr_FT1(rs2);
3897
                    tcg_gen_helper_0_0(helper_fandnots);
3898
                    gen_op_store_FT0_fpr(rd);
3899
                    break;
3900
                case 0x06a: /* VIS I fnot1 */
3901
                    CHECK_FPU_FEATURE(dc, VIS1);
3902
                    gen_op_load_fpr_DT1(DFPREG(rs1));
3903
                    tcg_gen_helper_0_0(helper_fnot);
3904
                    gen_op_store_DT0_fpr(DFPREG(rd));
3905
                    break;
3906
                case 0x06b: /* VIS I fnot1s */
3907
                    CHECK_FPU_FEATURE(dc, VIS1);
3908
                    gen_op_load_fpr_FT1(rs1);
3909
                    tcg_gen_helper_0_0(helper_fnot);
3910
                    gen_op_store_FT0_fpr(rd);
3911
                    break;
3912
                case 0x06c: /* VIS I fxor */
3913
                    CHECK_FPU_FEATURE(dc, VIS1);
3914
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3915
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3916
                    tcg_gen_helper_0_0(helper_fxor);
3917
                    gen_op_store_DT0_fpr(DFPREG(rd));
3918
                    break;
3919
                case 0x06d: /* VIS I fxors */
3920
                    CHECK_FPU_FEATURE(dc, VIS1);
3921
                    gen_op_load_fpr_FT0(rs1);
3922
                    gen_op_load_fpr_FT1(rs2);
3923
                    tcg_gen_helper_0_0(helper_fxors);
3924
                    gen_op_store_FT0_fpr(rd);
3925
                    break;
3926
                case 0x06e: /* VIS I fnand */
3927
                    CHECK_FPU_FEATURE(dc, VIS1);
3928
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3929
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3930
                    tcg_gen_helper_0_0(helper_fnand);
3931
                    gen_op_store_DT0_fpr(DFPREG(rd));
3932
                    break;
3933
                case 0x06f: /* VIS I fnands */
3934
                    CHECK_FPU_FEATURE(dc, VIS1);
3935
                    gen_op_load_fpr_FT0(rs1);
3936
                    gen_op_load_fpr_FT1(rs2);
3937
                    tcg_gen_helper_0_0(helper_fnands);
3938
                    gen_op_store_FT0_fpr(rd);
3939
                    break;
3940
                case 0x070: /* VIS I fand */
3941
                    CHECK_FPU_FEATURE(dc, VIS1);
3942
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3943
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3944
                    tcg_gen_helper_0_0(helper_fand);
3945
                    gen_op_store_DT0_fpr(DFPREG(rd));
3946
                    break;
3947
                case 0x071: /* VIS I fands */
3948
                    CHECK_FPU_FEATURE(dc, VIS1);
3949
                    gen_op_load_fpr_FT0(rs1);
3950
                    gen_op_load_fpr_FT1(rs2);
3951
                    tcg_gen_helper_0_0(helper_fands);
3952
                    gen_op_store_FT0_fpr(rd);
3953
                    break;
3954
                case 0x072: /* VIS I fxnor */
3955
                    CHECK_FPU_FEATURE(dc, VIS1);
3956
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3957
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3958
                    tcg_gen_helper_0_0(helper_fxnor);
3959
                    gen_op_store_DT0_fpr(DFPREG(rd));
3960
                    break;
3961
                case 0x073: /* VIS I fxnors */
3962
                    CHECK_FPU_FEATURE(dc, VIS1);
3963
                    gen_op_load_fpr_FT0(rs1);
3964
                    gen_op_load_fpr_FT1(rs2);
3965
                    tcg_gen_helper_0_0(helper_fxnors);
3966
                    gen_op_store_FT0_fpr(rd);
3967
                    break;
3968
                case 0x074: /* VIS I fsrc1 */
3969
                    CHECK_FPU_FEATURE(dc, VIS1);
3970
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3971
                    gen_op_store_DT0_fpr(DFPREG(rd));
3972
                    break;
3973
                case 0x075: /* VIS I fsrc1s */
3974
                    CHECK_FPU_FEATURE(dc, VIS1);
3975
                    gen_op_load_fpr_FT0(rs1);
3976
                    gen_op_store_FT0_fpr(rd);
3977
                    break;
3978
                case 0x076: /* VIS I fornot2 */
3979
                    CHECK_FPU_FEATURE(dc, VIS1);
3980
                    gen_op_load_fpr_DT1(DFPREG(rs1));
3981
                    gen_op_load_fpr_DT0(DFPREG(rs2));
3982
                    tcg_gen_helper_0_0(helper_fornot);
3983
                    gen_op_store_DT0_fpr(DFPREG(rd));
3984
                    break;
3985
                case 0x077: /* VIS I fornot2s */
3986
                    CHECK_FPU_FEATURE(dc, VIS1);
3987
                    gen_op_load_fpr_FT1(rs1);
3988
                    gen_op_load_fpr_FT0(rs2);
3989
                    tcg_gen_helper_0_0(helper_fornots);
3990
                    gen_op_store_FT0_fpr(rd);
3991
                    break;
3992
                case 0x078: /* VIS I fsrc2 */
3993
                    CHECK_FPU_FEATURE(dc, VIS1);
3994
                    gen_op_load_fpr_DT0(DFPREG(rs2));
3995
                    gen_op_store_DT0_fpr(DFPREG(rd));
3996
                    break;
3997
                case 0x079: /* VIS I fsrc2s */
3998
                    CHECK_FPU_FEATURE(dc, VIS1);
3999
                    gen_op_load_fpr_FT0(rs2);
4000
                    gen_op_store_FT0_fpr(rd);
4001
                    break;
4002
                case 0x07a: /* VIS I fornot1 */
4003
                    CHECK_FPU_FEATURE(dc, VIS1);
4004
                    gen_op_load_fpr_DT0(DFPREG(rs1));
4005
                    gen_op_load_fpr_DT1(DFPREG(rs2));
4006
                    tcg_gen_helper_0_0(helper_fornot);
4007
                    gen_op_store_DT0_fpr(DFPREG(rd));
4008
                    break;
4009
                case 0x07b: /* VIS I fornot1s */
4010
                    CHECK_FPU_FEATURE(dc, VIS1);
4011
                    gen_op_load_fpr_FT0(rs1);
4012
                    gen_op_load_fpr_FT1(rs2);
4013
                    tcg_gen_helper_0_0(helper_fornots);
4014
                    gen_op_store_FT0_fpr(rd);
4015
                    break;
4016
                case 0x07c: /* VIS I for */
4017
                    CHECK_FPU_FEATURE(dc, VIS1);
4018
                    gen_op_load_fpr_DT0(DFPREG(rs1));
4019
                    gen_op_load_fpr_DT1(DFPREG(rs2));
4020
                    tcg_gen_helper_0_0(helper_for);
4021
                    gen_op_store_DT0_fpr(DFPREG(rd));
4022
                    break;
4023
                case 0x07d: /* VIS I fors */
4024
                    CHECK_FPU_FEATURE(dc, VIS1);
4025
                    gen_op_load_fpr_FT0(rs1);
4026
                    gen_op_load_fpr_FT1(rs2);
4027
                    tcg_gen_helper_0_0(helper_fors);
4028
                    gen_op_store_FT0_fpr(rd);
4029
                    break;
4030
                case 0x07e: /* VIS I fone */
4031
                    CHECK_FPU_FEATURE(dc, VIS1);
4032
                    tcg_gen_helper_0_0(helper_movl_DT0_1);
4033
                    gen_op_store_DT0_fpr(DFPREG(rd));
4034
                    break;
4035
                case 0x07f: /* VIS I fones */
4036
                    CHECK_FPU_FEATURE(dc, VIS1);
4037
                    tcg_gen_helper_0_0(helper_movl_FT0_1);
4038
                    gen_op_store_FT0_fpr(rd);
4039
                    break;
4040
                case 0x080: /* VIS I shutdown */
4041
                case 0x081: /* VIS II siam */
4042
                    // XXX
4043
                    goto illegal_insn;
4044
                default:
4045
                    goto illegal_insn;
4046
                }
4047
#else
4048
                goto ncp_insn;
4049
#endif
4050
            } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
4051
#ifdef TARGET_SPARC64
4052
                goto illegal_insn;
4053
#else
4054
                goto ncp_insn;
4055
#endif
4056
#ifdef TARGET_SPARC64
4057
            } else if (xop == 0x39) { /* V9 return */
4058
                TCGv r_const;
4059

    
4060
                save_state(dc, cpu_cond);
4061
                cpu_src1 = get_src1(insn, cpu_src1);
4062
                if (IS_IMM) {   /* immediate */
4063
                    rs2 = GET_FIELDs(insn, 19, 31);
4064
                    tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
4065
                } else {                /* register */
4066
                    rs2 = GET_FIELD(insn, 27, 31);
4067
                    if (rs2) {
4068
                        gen_movl_reg_TN(rs2, cpu_src2);
4069
                        tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
4070
                    } else
4071
                        tcg_gen_mov_tl(cpu_dst, cpu_src1);
4072
                }
4073
                tcg_gen_helper_0_0(helper_restore);
4074
                gen_mov_pc_npc(dc, cpu_cond);
4075
                r_const = tcg_const_i32(3);
4076
                tcg_gen_helper_0_2(helper_check_align, cpu_dst, r_const);
4077
                tcg_temp_free(r_const);
4078
                tcg_gen_mov_tl(cpu_npc, cpu_dst);
4079
                dc->npc = DYNAMIC_PC;
4080
                goto jmp_insn;
4081
#endif
4082
            } else {
4083
                cpu_src1 = get_src1(insn, cpu_src1);
4084
                if (IS_IMM) {   /* immediate */
4085
                    rs2 = GET_FIELDs(insn, 19, 31);
4086
                    tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
4087
                } else {                /* register */
4088
                    rs2 = GET_FIELD(insn, 27, 31);
4089
                    if (rs2) {
4090
                        gen_movl_reg_TN(rs2, cpu_src2);
4091
                        tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
4092
                    } else
4093
                        tcg_gen_mov_tl(cpu_dst, cpu_src1);
4094
                }
4095
                switch (xop) {
4096
                case 0x38:      /* jmpl */
4097
                    {
4098
                        TCGv r_const;
4099

    
4100
                        r_const = tcg_const_tl(dc->pc);
4101
                        gen_movl_TN_reg(rd, r_const);
4102
                        tcg_temp_free(r_const);
4103
                        gen_mov_pc_npc(dc, cpu_cond);
4104
                        r_const = tcg_const_i32(3);
4105
                        tcg_gen_helper_0_2(helper_check_align, cpu_dst,
4106
                                           r_const);
4107
                        tcg_temp_free(r_const);
4108
                        tcg_gen_mov_tl(cpu_npc, cpu_dst);
4109
                        dc->npc = DYNAMIC_PC;
4110
                    }
4111
                    goto jmp_insn;
4112
#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
4113
                case 0x39:      /* rett, V9 return */
4114
                    {
4115
                        TCGv r_const;
4116

    
4117
                        if (!supervisor(dc))
4118
                            goto priv_insn;
4119
                        gen_mov_pc_npc(dc, cpu_cond);
4120
                        r_const = tcg_const_i32(3);
4121
                        tcg_gen_helper_0_2(helper_check_align, cpu_dst,
4122
                                           r_const);
4123
                        tcg_temp_free(r_const);
4124
                        tcg_gen_mov_tl(cpu_npc, cpu_dst);
4125
                        dc->npc = DYNAMIC_PC;
4126
                        tcg_gen_helper_0_0(helper_rett);
4127
                    }
4128
                    goto jmp_insn;
4129
#endif
4130
                case 0x3b: /* flush */
4131
                    if (!((dc)->features & CPU_FEATURE_FLUSH))
4132
                        goto unimp_flush;
4133
                    tcg_gen_helper_0_1(helper_flush, cpu_dst);
4134
                    break;
4135
                case 0x3c:      /* save */
4136
                    save_state(dc, cpu_cond);
4137
                    tcg_gen_helper_0_0(helper_save);
4138
                    gen_movl_TN_reg(rd, cpu_dst);
4139
                    break;
4140
                case 0x3d:      /* restore */
4141
                    save_state(dc, cpu_cond);
4142
                    tcg_gen_helper_0_0(helper_restore);
4143
                    gen_movl_TN_reg(rd, cpu_dst);
4144
                    break;
4145
#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
4146
                case 0x3e:      /* V9 done/retry */
4147
                    {
4148
                        switch (rd) {
4149
                        case 0:
4150
                            if (!supervisor(dc))
4151
                                goto priv_insn;
4152
                            dc->npc = DYNAMIC_PC;
4153
                            dc->pc = DYNAMIC_PC;
4154
                            tcg_gen_helper_0_0(helper_done);
4155
                            goto jmp_insn;
4156
                        case 1:
4157
                            if (!supervisor(dc))
4158
                                goto priv_insn;
4159
                            dc->npc = DYNAMIC_PC;
4160
                            dc->pc = DYNAMIC_PC;
4161
                            tcg_gen_helper_0_0(helper_retry);
4162
                            goto jmp_insn;
4163
                        default:
4164
                            goto illegal_insn;
4165
                        }
4166
                    }
4167
                    break;
4168
#endif
4169
                default:
4170
                    goto illegal_insn;
4171
                }
4172
            }
4173
            break;
4174
        }
4175
        break;
4176
    case 3:                     /* load/store instructions */
4177
        {
4178
            unsigned int xop = GET_FIELD(insn, 7, 12);
4179

    
4180
            cpu_src1 = get_src1(insn, cpu_src1);
4181
            if (xop == 0x3c || xop == 0x3e) { // V9 casa/casxa
4182
                rs2 = GET_FIELD(insn, 27, 31);
4183
                gen_movl_reg_TN(rs2, cpu_src2);
4184
                tcg_gen_mov_tl(cpu_addr, cpu_src1);
4185
            } else if (IS_IMM) {     /* immediate */
4186
                rs2 = GET_FIELDs(insn, 19, 31);
4187
                tcg_gen_addi_tl(cpu_addr, cpu_src1, (int)rs2);
4188
            } else {            /* register */
4189
                rs2 = GET_FIELD(insn, 27, 31);
4190
                if (rs2 != 0) {
4191
                    gen_movl_reg_TN(rs2, cpu_src2);
4192
                    tcg_gen_add_tl(cpu_addr, cpu_src1, cpu_src2);
4193
                } else
4194
                    tcg_gen_mov_tl(cpu_addr, cpu_src1);
4195
            }
4196
            if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
4197
                (xop > 0x17 && xop <= 0x1d ) ||
4198
                (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
4199
                switch (xop) {
4200
                case 0x0:       /* load unsigned word */
4201
                    ABI32_MASK(cpu_addr);
4202
                    tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx);
4203
                    break;
4204
                case 0x1:       /* load unsigned byte */
4205
                    ABI32_MASK(cpu_addr);
4206
                    tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx);
4207
                    break;
4208
                case 0x2:       /* load unsigned halfword */
4209
                    ABI32_MASK(cpu_addr);
4210
                    tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx);
4211
                    break;
4212
                case 0x3:       /* load double word */
4213
                    if (rd & 1)
4214
                        goto illegal_insn;
4215
                    else {
4216
                        TCGv r_const;
4217

    
4218
                        save_state(dc, cpu_cond);
4219
                        r_const = tcg_const_i32(7);
4220
                        tcg_gen_helper_0_2(helper_check_align, cpu_addr,
4221
                                           r_const); // XXX remove
4222
                        tcg_temp_free(r_const);
4223
                        ABI32_MASK(cpu_addr);
4224
                        tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx);
4225
                        tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64);
4226
                        tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffffULL);
4227
                        gen_movl_TN_reg(rd + 1, cpu_tmp0);
4228
                        tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
4229
                        tcg_gen_trunc_i64_tl(cpu_val, cpu_tmp64);
4230
                        tcg_gen_andi_tl(cpu_val, cpu_val, 0xffffffffULL);
4231
                    }
4232
                    break;
4233
                case 0x9:       /* load signed byte */
4234
                    ABI32_MASK(cpu_addr);
4235
                    tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4236
                    break;
4237
                case 0xa:       /* load signed halfword */
4238
                    ABI32_MASK(cpu_addr);
4239
                    tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx);
4240
                    break;
4241
                case 0xd:       /* ldstub -- XXX: should be atomically */
4242
                    {
4243
                        TCGv r_const;
4244

    
4245
                        ABI32_MASK(cpu_addr);
4246
                        tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4247
                        r_const = tcg_const_tl(0xff);
4248
                        tcg_gen_qemu_st8(r_const, cpu_addr, dc->mem_idx);
4249
                        tcg_temp_free(r_const);
4250
                    }
4251
                    break;
4252
                case 0x0f:      /* swap register with memory. Also
4253
                                   atomically */
4254
                    CHECK_IU_FEATURE(dc, SWAP);
4255
                    gen_movl_reg_TN(rd, cpu_val);
4256
                    ABI32_MASK(cpu_addr);
4257
                    tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4258
                    tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
4259
                    tcg_gen_extu_i32_tl(cpu_val, cpu_tmp32);
4260
                    break;
4261
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4262
                case 0x10:      /* load word alternate */
4263
#ifndef TARGET_SPARC64
4264
                    if (IS_IMM)
4265
                        goto illegal_insn;
4266
                    if (!supervisor(dc))
4267
                        goto priv_insn;
4268
#endif
4269
                    save_state(dc, cpu_cond);
4270
                    gen_ld_asi(cpu_val, cpu_addr, insn, 4, 0);
4271
                    break;
4272
                case 0x11:      /* load unsigned byte alternate */
4273
#ifndef TARGET_SPARC64
4274
                    if (IS_IMM)
4275
                        goto illegal_insn;
4276
                    if (!supervisor(dc))
4277
                        goto priv_insn;
4278
#endif
4279
                    save_state(dc, cpu_cond);
4280
                    gen_ld_asi(cpu_val, cpu_addr, insn, 1, 0);
4281
                    break;
4282
                case 0x12:      /* load unsigned halfword alternate */
4283
#ifndef TARGET_SPARC64
4284
                    if (IS_IMM)
4285
                        goto illegal_insn;
4286
                    if (!supervisor(dc))
4287
                        goto priv_insn;
4288
#endif
4289
                    save_state(dc, cpu_cond);
4290
                    gen_ld_asi(cpu_val, cpu_addr, insn, 2, 0);
4291
                    break;
4292
                case 0x13:      /* load double word alternate */
4293
#ifndef TARGET_SPARC64
4294
                    if (IS_IMM)
4295
                        goto illegal_insn;
4296
                    if (!supervisor(dc))
4297
                        goto priv_insn;
4298
#endif
4299
                    if (rd & 1)
4300
                        goto illegal_insn;
4301
                    save_state(dc, cpu_cond);
4302
                    gen_ldda_asi(cpu_tmp0, cpu_val, cpu_addr, insn);
4303
                    gen_movl_TN_reg(rd + 1, cpu_tmp0);
4304
                    break;
4305
                case 0x19:      /* load signed byte alternate */
4306
#ifndef TARGET_SPARC64
4307
                    if (IS_IMM)
4308
                        goto illegal_insn;
4309
                    if (!supervisor(dc))
4310
                        goto priv_insn;
4311
#endif
4312
                    save_state(dc, cpu_cond);
4313
                    gen_ld_asi(cpu_val, cpu_addr, insn, 1, 1);
4314
                    break;
4315
                case 0x1a:      /* load signed halfword alternate */
4316
#ifndef TARGET_SPARC64
4317
                    if (IS_IMM)
4318
                        goto illegal_insn;
4319
                    if (!supervisor(dc))
4320
                        goto priv_insn;
4321
#endif
4322
                    save_state(dc, cpu_cond);
4323
                    gen_ld_asi(cpu_val, cpu_addr, insn, 2, 1);
4324
                    break;
4325
                case 0x1d:      /* ldstuba -- XXX: should be atomically */
4326
#ifndef TARGET_SPARC64
4327
                    if (IS_IMM)
4328
                        goto illegal_insn;
4329
                    if (!supervisor(dc))
4330
                        goto priv_insn;
4331
#endif
4332
                    save_state(dc, cpu_cond);
4333
                    gen_ldstub_asi(cpu_val, cpu_addr, insn);
4334
                    break;
4335
                case 0x1f:      /* swap reg with alt. memory. Also
4336
                                   atomically */
4337
                    CHECK_IU_FEATURE(dc, SWAP);
4338
#ifndef TARGET_SPARC64
4339
                    if (IS_IMM)
4340
                        goto illegal_insn;
4341
                    if (!supervisor(dc))
4342
                        goto priv_insn;
4343
#endif
4344
                    save_state(dc, cpu_cond);
4345
                    gen_movl_reg_TN(rd, cpu_val);
4346
                    gen_swap_asi(cpu_val, cpu_addr, insn);
4347
                    break;
4348

    
4349
#ifndef TARGET_SPARC64
4350
                case 0x30: /* ldc */
4351
                case 0x31: /* ldcsr */
4352
                case 0x33: /* lddc */
4353
                    goto ncp_insn;
4354
#endif
4355
#endif
4356
#ifdef TARGET_SPARC64
4357
                case 0x08: /* V9 ldsw */
4358
                    ABI32_MASK(cpu_addr);
4359
                    tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx);
4360
                    break;
4361
                case 0x0b: /* V9 ldx */
4362
                    ABI32_MASK(cpu_addr);
4363
                    tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx);
4364
                    break;
4365
                case 0x18: /* V9 ldswa */
4366
                    save_state(dc, cpu_cond);
4367
                    gen_ld_asi(cpu_val, cpu_addr, insn, 4, 1);
4368
                    break;
4369
                case 0x1b: /* V9 ldxa */
4370
                    save_state(dc, cpu_cond);
4371
                    gen_ld_asi(cpu_val, cpu_addr, insn, 8, 0);
4372
                    break;
4373
                case 0x2d: /* V9 prefetch, no effect */
4374
                    goto skip_move;
4375
                case 0x30: /* V9 ldfa */
4376
                    save_state(dc, cpu_cond);
4377
                    gen_ldf_asi(cpu_addr, insn, 4, rd);
4378
                    goto skip_move;
4379
                case 0x33: /* V9 lddfa */
4380
                    save_state(dc, cpu_cond);
4381
                    gen_ldf_asi(cpu_addr, insn, 8, DFPREG(rd));
4382
                    goto skip_move;
4383
                case 0x3d: /* V9 prefetcha, no effect */
4384
                    goto skip_move;
4385
                case 0x32: /* V9 ldqfa */
4386
                    CHECK_FPU_FEATURE(dc, FLOAT128);
4387
                    save_state(dc, cpu_cond);
4388
                    gen_ldf_asi(cpu_addr, insn, 16, QFPREG(rd));
4389
                    goto skip_move;
4390
#endif
4391
                default:
4392
                    goto illegal_insn;
4393
                }
4394
                gen_movl_TN_reg(rd, cpu_val);
4395
#ifdef TARGET_SPARC64
4396
            skip_move: ;
4397
#endif
4398
            } else if (xop >= 0x20 && xop < 0x24) {
4399
                if (gen_trap_ifnofpu(dc, cpu_cond))
4400
                    goto jmp_insn;
4401
                save_state(dc, cpu_cond);
4402
                switch (xop) {
4403
                case 0x20:      /* load fpreg */
4404
                    ABI32_MASK(cpu_addr);
4405
                    tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4406
                    tcg_gen_st_i32(cpu_tmp32, cpu_env,
4407
                                   offsetof(CPUState, fpr[rd]));
4408
                    break;
4409
                case 0x21:      /* load fsr */
4410
                    ABI32_MASK(cpu_addr);
4411
                    tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4412
                    tcg_gen_st_i32(cpu_tmp32, cpu_env,
4413
                                   offsetof(CPUState, ft0));
4414
                    tcg_gen_helper_0_0(helper_ldfsr);
4415
                    break;
4416
                case 0x22:      /* load quad fpreg */
4417
                    {
4418
                        TCGv r_const;
4419

    
4420
                        CHECK_FPU_FEATURE(dc, FLOAT128);
4421
                        r_const = tcg_const_i32(dc->mem_idx);
4422
                        tcg_gen_helper_0_2(helper_ldqf, cpu_addr, r_const);
4423
                        tcg_temp_free(r_const);
4424
                        gen_op_store_QT0_fpr(QFPREG(rd));
4425
                    }
4426
                    break;
4427
                case 0x23:      /* load double fpreg */
4428
                    {
4429
                        TCGv r_const;
4430

    
4431
                        r_const = tcg_const_i32(dc->mem_idx);
4432
                        tcg_gen_helper_0_2(helper_lddf, cpu_addr, r_const);
4433
                        tcg_temp_free(r_const);
4434
                        gen_op_store_DT0_fpr(DFPREG(rd));
4435
                    }
4436
                    break;
4437
                default:
4438
                    goto illegal_insn;
4439
                }
4440
            } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
4441
                       xop == 0xe || xop == 0x1e) {
4442
                gen_movl_reg_TN(rd, cpu_val);
4443
                switch (xop) {
4444
                case 0x4: /* store word */
4445
                    ABI32_MASK(cpu_addr);
4446
                    tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
4447
                    break;
4448
                case 0x5: /* store byte */
4449
                    ABI32_MASK(cpu_addr);
4450
                    tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx);
4451
                    break;
4452
                case 0x6: /* store halfword */
4453
                    ABI32_MASK(cpu_addr);
4454
                    tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx);
4455
                    break;
4456
                case 0x7: /* store double word */
4457
                    if (rd & 1)
4458
                        goto illegal_insn;
4459
                    else {
4460
                        TCGv r_low, r_const;
4461

    
4462
                        save_state(dc, cpu_cond);
4463
                        ABI32_MASK(cpu_addr);
4464
                        r_const = tcg_const_i32(7);
4465
                        tcg_gen_helper_0_2(helper_check_align, cpu_addr,
4466
                                           r_const); // XXX remove
4467
                        tcg_temp_free(r_const);
4468
                        r_low = tcg_temp_new(TCG_TYPE_TL);
4469
                        gen_movl_reg_TN(rd + 1, r_low);
4470
                        tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, cpu_val,
4471
                                           r_low);
4472
                        tcg_temp_free(r_low);
4473
                        tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx);
4474
                    }
4475
                    break;
4476
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4477
                case 0x14: /* store word alternate */
4478
#ifndef TARGET_SPARC64
4479
                    if (IS_IMM)
4480
                        goto illegal_insn;
4481
                    if (!supervisor(dc))
4482
                        goto priv_insn;
4483
#endif
4484
                    save_state(dc, cpu_cond);
4485
                    gen_st_asi(cpu_val, cpu_addr, insn, 4);
4486
                    break;
4487
                case 0x15: /* store byte alternate */
4488
#ifndef TARGET_SPARC64
4489
                    if (IS_IMM)
4490
                        goto illegal_insn;
4491
                    if (!supervisor(dc))
4492
                        goto priv_insn;
4493
#endif
4494
                    save_state(dc, cpu_cond);
4495
                    gen_st_asi(cpu_val, cpu_addr, insn, 1);
4496
                    break;
4497
                case 0x16: /* store halfword alternate */
4498
#ifndef TARGET_SPARC64
4499
                    if (IS_IMM)
4500
                        goto illegal_insn;
4501
                    if (!supervisor(dc))
4502
                        goto priv_insn;
4503
#endif
4504
                    save_state(dc, cpu_cond);
4505
                    gen_st_asi(cpu_val, cpu_addr, insn, 2);
4506
                    break;
4507
                case 0x17: /* store double word alternate */
4508
#ifndef TARGET_SPARC64
4509
                    if (IS_IMM)
4510
                        goto illegal_insn;
4511
                    if (!supervisor(dc))
4512
                        goto priv_insn;
4513
#endif
4514
                    if (rd & 1)
4515
                        goto illegal_insn;
4516
                    else {
4517
                        save_state(dc, cpu_cond);
4518
                        gen_stda_asi(cpu_val, cpu_addr, insn, rd);
4519
                    }
4520
                    break;
4521
#endif
4522
#ifdef TARGET_SPARC64
4523
                case 0x0e: /* V9 stx */
4524
                    ABI32_MASK(cpu_addr);
4525
                    tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx);
4526
                    break;
4527
                case 0x1e: /* V9 stxa */
4528
                    save_state(dc, cpu_cond);
4529
                    gen_st_asi(cpu_val, cpu_addr, insn, 8);
4530
                    break;
4531
#endif
4532
                default:
4533
                    goto illegal_insn;
4534
                }
4535
            } else if (xop > 0x23 && xop < 0x28) {
4536
                if (gen_trap_ifnofpu(dc, cpu_cond))
4537
                    goto jmp_insn;
4538
                save_state(dc, cpu_cond);
4539
                switch (xop) {
4540
                case 0x24: /* store fpreg */
4541
                    ABI32_MASK(cpu_addr);
4542
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
4543
                                   offsetof(CPUState, fpr[rd]));
4544
                    tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
4545
                    break;
4546
                case 0x25: /* stfsr, V9 stxfsr */
4547
                    ABI32_MASK(cpu_addr);
4548
                    tcg_gen_helper_0_0(helper_stfsr);
4549
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
4550
                                   offsetof(CPUState, ft0));
4551
                    tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
4552
                    break;
4553
                case 0x26:
4554
#ifdef TARGET_SPARC64
4555
                    /* V9 stqf, store quad fpreg */
4556
                    {
4557
                        TCGv r_const;
4558

    
4559
                        CHECK_FPU_FEATURE(dc, FLOAT128);
4560
                        gen_op_load_fpr_QT0(QFPREG(rd));
4561
                        r_const = tcg_const_i32(dc->mem_idx);
4562
                        tcg_gen_helper_0_2(helper_stqf, cpu_addr, r_const);
4563
                        tcg_temp_free(r_const);
4564
                    }
4565
                    break;
4566
#else /* !TARGET_SPARC64 */
4567
                    /* stdfq, store floating point queue */
4568
#if defined(CONFIG_USER_ONLY)
4569
                    goto illegal_insn;
4570
#else
4571
                    if (!supervisor(dc))
4572
                        goto priv_insn;
4573
                    if (gen_trap_ifnofpu(dc, cpu_cond))
4574
                        goto jmp_insn;
4575
                    goto nfq_insn;
4576
#endif
4577
#endif
4578
                case 0x27: /* store double fpreg */
4579
                    {
4580
                        TCGv r_const;
4581

    
4582
                        gen_op_load_fpr_DT0(DFPREG(rd));
4583
                        r_const = tcg_const_i32(dc->mem_idx);
4584
                        tcg_gen_helper_0_2(helper_stdf, cpu_addr, r_const);
4585
                        tcg_temp_free(r_const);
4586
                    }
4587
                    break;
4588
                default:
4589
                    goto illegal_insn;
4590
                }
4591
            } else if (xop > 0x33 && xop < 0x3f) {
4592
                save_state(dc, cpu_cond);
4593
                switch (xop) {
4594
#ifdef TARGET_SPARC64
4595
                case 0x34: /* V9 stfa */
4596
                    gen_op_load_fpr_FT0(rd);
4597
                    gen_stf_asi(cpu_addr, insn, 4, rd);
4598
                    break;
4599
                case 0x36: /* V9 stqfa */
4600
                    {
4601
                        TCGv r_const;
4602

    
4603
                        CHECK_FPU_FEATURE(dc, FLOAT128);
4604
                        r_const = tcg_const_i32(7);
4605
                        tcg_gen_helper_0_2(helper_check_align, cpu_addr,
4606
                                           r_const);
4607
                        tcg_temp_free(r_const);
4608
                        gen_op_load_fpr_QT0(QFPREG(rd));
4609
                        gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd));
4610
                    }
4611
                    break;
4612
                case 0x37: /* V9 stdfa */
4613
                    gen_op_load_fpr_DT0(DFPREG(rd));
4614
                    gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd));
4615
                    break;
4616
                case 0x3c: /* V9 casa */
4617
                    gen_cas_asi(cpu_val, cpu_addr, cpu_src2, insn, rd);
4618
                    gen_movl_TN_reg(rd, cpu_val);
4619
                    break;
4620
                case 0x3e: /* V9 casxa */
4621
                    gen_casx_asi(cpu_val, cpu_addr, cpu_src2, insn, rd);
4622
                    gen_movl_TN_reg(rd, cpu_val);
4623
                    break;
4624
#else
4625
                case 0x34: /* stc */
4626
                case 0x35: /* stcsr */
4627
                case 0x36: /* stdcq */
4628
                case 0x37: /* stdc */
4629
                    goto ncp_insn;
4630
#endif
4631
                default:
4632
                    goto illegal_insn;
4633
                }
4634
            }
4635
            else
4636
                goto illegal_insn;
4637
        }
4638
        break;
4639
    }
4640
    /* default case for non jump instructions */
4641
    if (dc->npc == DYNAMIC_PC) {
4642
        dc->pc = DYNAMIC_PC;
4643
        gen_op_next_insn();
4644
    } else if (dc->npc == JUMP_PC) {
4645
        /* we can do a static jump */
4646
        gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond);
4647
        dc->is_br = 1;
4648
    } else {
4649
        dc->pc = dc->npc;
4650
        dc->npc = dc->npc + 4;
4651
    }
4652
 jmp_insn:
4653
    return;
4654
 illegal_insn:
4655
    {
4656
        TCGv r_const;
4657

    
4658
        save_state(dc, cpu_cond);
4659
        r_const = tcg_const_i32(TT_ILL_INSN);
4660
        tcg_gen_helper_0_1(raise_exception, r_const);
4661
        tcg_temp_free(r_const);
4662
        dc->is_br = 1;
4663
    }
4664
    return;
4665
 unimp_flush:
4666
    {
4667
        TCGv r_const;
4668

    
4669
        save_state(dc, cpu_cond);
4670
        r_const = tcg_const_i32(TT_UNIMP_FLUSH);
4671
        tcg_gen_helper_0_1(raise_exception, r_const);
4672
        tcg_temp_free(r_const);
4673
        dc->is_br = 1;
4674
    }
4675
    return;
4676
#if !defined(CONFIG_USER_ONLY)
4677
 priv_insn:
4678
    {
4679
        TCGv r_const;
4680

    
4681
        save_state(dc, cpu_cond);
4682
        r_const = tcg_const_i32(TT_PRIV_INSN);
4683
        tcg_gen_helper_0_1(raise_exception, r_const);
4684
        tcg_temp_free(r_const);
4685
        dc->is_br = 1;
4686
    }
4687
    return;
4688
#endif
4689
 nfpu_insn:
4690
    save_state(dc, cpu_cond);
4691
    gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
4692
    dc->is_br = 1;
4693
    return;
4694
#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
4695
 nfq_insn:
4696
    save_state(dc, cpu_cond);
4697
    gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
4698
    dc->is_br = 1;
4699
    return;
4700
#endif
4701
#ifndef TARGET_SPARC64
4702
 ncp_insn:
4703
    {
4704
        TCGv r_const;
4705

    
4706
        save_state(dc, cpu_cond);
4707
        r_const = tcg_const_i32(TT_NCP_INSN);
4708
        tcg_gen_helper_0_1(raise_exception, r_const);
4709
        tcg_temp_free(r_const);
4710
        dc->is_br = 1;
4711
    }
4712
    return;
4713
#endif
4714
}
4715

    
4716
static inline int gen_intermediate_code_internal(TranslationBlock * tb,
4717
                                                 int spc, CPUSPARCState *env)
4718
{
4719
    target_ulong pc_start, last_pc;
4720
    uint16_t *gen_opc_end;
4721
    DisasContext dc1, *dc = &dc1;
4722
    int j, lj = -1;
4723
    int num_insns;
4724
    int max_insns;
4725

    
4726
    memset(dc, 0, sizeof(DisasContext));
4727
    dc->tb = tb;
4728
    pc_start = tb->pc;
4729
    dc->pc = pc_start;
4730
    last_pc = dc->pc;
4731
    dc->npc = (target_ulong) tb->cs_base;
4732
    dc->mem_idx = cpu_mmu_index(env);
4733
    dc->features = env->features;
4734
    if ((dc->features & CPU_FEATURE_FLOAT)) {
4735
        dc->fpu_enabled = cpu_fpu_enabled(env);
4736
#if defined(CONFIG_USER_ONLY)
4737
        dc->features |= CPU_FEATURE_FLOAT128;
4738
#endif
4739
    } else
4740
        dc->fpu_enabled = 0;
4741
    gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
4742

    
4743
    cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL);
4744
    cpu_tmp32 = tcg_temp_new(TCG_TYPE_I32);
4745
    cpu_tmp64 = tcg_temp_new(TCG_TYPE_I64);
4746

    
4747
    cpu_dst = tcg_temp_local_new(TCG_TYPE_TL);
4748

    
4749
    // loads and stores
4750
    cpu_val = tcg_temp_local_new(TCG_TYPE_TL);
4751
    cpu_addr = tcg_temp_local_new(TCG_TYPE_TL);
4752

    
4753
    num_insns = 0;
4754
    max_insns = tb->cflags & CF_COUNT_MASK;
4755
    if (max_insns == 0)
4756
        max_insns = CF_COUNT_MASK;
4757
    gen_icount_start();
4758
    do {
4759
        if (env->nb_breakpoints > 0) {
4760
            for(j = 0; j < env->nb_breakpoints; j++) {
4761
                if (env->breakpoints[j] == dc->pc) {
4762
                    if (dc->pc != pc_start)
4763
                        save_state(dc, cpu_cond);
4764
                    tcg_gen_helper_0_0(helper_debug);
4765
                    tcg_gen_exit_tb(0);
4766
                    dc->is_br = 1;
4767
                    goto exit_gen_loop;
4768
                }
4769
            }
4770
        }
4771
        if (spc) {
4772
            if (loglevel > 0)
4773
                fprintf(logfile, "Search PC...\n");
4774
            j = gen_opc_ptr - gen_opc_buf;
4775
            if (lj < j) {
4776
                lj++;
4777
                while (lj < j)
4778
                    gen_opc_instr_start[lj++] = 0;
4779
                gen_opc_pc[lj] = dc->pc;
4780
                gen_opc_npc[lj] = dc->npc;
4781
                gen_opc_instr_start[lj] = 1;
4782
                gen_opc_icount[lj] = num_insns;
4783
            }
4784
        }
4785
        if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
4786
            gen_io_start();
4787
        last_pc = dc->pc;
4788
        disas_sparc_insn(dc);
4789
        num_insns++;
4790

    
4791
        if (dc->is_br)
4792
            break;
4793
        /* if the next PC is different, we abort now */
4794
        if (dc->pc != (last_pc + 4))
4795
            break;
4796
        /* if we reach a page boundary, we stop generation so that the
4797
           PC of a TT_TFAULT exception is always in the right page */
4798
        if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
4799
            break;
4800
        /* if single step mode, we generate only one instruction and
4801
           generate an exception */
4802
        if (env->singlestep_enabled) {
4803
            tcg_gen_movi_tl(cpu_pc, dc->pc);
4804
            tcg_gen_exit_tb(0);
4805
            break;
4806
        }
4807
    } while ((gen_opc_ptr < gen_opc_end) &&
4808
             (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32) &&
4809
             num_insns < max_insns);
4810

    
4811
 exit_gen_loop:
4812
    tcg_temp_free(cpu_addr);
4813
    tcg_temp_free(cpu_val);
4814
    tcg_temp_free(cpu_dst);
4815
    tcg_temp_free(cpu_tmp64);
4816
    tcg_temp_free(cpu_tmp32);
4817
    tcg_temp_free(cpu_tmp0);
4818
    if (tb->cflags & CF_LAST_IO)
4819
        gen_io_end();
4820
    if (!dc->is_br) {
4821
        if (dc->pc != DYNAMIC_PC &&
4822
            (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
4823
            /* static PC and NPC: we can use direct chaining */
4824
            gen_goto_tb(dc, 0, dc->pc, dc->npc);
4825
        } else {
4826
            if (dc->pc != DYNAMIC_PC)
4827
                tcg_gen_movi_tl(cpu_pc, dc->pc);
4828
            save_npc(dc, cpu_cond);
4829
            tcg_gen_exit_tb(0);
4830
        }
4831
    }
4832
    gen_icount_end(tb, num_insns);
4833
    *gen_opc_ptr = INDEX_op_end;
4834
    if (spc) {
4835
        j = gen_opc_ptr - gen_opc_buf;
4836
        lj++;
4837
        while (lj <= j)
4838
            gen_opc_instr_start[lj++] = 0;
4839
#if 0
4840
        if (loglevel > 0) {
4841
            page_dump(logfile);
4842
        }
4843
#endif
4844
        gen_opc_jump_pc[0] = dc->jump_pc[0];
4845
        gen_opc_jump_pc[1] = dc->jump_pc[1];
4846
    } else {
4847
        tb->size = last_pc + 4 - pc_start;
4848
        tb->icount = num_insns;
4849
    }
4850
#ifdef DEBUG_DISAS
4851
    if (loglevel & CPU_LOG_TB_IN_ASM) {
4852
        fprintf(logfile, "--------------\n");
4853
        fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
4854
        target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
4855
        fprintf(logfile, "\n");
4856
    }
4857
#endif
4858
    return 0;
4859
}
4860

    
4861
int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
4862
{
4863
    return gen_intermediate_code_internal(tb, 0, env);
4864
}
4865

    
4866
int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
4867
{
4868
    return gen_intermediate_code_internal(tb, 1, env);
4869
}
4870

    
4871
void gen_intermediate_code_init(CPUSPARCState *env)
4872
{
4873
    unsigned int i;
4874
    static int inited;
4875
    static const char * const gregnames[8] = {
4876
        NULL, // g0 not used
4877
        "g1",
4878
        "g2",
4879
        "g3",
4880
        "g4",
4881
        "g5",
4882
        "g6",
4883
        "g7",
4884
    };
4885

    
4886
    /* init various static tables */
4887
    if (!inited) {
4888
        inited = 1;
4889

    
4890
        cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
4891
        cpu_regwptr = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
4892
                                         offsetof(CPUState, regwptr),
4893
                                         "regwptr");
4894
#ifdef TARGET_SPARC64
4895
        cpu_xcc = tcg_global_mem_new(TCG_TYPE_I32,
4896
                                     TCG_AREG0, offsetof(CPUState, xcc),
4897
                                     "xcc");
4898
#endif
4899
        cpu_cond = tcg_global_mem_new(TCG_TYPE_TL,
4900
                                      TCG_AREG0, offsetof(CPUState, cond),
4901
                                      "cond");
4902
        cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL,
4903
                                        TCG_AREG0, offsetof(CPUState, cc_src),
4