root / target-ppc / helper.c @ 71be0fc3
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1 | 79aceca5 | bellard | /*
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2 | 79aceca5 | bellard | * PPC emulation helpers for qemu.
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3 | 79aceca5 | bellard | *
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4 | 79aceca5 | bellard | * Copyright (c) 2003 Jocelyn Mayer
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5 | 79aceca5 | bellard | *
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6 | 79aceca5 | bellard | * This library is free software; you can redistribute it and/or
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7 | 79aceca5 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 79aceca5 | bellard | * License as published by the Free Software Foundation; either
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9 | 79aceca5 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 79aceca5 | bellard | *
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11 | 79aceca5 | bellard | * This library is distributed in the hope that it will be useful,
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12 | 79aceca5 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 79aceca5 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 79aceca5 | bellard | * Lesser General Public License for more details.
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15 | 79aceca5 | bellard | *
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16 | 79aceca5 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 79aceca5 | bellard | * License along with this library; if not, write to the Free Software
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18 | 79aceca5 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 79aceca5 | bellard | */
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20 | 79aceca5 | bellard | #include "exec.h" |
21 | 9a64fbe4 | bellard | |
22 | 9a64fbe4 | bellard | //#define DEBUG_MMU
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23 | 9a64fbe4 | bellard | //#define DEBUG_BATS
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24 | 9a64fbe4 | bellard | //#define DEBUG_EXCEPTIONS
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25 | d094807b | bellard | /* accurate but slower TLB flush in exceptions */
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26 | d094807b | bellard | //#define ACCURATE_TLB_FLUSH
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27 | 9a64fbe4 | bellard | |
28 | 9a64fbe4 | bellard | /*****************************************************************************/
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29 | 9a64fbe4 | bellard | /* PPC MMU emulation */
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30 | a541f297 | bellard | |
31 | 9a64fbe4 | bellard | /* Perform BAT hit & translation */
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32 | 9a64fbe4 | bellard | static int get_bat (CPUState *env, uint32_t *real, int *prot, |
33 | 9a64fbe4 | bellard | uint32_t virtual, int rw, int type) |
34 | 9a64fbe4 | bellard | { |
35 | 9a64fbe4 | bellard | uint32_t *BATlt, *BATut, *BATu, *BATl; |
36 | 9a64fbe4 | bellard | uint32_t base, BEPIl, BEPIu, bl; |
37 | 9a64fbe4 | bellard | int i;
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38 | 9a64fbe4 | bellard | int ret = -1; |
39 | 9a64fbe4 | bellard | |
40 | 9a64fbe4 | bellard | #if defined (DEBUG_BATS)
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41 | 9a64fbe4 | bellard | if (loglevel > 0) { |
42 | 9a64fbe4 | bellard | fprintf(logfile, "%s: %cBAT v 0x%08x\n", __func__,
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43 | 9a64fbe4 | bellard | type == ACCESS_CODE ? 'I' : 'D', virtual); |
44 | 9a64fbe4 | bellard | } |
45 | 9a64fbe4 | bellard | #endif
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46 | 9a64fbe4 | bellard | switch (type) {
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47 | 9a64fbe4 | bellard | case ACCESS_CODE:
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48 | 9a64fbe4 | bellard | BATlt = env->IBAT[1];
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49 | 9a64fbe4 | bellard | BATut = env->IBAT[0];
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50 | 9a64fbe4 | bellard | break;
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51 | 9a64fbe4 | bellard | default:
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52 | 9a64fbe4 | bellard | BATlt = env->DBAT[1];
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53 | 9a64fbe4 | bellard | BATut = env->DBAT[0];
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54 | 9a64fbe4 | bellard | break;
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55 | 9a64fbe4 | bellard | } |
56 | 9a64fbe4 | bellard | #if defined (DEBUG_BATS)
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57 | 9a64fbe4 | bellard | if (loglevel > 0) { |
58 | 9a64fbe4 | bellard | fprintf(logfile, "%s...: %cBAT v 0x%08x\n", __func__,
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59 | 9a64fbe4 | bellard | type == ACCESS_CODE ? 'I' : 'D', virtual); |
60 | 9a64fbe4 | bellard | } |
61 | 9a64fbe4 | bellard | #endif
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62 | 9a64fbe4 | bellard | base = virtual & 0xFFFC0000;
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63 | 9a64fbe4 | bellard | for (i = 0; i < 4; i++) { |
64 | 9a64fbe4 | bellard | BATu = &BATut[i]; |
65 | 9a64fbe4 | bellard | BATl = &BATlt[i]; |
66 | 9a64fbe4 | bellard | BEPIu = *BATu & 0xF0000000;
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67 | 9a64fbe4 | bellard | BEPIl = *BATu & 0x0FFE0000;
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68 | 9a64fbe4 | bellard | bl = (*BATu & 0x00001FFC) << 15; |
69 | 9a64fbe4 | bellard | #if defined (DEBUG_BATS)
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70 | 9a64fbe4 | bellard | if (loglevel > 0) { |
71 | 9a64fbe4 | bellard | fprintf(logfile, "%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x\n",
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72 | 9a64fbe4 | bellard | __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual, |
73 | 9a64fbe4 | bellard | *BATu, *BATl); |
74 | 9a64fbe4 | bellard | } |
75 | 9a64fbe4 | bellard | #endif
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76 | 9a64fbe4 | bellard | if ((virtual & 0xF0000000) == BEPIu && |
77 | 9a64fbe4 | bellard | ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
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78 | 9a64fbe4 | bellard | /* BAT matches */
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79 | 9a64fbe4 | bellard | if ((msr_pr == 0 && (*BATu & 0x00000002)) || |
80 | 9a64fbe4 | bellard | (msr_pr == 1 && (*BATu & 0x00000001))) { |
81 | 9a64fbe4 | bellard | /* Get physical address */
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82 | 9a64fbe4 | bellard | *real = (*BATl & 0xF0000000) |
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83 | 9a64fbe4 | bellard | ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) | |
84 | a541f297 | bellard | (virtual & 0x0001F000);
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85 | 9a64fbe4 | bellard | if (*BATl & 0x00000001) |
86 | 5f21aef2 | bellard | *prot = PAGE_READ; |
87 | 9a64fbe4 | bellard | if (*BATl & 0x00000002) |
88 | 5f21aef2 | bellard | *prot = PAGE_WRITE | PAGE_READ; |
89 | 9a64fbe4 | bellard | #if defined (DEBUG_BATS)
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90 | 9a64fbe4 | bellard | if (loglevel > 0) { |
91 | 9a64fbe4 | bellard | fprintf(logfile, "BAT %d match: r 0x%08x prot=%c%c\n",
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92 | 5f21aef2 | bellard | i, *real, *prot & PAGE_READ ? 'R' : '-', |
93 | 5f21aef2 | bellard | *prot & PAGE_WRITE ? 'W' : '-'); |
94 | 9a64fbe4 | bellard | } |
95 | 9a64fbe4 | bellard | #endif
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96 | 9a64fbe4 | bellard | ret = 0;
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97 | 9a64fbe4 | bellard | break;
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98 | 9a64fbe4 | bellard | } |
99 | 9a64fbe4 | bellard | } |
100 | 9a64fbe4 | bellard | } |
101 | 9a64fbe4 | bellard | if (ret < 0) { |
102 | 9a64fbe4 | bellard | #if defined (DEBUG_BATS)
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103 | 9a64fbe4 | bellard | printf("no BAT match for 0x%08x:\n", virtual);
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104 | 9a64fbe4 | bellard | for (i = 0; i < 4; i++) { |
105 | 9a64fbe4 | bellard | BATu = &BATut[i]; |
106 | 9a64fbe4 | bellard | BATl = &BATlt[i]; |
107 | 9a64fbe4 | bellard | BEPIu = *BATu & 0xF0000000;
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108 | 9a64fbe4 | bellard | BEPIl = *BATu & 0x0FFE0000;
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109 | 9a64fbe4 | bellard | bl = (*BATu & 0x00001FFC) << 15; |
110 | 9a64fbe4 | bellard | printf("%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x \n\t"
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111 | 9a64fbe4 | bellard | "0x%08x 0x%08x 0x%08x\n",
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112 | 9a64fbe4 | bellard | __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual, |
113 | 9a64fbe4 | bellard | *BATu, *BATl, BEPIu, BEPIl, bl); |
114 | 9a64fbe4 | bellard | } |
115 | 9a64fbe4 | bellard | #endif
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116 | 9a64fbe4 | bellard | } |
117 | 9a64fbe4 | bellard | /* No hit */
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118 | 9a64fbe4 | bellard | return ret;
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119 | 9a64fbe4 | bellard | } |
120 | 9a64fbe4 | bellard | |
121 | 9a64fbe4 | bellard | /* PTE table lookup */
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122 | 9a64fbe4 | bellard | static int find_pte (uint32_t *RPN, int *prot, uint32_t base, uint32_t va, |
123 | 9a64fbe4 | bellard | int h, int key, int rw) |
124 | 9a64fbe4 | bellard | { |
125 | a541f297 | bellard | uint32_t pte0, pte1, keep = 0, access = 0; |
126 | 9a64fbe4 | bellard | int i, good = -1, store = 0; |
127 | 9a64fbe4 | bellard | int ret = -1; /* No entry found */ |
128 | 9a64fbe4 | bellard | |
129 | 9a64fbe4 | bellard | for (i = 0; i < 8; i++) { |
130 | 8df1cd07 | bellard | pte0 = ldl_phys(base + (i * 8));
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131 | 8df1cd07 | bellard | pte1 = ldl_phys(base + (i * 8) + 4); |
132 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
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133 | d094807b | bellard | if (loglevel > 0) { |
134 | a541f297 | bellard | fprintf(logfile, "Load pte from 0x%08x => 0x%08x 0x%08x "
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135 | a541f297 | bellard | "%d %d %d 0x%08x\n", base + (i * 8), pte0, pte1, |
136 | a541f297 | bellard | pte0 >> 31, h, (pte0 >> 6) & 1, va); |
137 | a541f297 | bellard | } |
138 | 9a64fbe4 | bellard | #endif
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139 | 9a64fbe4 | bellard | /* Check validity and table match */
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140 | 9a64fbe4 | bellard | if (pte0 & 0x80000000 && (h == ((pte0 >> 6) & 1))) { |
141 | 9a64fbe4 | bellard | /* Check vsid & api */
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142 | 9a64fbe4 | bellard | if ((pte0 & 0x7FFFFFBF) == va) { |
143 | 9a64fbe4 | bellard | if (good == -1) { |
144 | 9a64fbe4 | bellard | good = i; |
145 | 9a64fbe4 | bellard | keep = pte1; |
146 | 9a64fbe4 | bellard | } else {
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147 | 9a64fbe4 | bellard | /* All matches should have equal RPN, WIMG & PP */
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148 | 9a64fbe4 | bellard | if ((keep & 0xFFFFF07B) != (pte1 & 0xFFFFF07B)) { |
149 | a541f297 | bellard | if (loglevel > 0) |
150 | a541f297 | bellard | fprintf(logfile, "Bad RPN/WIMG/PP\n");
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151 | 9a64fbe4 | bellard | return -1; |
152 | 9a64fbe4 | bellard | } |
153 | 9a64fbe4 | bellard | } |
154 | 9a64fbe4 | bellard | /* Check access rights */
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155 | 9a64fbe4 | bellard | if (key == 0) { |
156 | 5f21aef2 | bellard | access = PAGE_READ; |
157 | 9a64fbe4 | bellard | if ((pte1 & 0x00000003) != 0x3) |
158 | 5f21aef2 | bellard | access |= PAGE_WRITE; |
159 | 9a64fbe4 | bellard | } else {
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160 | 9a64fbe4 | bellard | switch (pte1 & 0x00000003) { |
161 | 9a64fbe4 | bellard | case 0x0: |
162 | a541f297 | bellard | access = 0;
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163 | 9a64fbe4 | bellard | break;
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164 | 9a64fbe4 | bellard | case 0x1: |
165 | 9a64fbe4 | bellard | case 0x3: |
166 | 5f21aef2 | bellard | access = PAGE_READ; |
167 | 9a64fbe4 | bellard | break;
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168 | 9a64fbe4 | bellard | case 0x2: |
169 | 5f21aef2 | bellard | access = PAGE_READ | PAGE_WRITE; |
170 | 9a64fbe4 | bellard | break;
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171 | 9a64fbe4 | bellard | } |
172 | 9a64fbe4 | bellard | } |
173 | a541f297 | bellard | if (ret < 0) { |
174 | 5f21aef2 | bellard | if ((rw == 0 && (access & PAGE_READ)) || |
175 | 5f21aef2 | bellard | (rw == 1 && (access & PAGE_WRITE))) {
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176 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
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177 | a541f297 | bellard | if (loglevel > 0) |
178 | a541f297 | bellard | fprintf(logfile, "PTE access granted !\n");
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179 | 9a64fbe4 | bellard | #endif
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180 | d094807b | bellard | good = i; |
181 | d094807b | bellard | keep = pte1; |
182 | d094807b | bellard | ret = 0;
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183 | a541f297 | bellard | } else {
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184 | a541f297 | bellard | /* Access right violation */
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185 | d094807b | bellard | ret = -2;
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186 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
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187 | a541f297 | bellard | if (loglevel > 0) |
188 | a541f297 | bellard | fprintf(logfile, "PTE access rejected\n");
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189 | 9a64fbe4 | bellard | #endif
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190 | d094807b | bellard | } |
191 | a541f297 | bellard | *prot = access; |
192 | a541f297 | bellard | } |
193 | 9a64fbe4 | bellard | } |
194 | 9a64fbe4 | bellard | } |
195 | 9a64fbe4 | bellard | } |
196 | 9a64fbe4 | bellard | if (good != -1) { |
197 | 9a64fbe4 | bellard | *RPN = keep & 0xFFFFF000;
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198 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
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199 | d094807b | bellard | if (loglevel > 0) { |
200 | a541f297 | bellard | fprintf(logfile, "found PTE at addr 0x%08x prot=0x%01x ret=%d\n",
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201 | 9a64fbe4 | bellard | *RPN, *prot, ret); |
202 | a541f297 | bellard | } |
203 | 9a64fbe4 | bellard | #endif
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204 | 9a64fbe4 | bellard | /* Update page flags */
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205 | 9a64fbe4 | bellard | if (!(keep & 0x00000100)) { |
206 | a541f297 | bellard | /* Access flag */
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207 | 9a64fbe4 | bellard | keep |= 0x00000100;
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208 | 9a64fbe4 | bellard | store = 1;
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209 | 9a64fbe4 | bellard | } |
210 | d094807b | bellard | if (!(keep & 0x00000080)) { |
211 | a541f297 | bellard | if (rw && ret == 0) { |
212 | a541f297 | bellard | /* Change flag */
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213 | 9a64fbe4 | bellard | keep |= 0x00000080;
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214 | 9a64fbe4 | bellard | store = 1;
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215 | a541f297 | bellard | } else {
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216 | a541f297 | bellard | /* Force page fault for first write access */
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217 | 5f21aef2 | bellard | *prot &= ~PAGE_WRITE; |
218 | 9a64fbe4 | bellard | } |
219 | 9a64fbe4 | bellard | } |
220 | a541f297 | bellard | if (store) {
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221 | 8df1cd07 | bellard | stl_phys_notdirty(base + (good * 8) + 4, keep); |
222 | a541f297 | bellard | } |
223 | 9a64fbe4 | bellard | } |
224 | 9a64fbe4 | bellard | |
225 | 9a64fbe4 | bellard | return ret;
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226 | 79aceca5 | bellard | } |
227 | 79aceca5 | bellard | |
228 | 9a64fbe4 | bellard | static inline uint32_t get_pgaddr (uint32_t sdr1, uint32_t hash, uint32_t mask) |
229 | 79aceca5 | bellard | { |
230 | 9a64fbe4 | bellard | return (sdr1 & 0xFFFF0000) | (hash & mask); |
231 | 79aceca5 | bellard | } |
232 | 79aceca5 | bellard | |
233 | 9a64fbe4 | bellard | /* Perform segment based translation */
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234 | 9a64fbe4 | bellard | static int get_segment (CPUState *env, uint32_t *real, int *prot, |
235 | 9a64fbe4 | bellard | uint32_t virtual, int rw, int type) |
236 | 79aceca5 | bellard | { |
237 | 9a64fbe4 | bellard | uint32_t pg_addr, sdr, ptem, vsid, pgidx; |
238 | 9a64fbe4 | bellard | uint32_t hash, mask; |
239 | 9a64fbe4 | bellard | uint32_t sr; |
240 | 9a64fbe4 | bellard | int key;
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241 | 9a64fbe4 | bellard | int ret = -1, ret2; |
242 | 79aceca5 | bellard | |
243 | 9a64fbe4 | bellard | sr = env->sr[virtual >> 28];
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244 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
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245 | a541f297 | bellard | if (loglevel > 0) { |
246 | a541f297 | bellard | fprintf(logfile, "Check segment v=0x%08x %d 0x%08x nip=0x%08x "
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247 | a541f297 | bellard | "lr=0x%08x ir=%d dr=%d pr=%d %d t=%d\n",
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248 | a541f297 | bellard | virtual, virtual >> 28, sr, env->nip,
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249 | a541f297 | bellard | env->lr, msr_ir, msr_dr, msr_pr, rw, type); |
250 | a541f297 | bellard | } |
251 | 9a64fbe4 | bellard | #endif
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252 | a541f297 | bellard | key = (((sr & 0x20000000) && msr_pr == 1) || |
253 | a541f297 | bellard | ((sr & 0x40000000) && msr_pr == 0)) ? 1 : 0; |
254 | 9a64fbe4 | bellard | if ((sr & 0x80000000) == 0) { |
255 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
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256 | d094807b | bellard | if (loglevel > 0) |
257 | a541f297 | bellard | fprintf(logfile, "pte segment: key=%d n=0x%08x\n",
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258 | a541f297 | bellard | key, sr & 0x10000000);
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259 | 9a64fbe4 | bellard | #endif
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260 | 9a64fbe4 | bellard | /* Check if instruction fetch is allowed, if needed */
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261 | 9a64fbe4 | bellard | if (type != ACCESS_CODE || (sr & 0x10000000) == 0) { |
262 | 9a64fbe4 | bellard | /* Page address translation */
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263 | 9a64fbe4 | bellard | vsid = sr & 0x00FFFFFF;
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264 | 9a64fbe4 | bellard | pgidx = (virtual >> 12) & 0xFFFF; |
265 | a541f297 | bellard | sdr = env->sdr1; |
266 | a541f297 | bellard | hash = ((vsid ^ pgidx) & 0x0007FFFF) << 6; |
267 | 9a64fbe4 | bellard | mask = ((sdr & 0x000001FF) << 16) | 0xFFC0; |
268 | 9a64fbe4 | bellard | pg_addr = get_pgaddr(sdr, hash, mask); |
269 | 9a64fbe4 | bellard | ptem = (vsid << 7) | (pgidx >> 10); |
270 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
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271 | a541f297 | bellard | if (loglevel > 0) { |
272 | a541f297 | bellard | fprintf(logfile, "0 sdr1=0x%08x vsid=0x%06x api=0x%04x "
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273 | a541f297 | bellard | "hash=0x%07x pg_addr=0x%08x\n", sdr, vsid, pgidx, hash,
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274 | a541f297 | bellard | pg_addr); |
275 | a541f297 | bellard | } |
276 | 9a64fbe4 | bellard | #endif
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277 | 9a64fbe4 | bellard | /* Primary table lookup */
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278 | 9a64fbe4 | bellard | ret = find_pte(real, prot, pg_addr, ptem, 0, key, rw);
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279 | 9a64fbe4 | bellard | if (ret < 0) { |
280 | 9a64fbe4 | bellard | /* Secondary table lookup */
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281 | 9a64fbe4 | bellard | hash = (~hash) & 0x01FFFFC0;
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282 | 9a64fbe4 | bellard | pg_addr = get_pgaddr(sdr, hash, mask); |
283 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
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284 | a541f297 | bellard | if (virtual != 0xEFFFFFFF && loglevel > 0) { |
285 | a541f297 | bellard | fprintf(logfile, "1 sdr1=0x%08x vsid=0x%06x api=0x%04x "
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286 | a541f297 | bellard | "hash=0x%05x pg_addr=0x%08x\n", sdr, vsid, pgidx,
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287 | a541f297 | bellard | hash, pg_addr); |
288 | a541f297 | bellard | } |
289 | 9a64fbe4 | bellard | #endif
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290 | 9a64fbe4 | bellard | ret2 = find_pte(real, prot, pg_addr, ptem, 1, key, rw);
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291 | 9a64fbe4 | bellard | if (ret2 != -1) |
292 | 9a64fbe4 | bellard | ret = ret2; |
293 | 9a64fbe4 | bellard | } |
294 | 9a64fbe4 | bellard | } else {
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295 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
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296 | a541f297 | bellard | if (loglevel > 0) |
297 | a541f297 | bellard | fprintf(logfile, "No access allowed\n");
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298 | 9a64fbe4 | bellard | #endif
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299 | a541f297 | bellard | ret = -3;
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300 | 9a64fbe4 | bellard | } |
301 | 9a64fbe4 | bellard | } else {
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302 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
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303 | a541f297 | bellard | if (loglevel > 0) |
304 | a541f297 | bellard | fprintf(logfile, "direct store...\n");
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305 | 9a64fbe4 | bellard | #endif
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306 | 9a64fbe4 | bellard | /* Direct-store segment : absolutely *BUGGY* for now */
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307 | 9a64fbe4 | bellard | switch (type) {
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308 | 9a64fbe4 | bellard | case ACCESS_INT:
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309 | 9a64fbe4 | bellard | /* Integer load/store : only access allowed */
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310 | 9a64fbe4 | bellard | break;
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311 | 9a64fbe4 | bellard | case ACCESS_CODE:
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312 | 9a64fbe4 | bellard | /* No code fetch is allowed in direct-store areas */
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313 | 9a64fbe4 | bellard | return -4; |
314 | 9a64fbe4 | bellard | case ACCESS_FLOAT:
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315 | 9a64fbe4 | bellard | /* Floating point load/store */
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316 | 9a64fbe4 | bellard | return -4; |
317 | 9a64fbe4 | bellard | case ACCESS_RES:
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318 | 9a64fbe4 | bellard | /* lwarx, ldarx or srwcx. */
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319 | 9a64fbe4 | bellard | return -4; |
320 | 9a64fbe4 | bellard | case ACCESS_CACHE:
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321 | 9a64fbe4 | bellard | /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
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322 | 9a64fbe4 | bellard | /* Should make the instruction do no-op.
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323 | 9a64fbe4 | bellard | * As it already do no-op, it's quite easy :-)
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324 | 9a64fbe4 | bellard | */
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325 | 9a64fbe4 | bellard | *real = virtual; |
326 | 9a64fbe4 | bellard | return 0; |
327 | 9a64fbe4 | bellard | case ACCESS_EXT:
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328 | 9a64fbe4 | bellard | /* eciwx or ecowx */
|
329 | 9a64fbe4 | bellard | return -4; |
330 | 9a64fbe4 | bellard | default:
|
331 | 9a64fbe4 | bellard | if (logfile) {
|
332 | 9a64fbe4 | bellard | fprintf(logfile, "ERROR: instruction should not need "
|
333 | 9a64fbe4 | bellard | "address translation\n");
|
334 | 9a64fbe4 | bellard | } |
335 | 9a64fbe4 | bellard | printf("ERROR: instruction should not need "
|
336 | 9a64fbe4 | bellard | "address translation\n");
|
337 | 9a64fbe4 | bellard | return -4; |
338 | 9a64fbe4 | bellard | } |
339 | 9a64fbe4 | bellard | if ((rw == 1 || key != 1) && (rw == 0 || key != 0)) { |
340 | 9a64fbe4 | bellard | *real = virtual; |
341 | 9a64fbe4 | bellard | ret = 2;
|
342 | 9a64fbe4 | bellard | } else {
|
343 | 9a64fbe4 | bellard | ret = -2;
|
344 | 9a64fbe4 | bellard | } |
345 | 79aceca5 | bellard | } |
346 | 9a64fbe4 | bellard | |
347 | 9a64fbe4 | bellard | return ret;
|
348 | 79aceca5 | bellard | } |
349 | 79aceca5 | bellard | |
350 | 9a64fbe4 | bellard | int get_physical_address (CPUState *env, uint32_t *physical, int *prot, |
351 | 9a64fbe4 | bellard | uint32_t address, int rw, int access_type) |
352 | 9a64fbe4 | bellard | { |
353 | 9a64fbe4 | bellard | int ret;
|
354 | 514fb8c1 | bellard | #if 0
|
355 | 9a64fbe4 | bellard | if (loglevel > 0) {
|
356 | 9a64fbe4 | bellard | fprintf(logfile, "%s\n", __func__);
|
357 | 9a64fbe4 | bellard | }
|
358 | 514fb8c1 | bellard | #endif
|
359 | 4b3686fa | bellard | if ((access_type == ACCESS_CODE && msr_ir == 0) || |
360 | 4b3686fa | bellard | (access_type != ACCESS_CODE && msr_dr == 0)) {
|
361 | 9a64fbe4 | bellard | /* No address translation */
|
362 | a541f297 | bellard | *physical = address & ~0xFFF;
|
363 | 5f21aef2 | bellard | *prot = PAGE_READ | PAGE_WRITE; |
364 | 9a64fbe4 | bellard | ret = 0;
|
365 | 9a64fbe4 | bellard | } else {
|
366 | 9a64fbe4 | bellard | /* Try to find a BAT */
|
367 | 9a64fbe4 | bellard | ret = get_bat(env, physical, prot, address, rw, access_type); |
368 | 9a64fbe4 | bellard | if (ret < 0) { |
369 | 9a64fbe4 | bellard | /* We didn't match any BAT entry */
|
370 | 9a64fbe4 | bellard | ret = get_segment(env, physical, prot, address, rw, access_type); |
371 | 9a64fbe4 | bellard | } |
372 | 9a64fbe4 | bellard | } |
373 | 514fb8c1 | bellard | #if 0
|
374 | a541f297 | bellard | if (loglevel > 0) {
|
375 | a541f297 | bellard | fprintf(logfile, "%s address %08x => %08x\n",
|
376 | a541f297 | bellard | __func__, address, *physical);
|
377 | a541f297 | bellard | }
|
378 | 514fb8c1 | bellard | #endif
|
379 | 9a64fbe4 | bellard | return ret;
|
380 | 9a64fbe4 | bellard | } |
381 | 9a64fbe4 | bellard | |
382 | a6b025d3 | bellard | #if defined(CONFIG_USER_ONLY)
|
383 | a6b025d3 | bellard | target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
384 | a6b025d3 | bellard | { |
385 | a6b025d3 | bellard | return addr;
|
386 | a6b025d3 | bellard | } |
387 | a6b025d3 | bellard | #else
|
388 | a6b025d3 | bellard | target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
389 | a6b025d3 | bellard | { |
390 | a6b025d3 | bellard | uint32_t phys_addr; |
391 | a6b025d3 | bellard | int prot;
|
392 | a6b025d3 | bellard | |
393 | a6b025d3 | bellard | if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0) |
394 | a6b025d3 | bellard | return -1; |
395 | a6b025d3 | bellard | return phys_addr;
|
396 | a6b025d3 | bellard | } |
397 | a6b025d3 | bellard | #endif
|
398 | 9a64fbe4 | bellard | |
399 | 9a64fbe4 | bellard | #if !defined(CONFIG_USER_ONLY)
|
400 | 9a64fbe4 | bellard | |
401 | 9a64fbe4 | bellard | #define MMUSUFFIX _mmu
|
402 | 9a64fbe4 | bellard | #define GETPC() (__builtin_return_address(0)) |
403 | 9a64fbe4 | bellard | |
404 | 9a64fbe4 | bellard | #define SHIFT 0 |
405 | 9a64fbe4 | bellard | #include "softmmu_template.h" |
406 | 9a64fbe4 | bellard | |
407 | 9a64fbe4 | bellard | #define SHIFT 1 |
408 | 9a64fbe4 | bellard | #include "softmmu_template.h" |
409 | 9a64fbe4 | bellard | |
410 | 9a64fbe4 | bellard | #define SHIFT 2 |
411 | 9a64fbe4 | bellard | #include "softmmu_template.h" |
412 | 9a64fbe4 | bellard | |
413 | 9a64fbe4 | bellard | #define SHIFT 3 |
414 | 9a64fbe4 | bellard | #include "softmmu_template.h" |
415 | 9a64fbe4 | bellard | |
416 | 9a64fbe4 | bellard | /* try to fill the TLB and return an exception if error. If retaddr is
|
417 | 9a64fbe4 | bellard | NULL, it means that the function was called in C code (i.e. not
|
418 | 9a64fbe4 | bellard | from generated code or from helper.c) */
|
419 | 9a64fbe4 | bellard | /* XXX: fix it to restore all registers */
|
420 | 0fa85d43 | bellard | void tlb_fill(target_ulong addr, int is_write, int is_user, void *retaddr) |
421 | 9a64fbe4 | bellard | { |
422 | 9a64fbe4 | bellard | TranslationBlock *tb; |
423 | 9a64fbe4 | bellard | CPUState *saved_env; |
424 | a541f297 | bellard | unsigned long pc; |
425 | a541f297 | bellard | int ret;
|
426 | 9a64fbe4 | bellard | |
427 | 9a64fbe4 | bellard | /* XXX: hack to restore env in all cases, even if not called from
|
428 | 9a64fbe4 | bellard | generated code */
|
429 | 9a64fbe4 | bellard | saved_env = env; |
430 | 9a64fbe4 | bellard | env = cpu_single_env; |
431 | b769d8fe | bellard | #if 0
|
432 | 9a64fbe4 | bellard | {
|
433 | 9a64fbe4 | bellard | unsigned long tlb_addrr, tlb_addrw;
|
434 | 9a64fbe4 | bellard | int index;
|
435 | 9a64fbe4 | bellard | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
|
436 | 9a64fbe4 | bellard | tlb_addrr = env->tlb_read[is_user][index].address;
|
437 | 9a64fbe4 | bellard | tlb_addrw = env->tlb_write[is_user][index].address;
|
438 | 4b3686fa | bellard | if (loglevel) {
|
439 | 4b3686fa | bellard | fprintf(logfile,
|
440 | 4b3686fa | bellard | "%s 1 %p %p idx=%d addr=0x%08lx tbl_addr=0x%08lx 0x%08lx "
|
441 | 9a64fbe4 | bellard | "(0x%08lx 0x%08lx)\n", __func__, env,
|
442 | 9a64fbe4 | bellard | &env->tlb_read[is_user][index], index, addr,
|
443 | 9a64fbe4 | bellard | tlb_addrr, tlb_addrw, addr & TARGET_PAGE_MASK,
|
444 | 9a64fbe4 | bellard | tlb_addrr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
|
445 | 4b3686fa | bellard | }
|
446 | 9a64fbe4 | bellard | }
|
447 | b769d8fe | bellard | #endif
|
448 | a541f297 | bellard | ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, is_user, 1);
|
449 | 9a64fbe4 | bellard | if (ret) {
|
450 | 9a64fbe4 | bellard | if (retaddr) {
|
451 | 9a64fbe4 | bellard | /* now we have a real cpu fault */
|
452 | 9a64fbe4 | bellard | pc = (unsigned long)retaddr; |
453 | 9a64fbe4 | bellard | tb = tb_find_pc(pc); |
454 | 9a64fbe4 | bellard | if (tb) {
|
455 | 9a64fbe4 | bellard | /* the PC is inside the translated code. It means that we have
|
456 | 9a64fbe4 | bellard | a virtual CPU fault */
|
457 | b324e814 | bellard | cpu_restore_state(tb, env, pc, NULL);
|
458 | 9a64fbe4 | bellard | } |
459 | 9a64fbe4 | bellard | } |
460 | 9fddaa0c | bellard | do_raise_exception_err(env->exception_index, env->error_code); |
461 | 9a64fbe4 | bellard | } |
462 | b769d8fe | bellard | #if 0
|
463 | 9a64fbe4 | bellard | {
|
464 | 9a64fbe4 | bellard | unsigned long tlb_addrr, tlb_addrw;
|
465 | 9a64fbe4 | bellard | int index;
|
466 | 9a64fbe4 | bellard | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
|
467 | 9a64fbe4 | bellard | tlb_addrr = env->tlb_read[is_user][index].address;
|
468 | 9a64fbe4 | bellard | tlb_addrw = env->tlb_write[is_user][index].address;
|
469 | 9a64fbe4 | bellard | printf("%s 2 %p %p idx=%d addr=0x%08lx tbl_addr=0x%08lx 0x%08lx "
|
470 | 9a64fbe4 | bellard | "(0x%08lx 0x%08lx)\n", __func__, env,
|
471 | 9a64fbe4 | bellard | &env->tlb_read[is_user][index], index, addr,
|
472 | 9a64fbe4 | bellard | tlb_addrr, tlb_addrw, addr & TARGET_PAGE_MASK,
|
473 | 9a64fbe4 | bellard | tlb_addrr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
|
474 | 9a64fbe4 | bellard | }
|
475 | b769d8fe | bellard | #endif
|
476 | 9a64fbe4 | bellard | env = saved_env; |
477 | 9a64fbe4 | bellard | } |
478 | 9a64fbe4 | bellard | |
479 | a541f297 | bellard | void cpu_ppc_init_mmu(CPUState *env)
|
480 | 9a64fbe4 | bellard | { |
481 | 9a64fbe4 | bellard | /* Nothing to do: all translation are disabled */
|
482 | 9a64fbe4 | bellard | } |
483 | 9a64fbe4 | bellard | #endif
|
484 | 9a64fbe4 | bellard | |
485 | 9a64fbe4 | bellard | /* Perform address translation */
|
486 | 9a64fbe4 | bellard | int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw, |
487 | a541f297 | bellard | int is_user, int is_softmmu) |
488 | 9a64fbe4 | bellard | { |
489 | 9a64fbe4 | bellard | uint32_t physical; |
490 | 9a64fbe4 | bellard | int prot;
|
491 | 9a64fbe4 | bellard | int exception = 0, error_code = 0; |
492 | a541f297 | bellard | int access_type;
|
493 | 9a64fbe4 | bellard | int ret = 0; |
494 | 9a64fbe4 | bellard | |
495 | b769d8fe | bellard | if (rw == 2) { |
496 | b769d8fe | bellard | /* code access */
|
497 | b769d8fe | bellard | rw = 0;
|
498 | b769d8fe | bellard | access_type = ACCESS_CODE; |
499 | b769d8fe | bellard | } else {
|
500 | b769d8fe | bellard | /* data access */
|
501 | b769d8fe | bellard | /* XXX: put correct access by using cpu_restore_state()
|
502 | b769d8fe | bellard | correctly */
|
503 | b769d8fe | bellard | access_type = ACCESS_INT; |
504 | b769d8fe | bellard | // access_type = env->access_type;
|
505 | b769d8fe | bellard | } |
506 | 9a64fbe4 | bellard | if (env->user_mode_only) {
|
507 | 9a64fbe4 | bellard | /* user mode only emulation */
|
508 | 1ef59d0a | bellard | ret = -2;
|
509 | 9a64fbe4 | bellard | goto do_fault;
|
510 | 9a64fbe4 | bellard | } |
511 | 9a64fbe4 | bellard | ret = get_physical_address(env, &physical, &prot, |
512 | 9a64fbe4 | bellard | address, rw, access_type); |
513 | 9a64fbe4 | bellard | if (ret == 0) { |
514 | a541f297 | bellard | ret = tlb_set_page(env, address & ~0xFFF, physical, prot,
|
515 | a541f297 | bellard | is_user, is_softmmu); |
516 | 9a64fbe4 | bellard | } else if (ret < 0) { |
517 | 9a64fbe4 | bellard | do_fault:
|
518 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
|
519 | a541f297 | bellard | if (loglevel > 0) |
520 | 7fe48483 | bellard | cpu_dump_state(env, logfile, fprintf, 0);
|
521 | 9a64fbe4 | bellard | #endif
|
522 | 9a64fbe4 | bellard | if (access_type == ACCESS_CODE) {
|
523 | 9a64fbe4 | bellard | exception = EXCP_ISI; |
524 | 9a64fbe4 | bellard | switch (ret) {
|
525 | 9a64fbe4 | bellard | case -1: |
526 | 9a64fbe4 | bellard | /* No matches in page tables */
|
527 | 9a64fbe4 | bellard | error_code = EXCP_ISI_TRANSLATE; |
528 | 9a64fbe4 | bellard | break;
|
529 | 9a64fbe4 | bellard | case -2: |
530 | 9a64fbe4 | bellard | /* Access rights violation */
|
531 | 9a64fbe4 | bellard | error_code = EXCP_ISI_PROT; |
532 | 9a64fbe4 | bellard | break;
|
533 | 9a64fbe4 | bellard | case -3: |
534 | a541f297 | bellard | /* No execute protection violation */
|
535 | 9a64fbe4 | bellard | error_code = EXCP_ISI_NOEXEC; |
536 | 9a64fbe4 | bellard | break;
|
537 | 9a64fbe4 | bellard | case -4: |
538 | 9a64fbe4 | bellard | /* Direct store exception */
|
539 | 9a64fbe4 | bellard | /* No code fetch is allowed in direct-store areas */
|
540 | a541f297 | bellard | error_code = EXCP_ISI_DIRECT; |
541 | 9a64fbe4 | bellard | break;
|
542 | 9a64fbe4 | bellard | } |
543 | 9a64fbe4 | bellard | } else {
|
544 | 9a64fbe4 | bellard | exception = EXCP_DSI; |
545 | 9a64fbe4 | bellard | switch (ret) {
|
546 | 9a64fbe4 | bellard | case -1: |
547 | 9a64fbe4 | bellard | /* No matches in page tables */
|
548 | 9a64fbe4 | bellard | error_code = EXCP_DSI_TRANSLATE; |
549 | 9a64fbe4 | bellard | break;
|
550 | 9a64fbe4 | bellard | case -2: |
551 | 9a64fbe4 | bellard | /* Access rights violation */
|
552 | 9a64fbe4 | bellard | error_code = EXCP_DSI_PROT; |
553 | 9a64fbe4 | bellard | break;
|
554 | 9a64fbe4 | bellard | case -4: |
555 | 9a64fbe4 | bellard | /* Direct store exception */
|
556 | 9a64fbe4 | bellard | switch (access_type) {
|
557 | 9a64fbe4 | bellard | case ACCESS_FLOAT:
|
558 | 9a64fbe4 | bellard | /* Floating point load/store */
|
559 | 9a64fbe4 | bellard | exception = EXCP_ALIGN; |
560 | 9a64fbe4 | bellard | error_code = EXCP_ALIGN_FP; |
561 | 9a64fbe4 | bellard | break;
|
562 | 9a64fbe4 | bellard | case ACCESS_RES:
|
563 | 9a64fbe4 | bellard | /* lwarx, ldarx or srwcx. */
|
564 | 9a64fbe4 | bellard | exception = EXCP_DSI; |
565 | 9a64fbe4 | bellard | error_code = EXCP_DSI_NOTSUP | EXCP_DSI_DIRECT; |
566 | 9a64fbe4 | bellard | break;
|
567 | 9a64fbe4 | bellard | case ACCESS_EXT:
|
568 | 9a64fbe4 | bellard | /* eciwx or ecowx */
|
569 | 9a64fbe4 | bellard | exception = EXCP_DSI; |
570 | a541f297 | bellard | error_code = EXCP_DSI_NOTSUP | EXCP_DSI_DIRECT | |
571 | a541f297 | bellard | EXCP_DSI_ECXW; |
572 | 9a64fbe4 | bellard | break;
|
573 | 9a64fbe4 | bellard | default:
|
574 | a541f297 | bellard | printf("DSI: invalid exception (%d)\n", ret);
|
575 | 9a64fbe4 | bellard | exception = EXCP_PROGRAM; |
576 | 9a64fbe4 | bellard | error_code = EXCP_INVAL | EXCP_INVAL_INVAL; |
577 | 9a64fbe4 | bellard | break;
|
578 | 9a64fbe4 | bellard | } |
579 | 9a64fbe4 | bellard | } |
580 | 9a64fbe4 | bellard | if (rw)
|
581 | 9a64fbe4 | bellard | error_code |= EXCP_DSI_STORE; |
582 | a541f297 | bellard | /* Store fault address */
|
583 | a541f297 | bellard | env->spr[DAR] = address; |
584 | 9a64fbe4 | bellard | } |
585 | 9a64fbe4 | bellard | #if 0
|
586 | 9a64fbe4 | bellard | printf("%s: set exception to %d %02x\n",
|
587 | 9a64fbe4 | bellard | __func__, exception, error_code);
|
588 | 9a64fbe4 | bellard | #endif
|
589 | 9a64fbe4 | bellard | env->exception_index = exception; |
590 | 9a64fbe4 | bellard | env->error_code = error_code; |
591 | 9a64fbe4 | bellard | ret = 1;
|
592 | 9a64fbe4 | bellard | } |
593 | 9a64fbe4 | bellard | return ret;
|
594 | 9a64fbe4 | bellard | } |
595 | 9a64fbe4 | bellard | |
596 | a541f297 | bellard | uint32_t _load_xer (CPUState *env) |
597 | 79aceca5 | bellard | { |
598 | 79aceca5 | bellard | return (xer_so << XER_SO) |
|
599 | 79aceca5 | bellard | (xer_ov << XER_OV) | |
600 | 79aceca5 | bellard | (xer_ca << XER_CA) | |
601 | 79aceca5 | bellard | (xer_bc << XER_BC); |
602 | 79aceca5 | bellard | } |
603 | 79aceca5 | bellard | |
604 | a541f297 | bellard | void _store_xer (CPUState *env, uint32_t value)
|
605 | 79aceca5 | bellard | { |
606 | 79aceca5 | bellard | xer_so = (value >> XER_SO) & 0x01;
|
607 | 79aceca5 | bellard | xer_ov = (value >> XER_OV) & 0x01;
|
608 | 79aceca5 | bellard | xer_ca = (value >> XER_CA) & 0x01;
|
609 | d094807b | bellard | xer_bc = (value >> XER_BC) & 0x3f;
|
610 | 79aceca5 | bellard | } |
611 | 79aceca5 | bellard | |
612 | a541f297 | bellard | uint32_t _load_msr (CPUState *env) |
613 | 79aceca5 | bellard | { |
614 | 79aceca5 | bellard | return (msr_pow << MSR_POW) |
|
615 | 79aceca5 | bellard | (msr_ile << MSR_ILE) | |
616 | 79aceca5 | bellard | (msr_ee << MSR_EE) | |
617 | 79aceca5 | bellard | (msr_pr << MSR_PR) | |
618 | 79aceca5 | bellard | (msr_fp << MSR_FP) | |
619 | 79aceca5 | bellard | (msr_me << MSR_ME) | |
620 | 79aceca5 | bellard | (msr_fe0 << MSR_FE0) | |
621 | 79aceca5 | bellard | (msr_se << MSR_SE) | |
622 | 79aceca5 | bellard | (msr_be << MSR_BE) | |
623 | 79aceca5 | bellard | (msr_fe1 << MSR_FE1) | |
624 | 79aceca5 | bellard | (msr_ip << MSR_IP) | |
625 | 79aceca5 | bellard | (msr_ir << MSR_IR) | |
626 | 79aceca5 | bellard | (msr_dr << MSR_DR) | |
627 | 79aceca5 | bellard | (msr_ri << MSR_RI) | |
628 | 79aceca5 | bellard | (msr_le << MSR_LE); |
629 | 79aceca5 | bellard | } |
630 | 79aceca5 | bellard | |
631 | a541f297 | bellard | void _store_msr (CPUState *env, uint32_t value)
|
632 | 79aceca5 | bellard | { |
633 | d094807b | bellard | #ifdef ACCURATE_TLB_FLUSH
|
634 | 1ef59d0a | bellard | if (((value >> MSR_IR) & 0x01) != msr_ir || |
635 | 4b3686fa | bellard | ((value >> MSR_DR) & 0x01) != msr_dr)
|
636 | 4b3686fa | bellard | { |
637 | a541f297 | bellard | /* Flush all tlb when changing translation mode or privilege level */
|
638 | d094807b | bellard | tlb_flush(env, 1);
|
639 | a541f297 | bellard | } |
640 | 4b3686fa | bellard | #endif
|
641 | 9a64fbe4 | bellard | msr_pow = (value >> MSR_POW) & 0x03;
|
642 | 9a64fbe4 | bellard | msr_ile = (value >> MSR_ILE) & 0x01;
|
643 | 9a64fbe4 | bellard | msr_ee = (value >> MSR_EE) & 0x01;
|
644 | 9a64fbe4 | bellard | msr_pr = (value >> MSR_PR) & 0x01;
|
645 | 9a64fbe4 | bellard | msr_fp = (value >> MSR_FP) & 0x01;
|
646 | 9a64fbe4 | bellard | msr_me = (value >> MSR_ME) & 0x01;
|
647 | 9a64fbe4 | bellard | msr_fe0 = (value >> MSR_FE0) & 0x01;
|
648 | 9a64fbe4 | bellard | msr_se = (value >> MSR_SE) & 0x01;
|
649 | 9a64fbe4 | bellard | msr_be = (value >> MSR_BE) & 0x01;
|
650 | 9a64fbe4 | bellard | msr_fe1 = (value >> MSR_FE1) & 0x01;
|
651 | 9a64fbe4 | bellard | msr_ip = (value >> MSR_IP) & 0x01;
|
652 | 9a64fbe4 | bellard | msr_ir = (value >> MSR_IR) & 0x01;
|
653 | 9a64fbe4 | bellard | msr_dr = (value >> MSR_DR) & 0x01;
|
654 | 9a64fbe4 | bellard | msr_ri = (value >> MSR_RI) & 0x01;
|
655 | 9a64fbe4 | bellard | msr_le = (value >> MSR_LE) & 0x01;
|
656 | 18fba28c | bellard | /* XXX: should enter PM state if msr_pow has been set */
|
657 | 79aceca5 | bellard | } |
658 | 79aceca5 | bellard | |
659 | 18fba28c | bellard | #if defined (CONFIG_USER_ONLY)
|
660 | 9a64fbe4 | bellard | void do_interrupt (CPUState *env)
|
661 | 79aceca5 | bellard | { |
662 | 18fba28c | bellard | env->exception_index = -1;
|
663 | 18fba28c | bellard | } |
664 | 9a64fbe4 | bellard | #else
|
665 | d094807b | bellard | static void dump_syscall(CPUState *env) |
666 | d094807b | bellard | { |
667 | d094807b | bellard | fprintf(logfile, "syscall r0=0x%08x r3=0x%08x r4=0x%08x r5=0x%08x r6=0x%08x nip=0x%08x\n",
|
668 | d094807b | bellard | env->gpr[0], env->gpr[3], env->gpr[4], |
669 | d094807b | bellard | env->gpr[5], env->gpr[6], env->nip); |
670 | d094807b | bellard | } |
671 | d094807b | bellard | |
672 | 18fba28c | bellard | void do_interrupt (CPUState *env)
|
673 | 18fba28c | bellard | { |
674 | 9a64fbe4 | bellard | uint32_t msr; |
675 | 18fba28c | bellard | int excp;
|
676 | 79aceca5 | bellard | |
677 | 18fba28c | bellard | excp = env->exception_index; |
678 | a541f297 | bellard | msr = _load_msr(env); |
679 | 9a64fbe4 | bellard | #if defined (DEBUG_EXCEPTIONS)
|
680 | a541f297 | bellard | if ((excp == EXCP_PROGRAM || excp == EXCP_DSI) && msr_pr == 1) |
681 | 9a64fbe4 | bellard | { |
682 | 9a64fbe4 | bellard | if (loglevel > 0) { |
683 | 9a64fbe4 | bellard | fprintf(logfile, "Raise exception at 0x%08x => 0x%08x (%02x)\n",
|
684 | 9a64fbe4 | bellard | env->nip, excp << 8, env->error_code);
|
685 | b769d8fe | bellard | } |
686 | a541f297 | bellard | if (loglevel > 0) |
687 | 7fe48483 | bellard | cpu_dump_state(env, logfile, fprintf, 0);
|
688 | 79aceca5 | bellard | } |
689 | 9a64fbe4 | bellard | #endif
|
690 | b769d8fe | bellard | if (loglevel & CPU_LOG_INT) {
|
691 | b769d8fe | bellard | fprintf(logfile, "Raise exception at 0x%08x => 0x%08x (%02x)\n",
|
692 | b769d8fe | bellard | env->nip, excp << 8, env->error_code);
|
693 | b769d8fe | bellard | } |
694 | 9a64fbe4 | bellard | /* Generate informations in save/restore registers */
|
695 | 9a64fbe4 | bellard | switch (excp) {
|
696 | 9a64fbe4 | bellard | case EXCP_NONE:
|
697 | 9a64fbe4 | bellard | /* Do nothing */
|
698 | 9a64fbe4 | bellard | #if defined (DEBUG_EXCEPTIONS)
|
699 | 9a64fbe4 | bellard | printf("%s: escape EXCP_NONE\n", __func__);
|
700 | 9a64fbe4 | bellard | #endif
|
701 | 9a64fbe4 | bellard | return;
|
702 | 9a64fbe4 | bellard | case EXCP_RESET:
|
703 | 9a64fbe4 | bellard | if (msr_ip)
|
704 | 9a64fbe4 | bellard | excp += 0xFFC00;
|
705 | 9a64fbe4 | bellard | goto store_next;
|
706 | 9a64fbe4 | bellard | case EXCP_MACHINE_CHECK:
|
707 | 9a64fbe4 | bellard | if (msr_me == 0) { |
708 | 4b3686fa | bellard | cpu_abort(env, "Machine check exception while not allowed\n");
|
709 | 79aceca5 | bellard | } |
710 | 9a64fbe4 | bellard | msr_me = 0;
|
711 | 9a64fbe4 | bellard | break;
|
712 | 9a64fbe4 | bellard | case EXCP_DSI:
|
713 | 9a64fbe4 | bellard | /* Store exception cause */
|
714 | 9a64fbe4 | bellard | /* data location address has been stored
|
715 | 9a64fbe4 | bellard | * when the fault has been detected
|
716 | 9a64fbe4 | bellard | */
|
717 | a541f297 | bellard | msr &= ~0xFFFF0000;
|
718 | a541f297 | bellard | env->spr[DSISR] = 0;
|
719 | d094807b | bellard | if ((env->error_code & 0x0f) == EXCP_DSI_TRANSLATE) |
720 | a541f297 | bellard | env->spr[DSISR] |= 0x40000000;
|
721 | d094807b | bellard | else if ((env->error_code & 0x0f) == EXCP_DSI_PROT) |
722 | a541f297 | bellard | env->spr[DSISR] |= 0x08000000;
|
723 | d094807b | bellard | else if ((env->error_code & 0x0f) == EXCP_DSI_NOTSUP) { |
724 | a541f297 | bellard | env->spr[DSISR] |= 0x80000000;
|
725 | a541f297 | bellard | if (env->error_code & EXCP_DSI_DIRECT)
|
726 | a541f297 | bellard | env->spr[DSISR] |= 0x04000000;
|
727 | a541f297 | bellard | } |
728 | a541f297 | bellard | if (env->error_code & EXCP_DSI_STORE)
|
729 | a541f297 | bellard | env->spr[DSISR] |= 0x02000000;
|
730 | a541f297 | bellard | if ((env->error_code & 0xF) == EXCP_DSI_DABR) |
731 | a541f297 | bellard | env->spr[DSISR] |= 0x00400000;
|
732 | a541f297 | bellard | if (env->error_code & EXCP_DSI_ECXW)
|
733 | a541f297 | bellard | env->spr[DSISR] |= 0x00100000;
|
734 | a541f297 | bellard | #if defined (DEBUG_EXCEPTIONS)
|
735 | a541f297 | bellard | if (loglevel) {
|
736 | a541f297 | bellard | fprintf(logfile, "DSI exception: DSISR=0x%08x, DAR=0x%08x\n",
|
737 | a541f297 | bellard | env->spr[DSISR], env->spr[DAR]); |
738 | a541f297 | bellard | } else {
|
739 | a541f297 | bellard | printf("DSI exception: DSISR=0x%08x, DAR=0x%08x nip=0x%08x\n",
|
740 | a541f297 | bellard | env->spr[DSISR], env->spr[DAR], env->nip); |
741 | a541f297 | bellard | } |
742 | a541f297 | bellard | #endif
|
743 | a541f297 | bellard | goto store_next;
|
744 | 9a64fbe4 | bellard | case EXCP_ISI:
|
745 | 9a64fbe4 | bellard | /* Store exception cause */
|
746 | a541f297 | bellard | msr &= ~0xFFFF0000;
|
747 | 9a64fbe4 | bellard | if (env->error_code == EXCP_ISI_TRANSLATE)
|
748 | 9a64fbe4 | bellard | msr |= 0x40000000;
|
749 | 9a64fbe4 | bellard | else if (env->error_code == EXCP_ISI_NOEXEC || |
750 | a541f297 | bellard | env->error_code == EXCP_ISI_GUARD || |
751 | a541f297 | bellard | env->error_code == EXCP_ISI_DIRECT) |
752 | 9a64fbe4 | bellard | msr |= 0x10000000;
|
753 | 9a64fbe4 | bellard | else
|
754 | 9a64fbe4 | bellard | msr |= 0x08000000;
|
755 | a541f297 | bellard | #if defined (DEBUG_EXCEPTIONS)
|
756 | a541f297 | bellard | if (loglevel) {
|
757 | a541f297 | bellard | fprintf(logfile, "ISI exception: msr=0x%08x, nip=0x%08x\n",
|
758 | a541f297 | bellard | msr, env->nip); |
759 | a541f297 | bellard | } else {
|
760 | a541f297 | bellard | printf("ISI exception: msr=0x%08x, nip=0x%08x tbl:0x%08x\n",
|
761 | a541f297 | bellard | msr, env->nip, env->spr[V_TBL]); |
762 | a541f297 | bellard | } |
763 | a541f297 | bellard | #endif
|
764 | 9a64fbe4 | bellard | goto store_next;
|
765 | 9a64fbe4 | bellard | case EXCP_EXTERNAL:
|
766 | 9a64fbe4 | bellard | if (msr_ee == 0) { |
767 | 9a64fbe4 | bellard | #if defined (DEBUG_EXCEPTIONS)
|
768 | 9a64fbe4 | bellard | if (loglevel > 0) { |
769 | 9a64fbe4 | bellard | fprintf(logfile, "Skipping hardware interrupt\n");
|
770 | 79aceca5 | bellard | } |
771 | 9a64fbe4 | bellard | #endif
|
772 | a541f297 | bellard | /* Requeue it */
|
773 | 9fddaa0c | bellard | do_raise_exception(EXCP_EXTERNAL); |
774 | 9a64fbe4 | bellard | return;
|
775 | 79aceca5 | bellard | } |
776 | 9a64fbe4 | bellard | goto store_next;
|
777 | 9a64fbe4 | bellard | case EXCP_ALIGN:
|
778 | 9a64fbe4 | bellard | /* Store exception cause */
|
779 | 9a64fbe4 | bellard | /* Get rS/rD and rA from faulting opcode */
|
780 | 9a64fbe4 | bellard | env->spr[DSISR] |= |
781 | 0fa85d43 | bellard | (ldl_code((env->nip - 4)) & 0x03FF0000) >> 16; |
782 | 9a64fbe4 | bellard | /* data location address has been stored
|
783 | 9a64fbe4 | bellard | * when the fault has been detected
|
784 | 9a64fbe4 | bellard | */
|
785 | 9a64fbe4 | bellard | goto store_current;
|
786 | 9a64fbe4 | bellard | case EXCP_PROGRAM:
|
787 | 9a64fbe4 | bellard | msr &= ~0xFFFF0000;
|
788 | 9a64fbe4 | bellard | switch (env->error_code & ~0xF) { |
789 | 9a64fbe4 | bellard | case EXCP_FP:
|
790 | 9a64fbe4 | bellard | if (msr_fe0 == 0 && msr_fe1 == 0) { |
791 | 9a64fbe4 | bellard | #if defined (DEBUG_EXCEPTIONS)
|
792 | 9a64fbe4 | bellard | printf("Ignore floating point exception\n");
|
793 | 9a64fbe4 | bellard | #endif
|
794 | 9a64fbe4 | bellard | return;
|
795 | 79aceca5 | bellard | } |
796 | 9a64fbe4 | bellard | msr |= 0x00100000;
|
797 | 9a64fbe4 | bellard | /* Set FX */
|
798 | 9a64fbe4 | bellard | env->fpscr[7] |= 0x8; |
799 | 9a64fbe4 | bellard | /* Finally, update FEX */
|
800 | 9a64fbe4 | bellard | if ((((env->fpscr[7] & 0x3) << 3) | (env->fpscr[6] >> 1)) & |
801 | 9a64fbe4 | bellard | ((env->fpscr[1] << 1) | (env->fpscr[0] >> 3))) |
802 | 9a64fbe4 | bellard | env->fpscr[7] |= 0x4; |
803 | 9a64fbe4 | bellard | break;
|
804 | 9a64fbe4 | bellard | case EXCP_INVAL:
|
805 | 4b3686fa | bellard | // printf("Invalid instruction at 0x%08x\n", env->nip);
|
806 | 9a64fbe4 | bellard | msr |= 0x00080000;
|
807 | 9a64fbe4 | bellard | break;
|
808 | 9a64fbe4 | bellard | case EXCP_PRIV:
|
809 | 9a64fbe4 | bellard | msr |= 0x00040000;
|
810 | 9a64fbe4 | bellard | break;
|
811 | 9a64fbe4 | bellard | case EXCP_TRAP:
|
812 | 9a64fbe4 | bellard | msr |= 0x00020000;
|
813 | 9a64fbe4 | bellard | break;
|
814 | 9a64fbe4 | bellard | default:
|
815 | 9a64fbe4 | bellard | /* Should never occur */
|
816 | 9a64fbe4 | bellard | break;
|
817 | 79aceca5 | bellard | } |
818 | 9a64fbe4 | bellard | msr |= 0x00010000;
|
819 | 9a64fbe4 | bellard | goto store_current;
|
820 | 9a64fbe4 | bellard | case EXCP_NO_FP:
|
821 | 4ecc3190 | bellard | msr &= ~0xFFFF0000;
|
822 | 9a64fbe4 | bellard | goto store_current;
|
823 | 9a64fbe4 | bellard | case EXCP_DECR:
|
824 | 9a64fbe4 | bellard | if (msr_ee == 0) { |
825 | 9a64fbe4 | bellard | /* Requeue it */
|
826 | 9fddaa0c | bellard | do_raise_exception(EXCP_DECR); |
827 | 9a64fbe4 | bellard | return;
|
828 | 9a64fbe4 | bellard | } |
829 | 9a64fbe4 | bellard | goto store_next;
|
830 | 9a64fbe4 | bellard | case EXCP_SYSCALL:
|
831 | d094807b | bellard | /* NOTE: this is a temporary hack to support graphics OSI
|
832 | d094807b | bellard | calls from the MOL driver */
|
833 | d094807b | bellard | if (env->gpr[3] == 0x113724fa && env->gpr[4] == 0x77810f9b && |
834 | d094807b | bellard | env->osi_call) { |
835 | d094807b | bellard | if (env->osi_call(env) != 0) |
836 | d094807b | bellard | return;
|
837 | d094807b | bellard | } |
838 | b769d8fe | bellard | if (loglevel & CPU_LOG_INT) {
|
839 | d094807b | bellard | dump_syscall(env); |
840 | b769d8fe | bellard | } |
841 | 9a64fbe4 | bellard | goto store_next;
|
842 | 9a64fbe4 | bellard | case EXCP_TRACE:
|
843 | 9a64fbe4 | bellard | goto store_next;
|
844 | 9a64fbe4 | bellard | case EXCP_FP_ASSIST:
|
845 | 9a64fbe4 | bellard | goto store_next;
|
846 | 9a64fbe4 | bellard | case EXCP_MTMSR:
|
847 | 9a64fbe4 | bellard | /* Nothing to do */
|
848 | 9a64fbe4 | bellard | return;
|
849 | 9a64fbe4 | bellard | case EXCP_BRANCH:
|
850 | 9a64fbe4 | bellard | /* Nothing to do */
|
851 | 9a64fbe4 | bellard | return;
|
852 | 9a64fbe4 | bellard | case EXCP_RFI:
|
853 | 9a64fbe4 | bellard | /* Restore user-mode state */
|
854 | 9a64fbe4 | bellard | #if defined (DEBUG_EXCEPTIONS)
|
855 | a541f297 | bellard | if (msr_pr == 1) |
856 | a541f297 | bellard | printf("Return from exception => 0x%08x\n", (uint32_t)env->nip);
|
857 | 9a64fbe4 | bellard | #endif
|
858 | 9a64fbe4 | bellard | return;
|
859 | 9a64fbe4 | bellard | store_current:
|
860 | 9a64fbe4 | bellard | /* SRR0 is set to current instruction */
|
861 | 9a64fbe4 | bellard | env->spr[SRR0] = (uint32_t)env->nip - 4;
|
862 | 9a64fbe4 | bellard | break;
|
863 | 9a64fbe4 | bellard | store_next:
|
864 | 9a64fbe4 | bellard | /* SRR0 is set to next instruction */
|
865 | 9a64fbe4 | bellard | env->spr[SRR0] = (uint32_t)env->nip; |
866 | 9a64fbe4 | bellard | break;
|
867 | 9a64fbe4 | bellard | } |
868 | 9a64fbe4 | bellard | env->spr[SRR1] = msr; |
869 | 9a64fbe4 | bellard | /* reload MSR with correct bits */
|
870 | 9a64fbe4 | bellard | msr_pow = 0;
|
871 | 9a64fbe4 | bellard | msr_ee = 0;
|
872 | 9a64fbe4 | bellard | msr_pr = 0;
|
873 | 9a64fbe4 | bellard | msr_fp = 0;
|
874 | 9a64fbe4 | bellard | msr_fe0 = 0;
|
875 | 9a64fbe4 | bellard | msr_se = 0;
|
876 | 9a64fbe4 | bellard | msr_be = 0;
|
877 | 9a64fbe4 | bellard | msr_fe1 = 0;
|
878 | 9a64fbe4 | bellard | msr_ir = 0;
|
879 | 9a64fbe4 | bellard | msr_dr = 0;
|
880 | 9a64fbe4 | bellard | msr_ri = 0;
|
881 | 9a64fbe4 | bellard | msr_le = msr_ile; |
882 | 9a64fbe4 | bellard | /* Jump to handler */
|
883 | 9a64fbe4 | bellard | env->nip = excp << 8;
|
884 | 9a64fbe4 | bellard | env->exception_index = EXCP_NONE; |
885 | 9a64fbe4 | bellard | /* Invalidate all TLB as we may have changed translation mode */
|
886 | d094807b | bellard | #ifdef ACCURATE_TLB_FLUSH
|
887 | d094807b | bellard | tlb_flush(env, 1);
|
888 | d094807b | bellard | #endif
|
889 | 9a64fbe4 | bellard | /* ensure that no TB jump will be modified as
|
890 | 9a64fbe4 | bellard | the program flow was changed */
|
891 | 9a64fbe4 | bellard | #ifdef __sparc__
|
892 | 9a64fbe4 | bellard | tmp_T0 = 0;
|
893 | 9a64fbe4 | bellard | #else
|
894 | 9a64fbe4 | bellard | T0 = 0;
|
895 | 9a64fbe4 | bellard | #endif
|
896 | 9fddaa0c | bellard | env->exception_index = -1;
|
897 | fb0eaffc | bellard | } |
898 | 18fba28c | bellard | #endif /* !CONFIG_USER_ONLY */ |