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/*
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 *  PPC emulation for qemu: main translation routines.
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 * 
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 *  Copyright (c) 2003 Jocelyn Mayer
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
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#include <stdarg.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <inttypes.h>
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#include "cpu.h"
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#include "exec-all.h"
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#include "disas.h"
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//#define DO_SINGLE_STEP
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//#define PPC_DEBUG_DISAS
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enum {
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#define DEF(s, n, copy_size) INDEX_op_ ## s,
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#include "opc.h"
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#undef DEF
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    NB_OPS,
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};
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static uint16_t *gen_opc_ptr;
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static uint32_t *gen_opparam_ptr;
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#include "gen-op.h"
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#define GEN8(func, NAME) \
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static GenOpFunc *NAME ## _table [8] = {                                      \
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NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \
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NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \
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};                                                                            \
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static inline void func(int n)                                                \
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{                                                                             \
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    NAME ## _table[n]();                                                      \
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}
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#define GEN16(func, NAME)                                                     \
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static GenOpFunc *NAME ## _table [16] = {                                     \
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NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \
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NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \
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NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11,                                 \
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NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15,                               \
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};                                                                            \
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static inline void func(int n)                                                \
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{                                                                             \
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    NAME ## _table[n]();                                                      \
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}
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#define GEN32(func, NAME) \
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static GenOpFunc *NAME ## _table [32] = {                                     \
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NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \
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NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \
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NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11,                                 \
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NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15,                               \
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NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19,                               \
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NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23,                               \
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NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27,                               \
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NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31,                               \
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};                                                                            \
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static inline void func(int n)                                                \
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{                                                                             \
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    NAME ## _table[n]();                                                      \
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}
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/* Condition register moves */
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GEN8(gen_op_load_crf_T0, gen_op_load_crf_T0_crf);
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GEN8(gen_op_load_crf_T1, gen_op_load_crf_T1_crf);
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GEN8(gen_op_store_T0_crf, gen_op_store_T0_crf_crf);
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GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf);
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/* Floating point condition and status register moves */
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GEN8(gen_op_load_fpscr_T0, gen_op_load_fpscr_T0_fpscr);
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GEN8(gen_op_store_T0_fpscr, gen_op_store_T0_fpscr_fpscr);
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GEN8(gen_op_clear_fpscr, gen_op_clear_fpscr_fpscr);
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static GenOpFunc1 *gen_op_store_T0_fpscri_fpscr_table[8] = {
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    &gen_op_store_T0_fpscri_fpscr0,
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    &gen_op_store_T0_fpscri_fpscr1,
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    &gen_op_store_T0_fpscri_fpscr2,
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    &gen_op_store_T0_fpscri_fpscr3,
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    &gen_op_store_T0_fpscri_fpscr4,
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    &gen_op_store_T0_fpscri_fpscr5,
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    &gen_op_store_T0_fpscri_fpscr6,
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    &gen_op_store_T0_fpscri_fpscr7,
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};
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static inline void gen_op_store_T0_fpscri(int n, uint8_t param)
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{
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    (*gen_op_store_T0_fpscri_fpscr_table[n])(param);
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}
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/* Segment register moves */
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GEN16(gen_op_load_sr, gen_op_load_sr);
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GEN16(gen_op_store_sr, gen_op_store_sr);
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/* General purpose registers moves */
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GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr);
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GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr);
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GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr);
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GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);
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GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);
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GEN32(gen_op_store_T2_gpr, gen_op_store_T2_gpr_gpr);
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/* floating point registers moves */
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GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fpr);
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GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fpr);
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GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fpr);
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GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fpr);
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GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fpr);
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GEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fpr);
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static uint8_t  spr_access[1024 / 2];
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/* internal defines */
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typedef struct DisasContext {
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    struct TranslationBlock *tb;
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    target_ulong nip;
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    uint32_t opcode;
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    uint32_t exception;
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    /* Routine used to access memory */
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    int mem_idx;
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    /* Translation flags */
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#if !defined(CONFIG_USER_ONLY)
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    int supervisor;
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#endif
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    int fpu_enabled;
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} DisasContext;
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typedef struct opc_handler_t {
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    /* invalid bits */
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    uint32_t inval;
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    /* instruction type */
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    uint32_t type;
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    /* handler */
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    void (*handler)(DisasContext *ctx);
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} opc_handler_t;
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#define RET_EXCP(ctx, excp, error)                                            \
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do {                                                                          \
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    if ((ctx)->exception == EXCP_NONE) {                                      \
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        gen_op_update_nip((ctx)->nip);                                        \
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    }                                                                         \
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    gen_op_raise_exception_err((excp), (error));                              \
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    ctx->exception = (excp);                                                  \
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} while (0)
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#define RET_INVAL(ctx)                                                        \
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RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_INVAL)
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#define RET_PRIVOPC(ctx)                                                      \
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RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_OPC)
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#define RET_PRIVREG(ctx)                                                      \
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RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_REG)
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#define RET_MTMSR(ctx)                                                        \
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RET_EXCP((ctx), EXCP_MTMSR, 0)
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#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                      \
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static void gen_##name (DisasContext *ctx);                                   \
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GEN_OPCODE(name, opc1, opc2, opc3, inval, type);                              \
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static void gen_##name (DisasContext *ctx)
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typedef struct opcode_t {
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    unsigned char opc1, opc2, opc3;
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#if HOST_LONG_BITS == 64 /* Explicitely align to 64 bits */
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    unsigned char pad[5];
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#else
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    unsigned char pad[1];
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#endif
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    opc_handler_t handler;
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} opcode_t;
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/***                           Instruction decoding                        ***/
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#define EXTRACT_HELPER(name, shift, nb)                                       \
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static inline uint32_t name (uint32_t opcode)                                 \
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{                                                                             \
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    return (opcode >> (shift)) & ((1 << (nb)) - 1);                           \
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}
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#define EXTRACT_SHELPER(name, shift, nb)                                      \
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static inline int32_t name (uint32_t opcode)                                  \
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{                                                                             \
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    return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1));                \
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}
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/* Opcode part 1 */
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EXTRACT_HELPER(opc1, 26, 6);
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/* Opcode part 2 */
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EXTRACT_HELPER(opc2, 1, 5);
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/* Opcode part 3 */
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EXTRACT_HELPER(opc3, 6, 5);
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/* Update Cr0 flags */
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EXTRACT_HELPER(Rc, 0, 1);
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/* Destination */
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EXTRACT_HELPER(rD, 21, 5);
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/* Source */
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EXTRACT_HELPER(rS, 21, 5);
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/* First operand */
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EXTRACT_HELPER(rA, 16, 5);
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/* Second operand */
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EXTRACT_HELPER(rB, 11, 5);
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/* Third operand */
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EXTRACT_HELPER(rC, 6, 5);
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/***                               Get CRn                                 ***/
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EXTRACT_HELPER(crfD, 23, 3);
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EXTRACT_HELPER(crfS, 18, 3);
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EXTRACT_HELPER(crbD, 21, 5);
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EXTRACT_HELPER(crbA, 16, 5);
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EXTRACT_HELPER(crbB, 11, 5);
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/* SPR / TBL */
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EXTRACT_HELPER(SPR, 11, 10);
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/***                              Get constants                            ***/
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EXTRACT_HELPER(IMM, 12, 8);
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/* 16 bits signed immediate value */
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EXTRACT_SHELPER(SIMM, 0, 16);
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/* 16 bits unsigned immediate value */
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EXTRACT_HELPER(UIMM, 0, 16);
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/* Bit count */
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EXTRACT_HELPER(NB, 11, 5);
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/* Shift count */
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EXTRACT_HELPER(SH, 11, 5);
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/* Mask start */
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EXTRACT_HELPER(MB, 6, 5);
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/* Mask end */
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EXTRACT_HELPER(ME, 1, 5);
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/* Trap operand */
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EXTRACT_HELPER(TO, 21, 5);
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EXTRACT_HELPER(CRM, 12, 8);
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EXTRACT_HELPER(FM, 17, 8);
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EXTRACT_HELPER(SR, 16, 4);
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EXTRACT_HELPER(FPIMM, 20, 4);
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/***                            Jump target decoding                       ***/
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/* Displacement */
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EXTRACT_SHELPER(d, 0, 16);
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/* Immediate address */
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static inline uint32_t LI (uint32_t opcode)
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{
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    return (opcode >> 0) & 0x03FFFFFC;
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}
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static inline uint32_t BD (uint32_t opcode)
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{
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    return (opcode >> 0) & 0xFFFC;
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}
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EXTRACT_HELPER(BO, 21, 5);
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EXTRACT_HELPER(BI, 16, 5);
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/* Absolute/relative address */
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EXTRACT_HELPER(AA, 1, 1);
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/* Link */
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EXTRACT_HELPER(LK, 0, 1);
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/* Create a mask between <start> and <end> bits */
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static inline uint32_t MASK (uint32_t start, uint32_t end)
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{
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    uint32_t ret;
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    ret = (((uint32_t)(-1)) >> (start)) ^ (((uint32_t)(-1) >> (end)) >> 1);
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    if (start > end)
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        return ~ret;
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    return ret;
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}
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#if defined(__APPLE__)
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#define OPCODES_SECTION \
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    __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (8) ))
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#else
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#define OPCODES_SECTION \
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    __attribute__ ((section(".opcodes"), unused, aligned (8) ))
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#endif
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#define GEN_OPCODE(name, op1, op2, op3, invl, _typ)                           \
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OPCODES_SECTION opcode_t opc_##name = {                                       \
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    .opc1 = op1,                                                              \
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    .opc2 = op2,                                                              \
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    .opc3 = op3,                                                              \
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    .pad  = { 0, },                                                           \
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    .handler = {                                                              \
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        .inval   = invl,                                                      \
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        .type = _typ,                                                         \
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        .handler = &gen_##name,                                               \
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    },                                                                        \
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}
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#define GEN_OPCODE_MARK(name)                                                 \
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OPCODES_SECTION opcode_t opc_##name = {                                       \
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    .opc1 = 0xFF,                                                             \
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    .opc2 = 0xFF,                                                             \
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    .opc3 = 0xFF,                                                             \
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    .pad  = { 0, },                                                           \
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    .handler = {                                                              \
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        .inval   = 0x00000000,                                                \
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        .type = 0x00,                                                         \
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        .handler = NULL,                                                      \
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    },                                                                        \
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}
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/* Start opcode list */
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GEN_OPCODE_MARK(start);
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/* Invalid instruction */
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GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
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{
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    RET_INVAL(ctx);
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}
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static opc_handler_t invalid_handler = {
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    .inval   = 0xFFFFFFFF,
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    .type    = PPC_NONE,
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    .handler = gen_invalid,
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};
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/***                           Integer arithmetic                          ***/
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#define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval)                       \
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GEN_HANDLER(name, opc1, opc2, opc3, inval, PPC_INTEGER)                       \
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{                                                                             \
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    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
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    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
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    gen_op_##name();                                                          \
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    if (Rc(ctx->opcode) != 0)                                                 \
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        gen_op_set_Rc0();                                                     \
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    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
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}
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#define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval)                     \
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GEN_HANDLER(name, opc1, opc2, opc3, inval, PPC_INTEGER)                       \
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{                                                                             \
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    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
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    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
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    gen_op_##name();                                                          \
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    if (Rc(ctx->opcode) != 0)                                                 \
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        gen_op_set_Rc0();                                                     \
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    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
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}
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#define __GEN_INT_ARITH1(name, opc1, opc2, opc3)                              \
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GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, PPC_INTEGER)                  \
359 79aceca5 bellard
{                                                                             \
360 79aceca5 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
361 79aceca5 bellard
    gen_op_##name();                                                          \
362 79aceca5 bellard
    if (Rc(ctx->opcode) != 0)                                                 \
363 79aceca5 bellard
        gen_op_set_Rc0();                                                     \
364 79aceca5 bellard
    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
365 79aceca5 bellard
}
366 79aceca5 bellard
#define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3)                            \
367 79aceca5 bellard
GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, PPC_INTEGER)                  \
368 79aceca5 bellard
{                                                                             \
369 79aceca5 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
370 79aceca5 bellard
    gen_op_##name();                                                          \
371 79aceca5 bellard
    if (Rc(ctx->opcode) != 0)                                                 \
372 18fba28c bellard
        gen_op_set_Rc0();                                                     \
373 79aceca5 bellard
    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
374 79aceca5 bellard
}
375 79aceca5 bellard
376 79aceca5 bellard
/* Two operands arithmetic functions */
377 79aceca5 bellard
#define GEN_INT_ARITH2(name, opc1, opc2, opc3)                                \
378 79aceca5 bellard
__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000)                          \
379 79aceca5 bellard
__GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000)
380 79aceca5 bellard
381 79aceca5 bellard
/* Two operands arithmetic functions with no overflow allowed */
382 79aceca5 bellard
#define GEN_INT_ARITHN(name, opc1, opc2, opc3)                                \
383 79aceca5 bellard
__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400)
384 79aceca5 bellard
385 79aceca5 bellard
/* One operand arithmetic functions */
386 79aceca5 bellard
#define GEN_INT_ARITH1(name, opc1, opc2, opc3)                                \
387 79aceca5 bellard
__GEN_INT_ARITH1(name, opc1, opc2, opc3)                                      \
388 79aceca5 bellard
__GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10)
389 79aceca5 bellard
390 79aceca5 bellard
/* add    add.    addo    addo.    */
391 79aceca5 bellard
GEN_INT_ARITH2 (add,    0x1F, 0x0A, 0x08);
392 79aceca5 bellard
/* addc   addc.   addco   addco.   */
393 79aceca5 bellard
GEN_INT_ARITH2 (addc,   0x1F, 0x0A, 0x00);
394 79aceca5 bellard
/* adde   adde.   addeo   addeo.   */
395 79aceca5 bellard
GEN_INT_ARITH2 (adde,   0x1F, 0x0A, 0x04);
396 79aceca5 bellard
/* addme  addme.  addmeo  addmeo.  */
397 79aceca5 bellard
GEN_INT_ARITH1 (addme,  0x1F, 0x0A, 0x07);
398 79aceca5 bellard
/* addze  addze.  addzeo  addzeo.  */
399 79aceca5 bellard
GEN_INT_ARITH1 (addze,  0x1F, 0x0A, 0x06);
400 79aceca5 bellard
/* divw   divw.   divwo   divwo.   */
401 79aceca5 bellard
GEN_INT_ARITH2 (divw,   0x1F, 0x0B, 0x0F);
402 79aceca5 bellard
/* divwu  divwu.  divwuo  divwuo.  */
403 79aceca5 bellard
GEN_INT_ARITH2 (divwu,  0x1F, 0x0B, 0x0E);
404 79aceca5 bellard
/* mulhw  mulhw.                   */
405 79aceca5 bellard
GEN_INT_ARITHN (mulhw,  0x1F, 0x0B, 0x02);
406 79aceca5 bellard
/* mulhwu mulhwu.                  */
407 79aceca5 bellard
GEN_INT_ARITHN (mulhwu, 0x1F, 0x0B, 0x00);
408 79aceca5 bellard
/* mullw  mullw.  mullwo  mullwo.  */
409 79aceca5 bellard
GEN_INT_ARITH2 (mullw,  0x1F, 0x0B, 0x07);
410 79aceca5 bellard
/* neg    neg.    nego    nego.    */
411 79aceca5 bellard
GEN_INT_ARITH1 (neg,    0x1F, 0x08, 0x03);
412 79aceca5 bellard
/* subf   subf.   subfo   subfo.   */
413 79aceca5 bellard
GEN_INT_ARITH2 (subf,   0x1F, 0x08, 0x01);
414 79aceca5 bellard
/* subfc  subfc.  subfco  subfco.  */
415 79aceca5 bellard
GEN_INT_ARITH2 (subfc,  0x1F, 0x08, 0x00);
416 79aceca5 bellard
/* subfe  subfe.  subfeo  subfeo.  */
417 79aceca5 bellard
GEN_INT_ARITH2 (subfe,  0x1F, 0x08, 0x04);
418 79aceca5 bellard
/* subfme subfme. subfmeo subfmeo. */
419 79aceca5 bellard
GEN_INT_ARITH1 (subfme, 0x1F, 0x08, 0x07);
420 79aceca5 bellard
/* subfze subfze. subfzeo subfzeo. */
421 79aceca5 bellard
GEN_INT_ARITH1 (subfze, 0x1F, 0x08, 0x06);
422 79aceca5 bellard
/* addi */
423 79aceca5 bellard
GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
424 79aceca5 bellard
{
425 79aceca5 bellard
    int32_t simm = SIMM(ctx->opcode);
426 79aceca5 bellard
427 79aceca5 bellard
    if (rA(ctx->opcode) == 0) {
428 79aceca5 bellard
        gen_op_set_T0(simm);
429 79aceca5 bellard
    } else {
430 79aceca5 bellard
        gen_op_load_gpr_T0(rA(ctx->opcode));
431 79aceca5 bellard
        gen_op_addi(simm);
432 79aceca5 bellard
    }
433 79aceca5 bellard
    gen_op_store_T0_gpr(rD(ctx->opcode));
434 79aceca5 bellard
}
435 79aceca5 bellard
/* addic */
436 79aceca5 bellard
GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
437 79aceca5 bellard
{
438 79aceca5 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));
439 79aceca5 bellard
    gen_op_addic(SIMM(ctx->opcode));
440 79aceca5 bellard
    gen_op_store_T0_gpr(rD(ctx->opcode));
441 79aceca5 bellard
}
442 79aceca5 bellard
/* addic. */
443 79aceca5 bellard
GEN_HANDLER(addic_, 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
444 79aceca5 bellard
{
445 79aceca5 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));
446 79aceca5 bellard
    gen_op_addic(SIMM(ctx->opcode));
447 79aceca5 bellard
    gen_op_set_Rc0();
448 79aceca5 bellard
    gen_op_store_T0_gpr(rD(ctx->opcode));
449 79aceca5 bellard
}
450 79aceca5 bellard
/* addis */
451 79aceca5 bellard
GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
452 79aceca5 bellard
{
453 79aceca5 bellard
    int32_t simm = SIMM(ctx->opcode);
454 79aceca5 bellard
455 79aceca5 bellard
    if (rA(ctx->opcode) == 0) {
456 79aceca5 bellard
        gen_op_set_T0(simm << 16);
457 79aceca5 bellard
    } else {
458 79aceca5 bellard
        gen_op_load_gpr_T0(rA(ctx->opcode));
459 79aceca5 bellard
        gen_op_addi(simm << 16);
460 79aceca5 bellard
    }
461 79aceca5 bellard
    gen_op_store_T0_gpr(rD(ctx->opcode));
462 79aceca5 bellard
}
463 79aceca5 bellard
/* mulli */
464 79aceca5 bellard
GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
465 79aceca5 bellard
{
466 79aceca5 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));
467 79aceca5 bellard
    gen_op_mulli(SIMM(ctx->opcode));
468 79aceca5 bellard
    gen_op_store_T0_gpr(rD(ctx->opcode));
469 79aceca5 bellard
}
470 79aceca5 bellard
/* subfic */
471 79aceca5 bellard
GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
472 79aceca5 bellard
{
473 79aceca5 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));
474 79aceca5 bellard
    gen_op_subfic(SIMM(ctx->opcode));
475 79aceca5 bellard
    gen_op_store_T0_gpr(rD(ctx->opcode));
476 79aceca5 bellard
}
477 79aceca5 bellard
478 79aceca5 bellard
/***                           Integer comparison                          ***/
479 79aceca5 bellard
#define GEN_CMP(name, opc)                                                    \
480 79aceca5 bellard
GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, PPC_INTEGER)                   \
481 79aceca5 bellard
{                                                                             \
482 79aceca5 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
483 79aceca5 bellard
    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
484 79aceca5 bellard
    gen_op_##name();                                                          \
485 79aceca5 bellard
    gen_op_store_T0_crf(crfD(ctx->opcode));                                   \
486 79aceca5 bellard
}
487 79aceca5 bellard
488 79aceca5 bellard
/* cmp */
489 79aceca5 bellard
GEN_CMP(cmp, 0x00);
490 79aceca5 bellard
/* cmpi */
491 79aceca5 bellard
GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
492 79aceca5 bellard
{
493 79aceca5 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));
494 79aceca5 bellard
    gen_op_cmpi(SIMM(ctx->opcode));
495 79aceca5 bellard
    gen_op_store_T0_crf(crfD(ctx->opcode));
496 79aceca5 bellard
}
497 79aceca5 bellard
/* cmpl */
498 79aceca5 bellard
GEN_CMP(cmpl, 0x01);
499 79aceca5 bellard
/* cmpli */
500 79aceca5 bellard
GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
501 79aceca5 bellard
{
502 79aceca5 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));
503 79aceca5 bellard
    gen_op_cmpli(UIMM(ctx->opcode));
504 79aceca5 bellard
    gen_op_store_T0_crf(crfD(ctx->opcode));
505 79aceca5 bellard
}
506 79aceca5 bellard
507 79aceca5 bellard
/***                            Integer logical                            ***/
508 79aceca5 bellard
#define __GEN_LOGICAL2(name, opc2, opc3)                                      \
509 79aceca5 bellard
GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, PPC_INTEGER)                  \
510 79aceca5 bellard
{                                                                             \
511 79aceca5 bellard
    gen_op_load_gpr_T0(rS(ctx->opcode));                                      \
512 79aceca5 bellard
    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
513 79aceca5 bellard
    gen_op_##name();                                                          \
514 79aceca5 bellard
    if (Rc(ctx->opcode) != 0)                                                 \
515 79aceca5 bellard
        gen_op_set_Rc0();                                                     \
516 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
517 79aceca5 bellard
}
518 79aceca5 bellard
#define GEN_LOGICAL2(name, opc)                                               \
519 79aceca5 bellard
__GEN_LOGICAL2(name, 0x1C, opc)
520 79aceca5 bellard
521 79aceca5 bellard
#define GEN_LOGICAL1(name, opc)                                               \
522 79aceca5 bellard
GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, PPC_INTEGER)                   \
523 79aceca5 bellard
{                                                                             \
524 79aceca5 bellard
    gen_op_load_gpr_T0(rS(ctx->opcode));                                      \
525 79aceca5 bellard
    gen_op_##name();                                                          \
526 79aceca5 bellard
    if (Rc(ctx->opcode) != 0)                                                 \
527 79aceca5 bellard
        gen_op_set_Rc0();                                                     \
528 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
529 79aceca5 bellard
}
530 79aceca5 bellard
531 79aceca5 bellard
/* and & and. */
532 79aceca5 bellard
GEN_LOGICAL2(and, 0x00);
533 79aceca5 bellard
/* andc & andc. */
534 79aceca5 bellard
GEN_LOGICAL2(andc, 0x01);
535 79aceca5 bellard
/* andi. */
536 79aceca5 bellard
GEN_HANDLER(andi_, 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
537 79aceca5 bellard
{
538 79aceca5 bellard
    gen_op_load_gpr_T0(rS(ctx->opcode));
539 79aceca5 bellard
    gen_op_andi_(UIMM(ctx->opcode));
540 79aceca5 bellard
    gen_op_set_Rc0();
541 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));
542 79aceca5 bellard
}
543 79aceca5 bellard
/* andis. */
544 79aceca5 bellard
GEN_HANDLER(andis_, 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
545 79aceca5 bellard
{
546 79aceca5 bellard
    gen_op_load_gpr_T0(rS(ctx->opcode));
547 79aceca5 bellard
    gen_op_andi_(UIMM(ctx->opcode) << 16);
548 79aceca5 bellard
    gen_op_set_Rc0();
549 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));
550 79aceca5 bellard
}
551 79aceca5 bellard
552 79aceca5 bellard
/* cntlzw */
553 79aceca5 bellard
GEN_LOGICAL1(cntlzw, 0x00);
554 79aceca5 bellard
/* eqv & eqv. */
555 79aceca5 bellard
GEN_LOGICAL2(eqv, 0x08);
556 79aceca5 bellard
/* extsb & extsb. */
557 79aceca5 bellard
GEN_LOGICAL1(extsb, 0x1D);
558 79aceca5 bellard
/* extsh & extsh. */
559 79aceca5 bellard
GEN_LOGICAL1(extsh, 0x1C);
560 79aceca5 bellard
/* nand & nand. */
561 79aceca5 bellard
GEN_LOGICAL2(nand, 0x0E);
562 79aceca5 bellard
/* nor & nor. */
563 79aceca5 bellard
GEN_LOGICAL2(nor, 0x03);
564 9a64fbe4 bellard
565 79aceca5 bellard
/* or & or. */
566 9a64fbe4 bellard
GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
567 9a64fbe4 bellard
{
568 9a64fbe4 bellard
    gen_op_load_gpr_T0(rS(ctx->opcode));
569 9a64fbe4 bellard
    /* Optimisation for mr case */
570 9a64fbe4 bellard
    if (rS(ctx->opcode) != rB(ctx->opcode)) {
571 9a64fbe4 bellard
        gen_op_load_gpr_T1(rB(ctx->opcode));
572 9a64fbe4 bellard
        gen_op_or();
573 9a64fbe4 bellard
    }
574 9a64fbe4 bellard
    if (Rc(ctx->opcode) != 0)
575 9a64fbe4 bellard
        gen_op_set_Rc0();
576 9a64fbe4 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));
577 9a64fbe4 bellard
}
578 9a64fbe4 bellard
579 79aceca5 bellard
/* orc & orc. */
580 79aceca5 bellard
GEN_LOGICAL2(orc, 0x0C);
581 79aceca5 bellard
/* xor & xor. */
582 9a64fbe4 bellard
GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
583 9a64fbe4 bellard
{
584 9a64fbe4 bellard
    gen_op_load_gpr_T0(rS(ctx->opcode));
585 9a64fbe4 bellard
    /* Optimisation for "set to zero" case */
586 9a64fbe4 bellard
    if (rS(ctx->opcode) != rB(ctx->opcode)) {
587 9a64fbe4 bellard
        gen_op_load_gpr_T1(rB(ctx->opcode));
588 9a64fbe4 bellard
        gen_op_xor();
589 9a64fbe4 bellard
    } else {
590 9a64fbe4 bellard
        gen_op_set_T0(0);
591 9a64fbe4 bellard
    }
592 9a64fbe4 bellard
    if (Rc(ctx->opcode) != 0)
593 9a64fbe4 bellard
        gen_op_set_Rc0();
594 9a64fbe4 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));
595 9a64fbe4 bellard
}
596 79aceca5 bellard
/* ori */
597 79aceca5 bellard
GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
598 79aceca5 bellard
{
599 79aceca5 bellard
    uint32_t uimm = UIMM(ctx->opcode);
600 79aceca5 bellard
601 9a64fbe4 bellard
    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
602 9a64fbe4 bellard
        /* NOP */
603 9a64fbe4 bellard
        return;
604 79aceca5 bellard
        }
605 79aceca5 bellard
        gen_op_load_gpr_T0(rS(ctx->opcode));
606 9a64fbe4 bellard
    if (uimm != 0)
607 79aceca5 bellard
        gen_op_ori(uimm);
608 79aceca5 bellard
        gen_op_store_T0_gpr(rA(ctx->opcode));
609 79aceca5 bellard
}
610 79aceca5 bellard
/* oris */
611 79aceca5 bellard
GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
612 79aceca5 bellard
{
613 79aceca5 bellard
    uint32_t uimm = UIMM(ctx->opcode);
614 79aceca5 bellard
615 9a64fbe4 bellard
    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
616 9a64fbe4 bellard
        /* NOP */
617 9a64fbe4 bellard
        return;
618 79aceca5 bellard
        }
619 79aceca5 bellard
        gen_op_load_gpr_T0(rS(ctx->opcode));
620 9a64fbe4 bellard
    if (uimm != 0)
621 79aceca5 bellard
        gen_op_ori(uimm << 16);
622 79aceca5 bellard
        gen_op_store_T0_gpr(rA(ctx->opcode));
623 79aceca5 bellard
}
624 79aceca5 bellard
/* xori */
625 79aceca5 bellard
GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
626 79aceca5 bellard
{
627 9a64fbe4 bellard
    uint32_t uimm = UIMM(ctx->opcode);
628 9a64fbe4 bellard
629 9a64fbe4 bellard
    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
630 9a64fbe4 bellard
        /* NOP */
631 9a64fbe4 bellard
        return;
632 9a64fbe4 bellard
    }
633 79aceca5 bellard
    gen_op_load_gpr_T0(rS(ctx->opcode));
634 9a64fbe4 bellard
    if (uimm != 0)
635 4b3686fa bellard
    gen_op_xori(uimm);
636 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));
637 79aceca5 bellard
}
638 79aceca5 bellard
639 79aceca5 bellard
/* xoris */
640 79aceca5 bellard
GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
641 79aceca5 bellard
{
642 9a64fbe4 bellard
    uint32_t uimm = UIMM(ctx->opcode);
643 9a64fbe4 bellard
644 9a64fbe4 bellard
    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
645 9a64fbe4 bellard
        /* NOP */
646 9a64fbe4 bellard
        return;
647 9a64fbe4 bellard
    }
648 79aceca5 bellard
    gen_op_load_gpr_T0(rS(ctx->opcode));
649 9a64fbe4 bellard
    if (uimm != 0)
650 4b3686fa bellard
    gen_op_xori(uimm << 16);
651 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));
652 79aceca5 bellard
}
653 79aceca5 bellard
654 79aceca5 bellard
/***                             Integer rotate                            ***/
655 79aceca5 bellard
/* rlwimi & rlwimi. */
656 79aceca5 bellard
GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
657 79aceca5 bellard
{
658 79aceca5 bellard
    uint32_t mb, me;
659 79aceca5 bellard
660 79aceca5 bellard
    mb = MB(ctx->opcode);
661 79aceca5 bellard
    me = ME(ctx->opcode);
662 79aceca5 bellard
    gen_op_load_gpr_T0(rS(ctx->opcode));
663 fb0eaffc bellard
    gen_op_load_gpr_T1(rA(ctx->opcode));
664 79aceca5 bellard
    gen_op_rlwimi(SH(ctx->opcode), MASK(mb, me), ~MASK(mb, me));
665 79aceca5 bellard
    if (Rc(ctx->opcode) != 0)
666 79aceca5 bellard
        gen_op_set_Rc0();
667 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));
668 79aceca5 bellard
}
669 79aceca5 bellard
/* rlwinm & rlwinm. */
670 79aceca5 bellard
GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
671 79aceca5 bellard
{
672 79aceca5 bellard
    uint32_t mb, me, sh;
673 79aceca5 bellard
    
674 79aceca5 bellard
    sh = SH(ctx->opcode);
675 79aceca5 bellard
    mb = MB(ctx->opcode);
676 79aceca5 bellard
    me = ME(ctx->opcode);
677 79aceca5 bellard
    gen_op_load_gpr_T0(rS(ctx->opcode));
678 4b3686fa bellard
#if 1 // TRY
679 4b3686fa bellard
    if (sh == 0) {
680 4b3686fa bellard
        gen_op_andi_(MASK(mb, me));
681 4b3686fa bellard
        goto store;
682 4b3686fa bellard
    }
683 4b3686fa bellard
#endif
684 79aceca5 bellard
    if (mb == 0) {
685 79aceca5 bellard
        if (me == 31) {
686 79aceca5 bellard
            gen_op_rotlwi(sh);
687 79aceca5 bellard
            goto store;
688 4b3686fa bellard
#if 0
689 79aceca5 bellard
        } else if (me == (31 - sh)) {
690 79aceca5 bellard
            gen_op_slwi(sh);
691 79aceca5 bellard
            goto store;
692 4b3686fa bellard
#endif
693 79aceca5 bellard
        }
694 79aceca5 bellard
    } else if (me == 31) {
695 4b3686fa bellard
#if 0
696 79aceca5 bellard
        if (sh == (32 - mb)) {
697 79aceca5 bellard
            gen_op_srwi(mb);
698 79aceca5 bellard
            goto store;
699 79aceca5 bellard
        }
700 4b3686fa bellard
#endif
701 79aceca5 bellard
    }
702 79aceca5 bellard
    gen_op_rlwinm(sh, MASK(mb, me));
703 79aceca5 bellard
store:
704 79aceca5 bellard
    if (Rc(ctx->opcode) != 0)
705 79aceca5 bellard
        gen_op_set_Rc0();
706 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));
707 79aceca5 bellard
}
708 79aceca5 bellard
/* rlwnm & rlwnm. */
709 79aceca5 bellard
GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
710 79aceca5 bellard
{
711 79aceca5 bellard
    uint32_t mb, me;
712 79aceca5 bellard
713 79aceca5 bellard
    mb = MB(ctx->opcode);
714 79aceca5 bellard
    me = ME(ctx->opcode);
715 79aceca5 bellard
    gen_op_load_gpr_T0(rS(ctx->opcode));
716 79aceca5 bellard
    gen_op_load_gpr_T1(rB(ctx->opcode));
717 79aceca5 bellard
    if (mb == 0 && me == 31) {
718 79aceca5 bellard
        gen_op_rotl();
719 79aceca5 bellard
    } else
720 79aceca5 bellard
    {
721 79aceca5 bellard
        gen_op_rlwnm(MASK(mb, me));
722 79aceca5 bellard
    }
723 79aceca5 bellard
    if (Rc(ctx->opcode) != 0)
724 79aceca5 bellard
        gen_op_set_Rc0();
725 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));
726 79aceca5 bellard
}
727 79aceca5 bellard
728 79aceca5 bellard
/***                             Integer shift                             ***/
729 79aceca5 bellard
/* slw & slw. */
730 79aceca5 bellard
__GEN_LOGICAL2(slw, 0x18, 0x00);
731 79aceca5 bellard
/* sraw & sraw. */
732 79aceca5 bellard
__GEN_LOGICAL2(sraw, 0x18, 0x18);
733 79aceca5 bellard
/* srawi & srawi. */
734 79aceca5 bellard
GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
735 79aceca5 bellard
{
736 79aceca5 bellard
    gen_op_load_gpr_T0(rS(ctx->opcode));
737 4ecc3190 bellard
    if (SH(ctx->opcode) != 0)
738 79aceca5 bellard
    gen_op_srawi(SH(ctx->opcode), MASK(32 - SH(ctx->opcode), 31));
739 79aceca5 bellard
    if (Rc(ctx->opcode) != 0)
740 79aceca5 bellard
        gen_op_set_Rc0();
741 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));
742 79aceca5 bellard
}
743 79aceca5 bellard
/* srw & srw. */
744 79aceca5 bellard
__GEN_LOGICAL2(srw, 0x18, 0x10);
745 79aceca5 bellard
746 79aceca5 bellard
/***                       Floating-Point arithmetic                       ***/
747 4ecc3190 bellard
#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat)                           \
748 9a64fbe4 bellard
GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, PPC_FLOAT)                   \
749 9a64fbe4 bellard
{                                                                             \
750 3cc62370 bellard
    if (!ctx->fpu_enabled) {                                                  \
751 3cc62370 bellard
        RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \
752 3cc62370 bellard
        return;                                                               \
753 3cc62370 bellard
    }                                                                         \
754 9a64fbe4 bellard
    gen_op_reset_scrfx();                                                     \
755 9a64fbe4 bellard
    gen_op_load_fpr_FT0(rA(ctx->opcode));                                     \
756 9a64fbe4 bellard
    gen_op_load_fpr_FT1(rC(ctx->opcode));                                     \
757 9a64fbe4 bellard
    gen_op_load_fpr_FT2(rB(ctx->opcode));                                     \
758 4ecc3190 bellard
    gen_op_f##op();                                                           \
759 4ecc3190 bellard
    if (isfloat) {                                                            \
760 4ecc3190 bellard
        gen_op_frsp();                                                        \
761 4ecc3190 bellard
    }                                                                         \
762 9a64fbe4 bellard
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
763 9a64fbe4 bellard
    if (Rc(ctx->opcode))                                                      \
764 9a64fbe4 bellard
        gen_op_set_Rc1();                                                     \
765 9a64fbe4 bellard
}
766 9a64fbe4 bellard
767 9a64fbe4 bellard
#define GEN_FLOAT_ACB(name, op2)                                              \
768 4ecc3190 bellard
_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0);                                     \
769 4ecc3190 bellard
_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1);
770 9a64fbe4 bellard
771 4ecc3190 bellard
#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat)                     \
772 9a64fbe4 bellard
GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT)                        \
773 9a64fbe4 bellard
{                                                                             \
774 3cc62370 bellard
    if (!ctx->fpu_enabled) {                                                  \
775 3cc62370 bellard
        RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \
776 3cc62370 bellard
        return;                                                               \
777 3cc62370 bellard
    }                                                                         \
778 9a64fbe4 bellard
    gen_op_reset_scrfx();                                                     \
779 9a64fbe4 bellard
    gen_op_load_fpr_FT0(rA(ctx->opcode));                                     \
780 9a64fbe4 bellard
    gen_op_load_fpr_FT1(rB(ctx->opcode));                                     \
781 4ecc3190 bellard
    gen_op_f##op();                                                           \
782 4ecc3190 bellard
    if (isfloat) {                                                            \
783 4ecc3190 bellard
        gen_op_frsp();                                                        \
784 4ecc3190 bellard
    }                                                                         \
785 9a64fbe4 bellard
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
786 9a64fbe4 bellard
    if (Rc(ctx->opcode))                                                      \
787 9a64fbe4 bellard
        gen_op_set_Rc1();                                                     \
788 9a64fbe4 bellard
}
789 9a64fbe4 bellard
#define GEN_FLOAT_AB(name, op2, inval)                                        \
790 4ecc3190 bellard
_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0);                               \
791 4ecc3190 bellard
_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1);
792 9a64fbe4 bellard
793 4ecc3190 bellard
#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat)                     \
794 9a64fbe4 bellard
GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT)                        \
795 9a64fbe4 bellard
{                                                                             \
796 3cc62370 bellard
    if (!ctx->fpu_enabled) {                                                  \
797 3cc62370 bellard
        RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \
798 3cc62370 bellard
        return;                                                               \
799 3cc62370 bellard
    }                                                                         \
800 9a64fbe4 bellard
    gen_op_reset_scrfx();                                                     \
801 9a64fbe4 bellard
    gen_op_load_fpr_FT0(rA(ctx->opcode));                                     \
802 9a64fbe4 bellard
    gen_op_load_fpr_FT1(rC(ctx->opcode));                                     \
803 4ecc3190 bellard
    gen_op_f##op();                                                           \
804 4ecc3190 bellard
    if (isfloat) {                                                            \
805 4ecc3190 bellard
        gen_op_frsp();                                                        \
806 4ecc3190 bellard
    }                                                                         \
807 9a64fbe4 bellard
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
808 9a64fbe4 bellard
    if (Rc(ctx->opcode))                                                      \
809 9a64fbe4 bellard
        gen_op_set_Rc1();                                                     \
810 9a64fbe4 bellard
}
811 9a64fbe4 bellard
#define GEN_FLOAT_AC(name, op2, inval)                                        \
812 4ecc3190 bellard
_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0);                               \
813 4ecc3190 bellard
_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1);
814 9a64fbe4 bellard
815 9a64fbe4 bellard
#define GEN_FLOAT_B(name, op2, op3)                                           \
816 9a64fbe4 bellard
GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, PPC_FLOAT)                   \
817 9a64fbe4 bellard
{                                                                             \
818 3cc62370 bellard
    if (!ctx->fpu_enabled) {                                                  \
819 3cc62370 bellard
        RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \
820 3cc62370 bellard
        return;                                                               \
821 3cc62370 bellard
    }                                                                         \
822 9a64fbe4 bellard
    gen_op_reset_scrfx();                                                     \
823 9a64fbe4 bellard
    gen_op_load_fpr_FT0(rB(ctx->opcode));                                     \
824 9a64fbe4 bellard
    gen_op_f##name();                                                         \
825 9a64fbe4 bellard
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
826 9a64fbe4 bellard
    if (Rc(ctx->opcode))                                                      \
827 9a64fbe4 bellard
        gen_op_set_Rc1();                                                     \
828 79aceca5 bellard
}
829 79aceca5 bellard
830 4ecc3190 bellard
#define GEN_FLOAT_BS(name, op1, op2)                                          \
831 4ecc3190 bellard
GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, PPC_FLOAT)                   \
832 9a64fbe4 bellard
{                                                                             \
833 3cc62370 bellard
    if (!ctx->fpu_enabled) {                                                  \
834 3cc62370 bellard
        RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \
835 3cc62370 bellard
        return;                                                               \
836 3cc62370 bellard
    }                                                                         \
837 9a64fbe4 bellard
    gen_op_reset_scrfx();                                                     \
838 9a64fbe4 bellard
    gen_op_load_fpr_FT0(rB(ctx->opcode));                                     \
839 9a64fbe4 bellard
    gen_op_f##name();                                                         \
840 9a64fbe4 bellard
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
841 9a64fbe4 bellard
    if (Rc(ctx->opcode))                                                      \
842 9a64fbe4 bellard
        gen_op_set_Rc1();                                                     \
843 79aceca5 bellard
}
844 79aceca5 bellard
845 9a64fbe4 bellard
/* fadd - fadds */
846 9a64fbe4 bellard
GEN_FLOAT_AB(add, 0x15, 0x000007C0);
847 4ecc3190 bellard
/* fdiv - fdivs */
848 9a64fbe4 bellard
GEN_FLOAT_AB(div, 0x12, 0x000007C0);
849 4ecc3190 bellard
/* fmul - fmuls */
850 9a64fbe4 bellard
GEN_FLOAT_AC(mul, 0x19, 0x0000F800);
851 79aceca5 bellard
852 79aceca5 bellard
/* fres */
853 4ecc3190 bellard
GEN_FLOAT_BS(res, 0x3B, 0x18);
854 79aceca5 bellard
855 79aceca5 bellard
/* frsqrte */
856 4ecc3190 bellard
GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A);
857 79aceca5 bellard
858 79aceca5 bellard
/* fsel */
859 4ecc3190 bellard
_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0);
860 4ecc3190 bellard
/* fsub - fsubs */
861 9a64fbe4 bellard
GEN_FLOAT_AB(sub, 0x14, 0x000007C0);
862 79aceca5 bellard
/* Optional: */
863 79aceca5 bellard
/* fsqrt */
864 c7d344af bellard
GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_OPT)
865 c7d344af bellard
{
866 c7d344af bellard
    if (!ctx->fpu_enabled) {
867 c7d344af bellard
        RET_EXCP(ctx, EXCP_NO_FP, 0);
868 c7d344af bellard
        return;
869 c7d344af bellard
    }
870 c7d344af bellard
    gen_op_reset_scrfx();
871 c7d344af bellard
    gen_op_load_fpr_FT0(rB(ctx->opcode));
872 c7d344af bellard
    gen_op_fsqrt();
873 c7d344af bellard
    gen_op_store_FT0_fpr(rD(ctx->opcode));
874 c7d344af bellard
    if (Rc(ctx->opcode))
875 c7d344af bellard
        gen_op_set_Rc1();
876 c7d344af bellard
}
877 79aceca5 bellard
878 9a64fbe4 bellard
GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_OPT)
879 79aceca5 bellard
{
880 3cc62370 bellard
    if (!ctx->fpu_enabled) {
881 3cc62370 bellard
        RET_EXCP(ctx, EXCP_NO_FP, 0);
882 3cc62370 bellard
        return;
883 3cc62370 bellard
    }
884 9a64fbe4 bellard
    gen_op_reset_scrfx();
885 9a64fbe4 bellard
    gen_op_load_fpr_FT0(rB(ctx->opcode));
886 4ecc3190 bellard
    gen_op_fsqrt();
887 4ecc3190 bellard
    gen_op_frsp();
888 9a64fbe4 bellard
    gen_op_store_FT0_fpr(rD(ctx->opcode));
889 9a64fbe4 bellard
    if (Rc(ctx->opcode))
890 9a64fbe4 bellard
        gen_op_set_Rc1();
891 79aceca5 bellard
}
892 79aceca5 bellard
893 79aceca5 bellard
/***                     Floating-Point multiply-and-add                   ***/
894 4ecc3190 bellard
/* fmadd - fmadds */
895 9a64fbe4 bellard
GEN_FLOAT_ACB(madd, 0x1D);
896 4ecc3190 bellard
/* fmsub - fmsubs */
897 9a64fbe4 bellard
GEN_FLOAT_ACB(msub, 0x1C);
898 4ecc3190 bellard
/* fnmadd - fnmadds */
899 9a64fbe4 bellard
GEN_FLOAT_ACB(nmadd, 0x1F);
900 4ecc3190 bellard
/* fnmsub - fnmsubs */
901 9a64fbe4 bellard
GEN_FLOAT_ACB(nmsub, 0x1E);
902 79aceca5 bellard
903 79aceca5 bellard
/***                     Floating-Point round & convert                    ***/
904 79aceca5 bellard
/* fctiw */
905 9a64fbe4 bellard
GEN_FLOAT_B(ctiw, 0x0E, 0x00);
906 79aceca5 bellard
/* fctiwz */
907 9a64fbe4 bellard
GEN_FLOAT_B(ctiwz, 0x0F, 0x00);
908 79aceca5 bellard
/* frsp */
909 9a64fbe4 bellard
GEN_FLOAT_B(rsp, 0x0C, 0x00);
910 79aceca5 bellard
911 79aceca5 bellard
/***                         Floating-Point compare                        ***/
912 79aceca5 bellard
/* fcmpo */
913 79aceca5 bellard
GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
914 79aceca5 bellard
{
915 3cc62370 bellard
    if (!ctx->fpu_enabled) {
916 3cc62370 bellard
        RET_EXCP(ctx, EXCP_NO_FP, 0);
917 3cc62370 bellard
        return;
918 3cc62370 bellard
    }
919 9a64fbe4 bellard
    gen_op_reset_scrfx();
920 9a64fbe4 bellard
    gen_op_load_fpr_FT0(rA(ctx->opcode));
921 9a64fbe4 bellard
    gen_op_load_fpr_FT1(rB(ctx->opcode));
922 9a64fbe4 bellard
    gen_op_fcmpo();
923 9a64fbe4 bellard
    gen_op_store_T0_crf(crfD(ctx->opcode));
924 79aceca5 bellard
}
925 79aceca5 bellard
926 79aceca5 bellard
/* fcmpu */
927 79aceca5 bellard
GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
928 79aceca5 bellard
{
929 3cc62370 bellard
    if (!ctx->fpu_enabled) {
930 3cc62370 bellard
        RET_EXCP(ctx, EXCP_NO_FP, 0);
931 3cc62370 bellard
        return;
932 3cc62370 bellard
    }
933 9a64fbe4 bellard
    gen_op_reset_scrfx();
934 9a64fbe4 bellard
    gen_op_load_fpr_FT0(rA(ctx->opcode));
935 9a64fbe4 bellard
    gen_op_load_fpr_FT1(rB(ctx->opcode));
936 9a64fbe4 bellard
    gen_op_fcmpu();
937 9a64fbe4 bellard
    gen_op_store_T0_crf(crfD(ctx->opcode));
938 79aceca5 bellard
}
939 79aceca5 bellard
940 9a64fbe4 bellard
/***                         Floating-point move                           ***/
941 9a64fbe4 bellard
/* fabs */
942 9a64fbe4 bellard
GEN_FLOAT_B(abs, 0x08, 0x08);
943 9a64fbe4 bellard
944 9a64fbe4 bellard
/* fmr  - fmr. */
945 9a64fbe4 bellard
GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
946 9a64fbe4 bellard
{
947 3cc62370 bellard
    if (!ctx->fpu_enabled) {
948 3cc62370 bellard
        RET_EXCP(ctx, EXCP_NO_FP, 0);
949 3cc62370 bellard
        return;
950 3cc62370 bellard
    }
951 9a64fbe4 bellard
    gen_op_reset_scrfx();
952 9a64fbe4 bellard
    gen_op_load_fpr_FT0(rB(ctx->opcode));
953 9a64fbe4 bellard
    gen_op_store_FT0_fpr(rD(ctx->opcode));
954 9a64fbe4 bellard
    if (Rc(ctx->opcode))
955 9a64fbe4 bellard
        gen_op_set_Rc1();
956 9a64fbe4 bellard
}
957 9a64fbe4 bellard
958 9a64fbe4 bellard
/* fnabs */
959 9a64fbe4 bellard
GEN_FLOAT_B(nabs, 0x08, 0x04);
960 9a64fbe4 bellard
/* fneg */
961 9a64fbe4 bellard
GEN_FLOAT_B(neg, 0x08, 0x01);
962 9a64fbe4 bellard
963 79aceca5 bellard
/***                  Floating-Point status & ctrl register                ***/
964 79aceca5 bellard
/* mcrfs */
965 79aceca5 bellard
GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
966 79aceca5 bellard
{
967 3cc62370 bellard
    if (!ctx->fpu_enabled) {
968 3cc62370 bellard
        RET_EXCP(ctx, EXCP_NO_FP, 0);
969 3cc62370 bellard
        return;
970 3cc62370 bellard
    }
971 fb0eaffc bellard
    gen_op_load_fpscr_T0(crfS(ctx->opcode));
972 fb0eaffc bellard
    gen_op_store_T0_crf(crfD(ctx->opcode));
973 fb0eaffc bellard
    gen_op_clear_fpscr(crfS(ctx->opcode));
974 79aceca5 bellard
}
975 79aceca5 bellard
976 79aceca5 bellard
/* mffs */
977 79aceca5 bellard
GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
978 79aceca5 bellard
{
979 3cc62370 bellard
    if (!ctx->fpu_enabled) {
980 3cc62370 bellard
        RET_EXCP(ctx, EXCP_NO_FP, 0);
981 3cc62370 bellard
        return;
982 3cc62370 bellard
    }
983 28b6751f bellard
    gen_op_load_fpscr();
984 fb0eaffc bellard
    gen_op_store_FT0_fpr(rD(ctx->opcode));
985 fb0eaffc bellard
    if (Rc(ctx->opcode))
986 fb0eaffc bellard
        gen_op_set_Rc1();
987 79aceca5 bellard
}
988 79aceca5 bellard
989 79aceca5 bellard
/* mtfsb0 */
990 79aceca5 bellard
GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
991 79aceca5 bellard
{
992 fb0eaffc bellard
    uint8_t crb;
993 fb0eaffc bellard
    
994 3cc62370 bellard
    if (!ctx->fpu_enabled) {
995 3cc62370 bellard
        RET_EXCP(ctx, EXCP_NO_FP, 0);
996 3cc62370 bellard
        return;
997 3cc62370 bellard
    }
998 fb0eaffc bellard
    crb = crbD(ctx->opcode) >> 2;
999 fb0eaffc bellard
    gen_op_load_fpscr_T0(crb);
1000 fb0eaffc bellard
    gen_op_andi_(~(1 << (crbD(ctx->opcode) & 0x03)));
1001 fb0eaffc bellard
    gen_op_store_T0_fpscr(crb);
1002 fb0eaffc bellard
    if (Rc(ctx->opcode))
1003 fb0eaffc bellard
        gen_op_set_Rc1();
1004 79aceca5 bellard
}
1005 79aceca5 bellard
1006 79aceca5 bellard
/* mtfsb1 */
1007 79aceca5 bellard
GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
1008 79aceca5 bellard
{
1009 fb0eaffc bellard
    uint8_t crb;
1010 fb0eaffc bellard
    
1011 3cc62370 bellard
    if (!ctx->fpu_enabled) {
1012 3cc62370 bellard
        RET_EXCP(ctx, EXCP_NO_FP, 0);
1013 3cc62370 bellard
        return;
1014 3cc62370 bellard
    }
1015 fb0eaffc bellard
    crb = crbD(ctx->opcode) >> 2;
1016 fb0eaffc bellard
    gen_op_load_fpscr_T0(crb);
1017 fb0eaffc bellard
    gen_op_ori(1 << (crbD(ctx->opcode) & 0x03));
1018 fb0eaffc bellard
    gen_op_store_T0_fpscr(crb);
1019 fb0eaffc bellard
    if (Rc(ctx->opcode))
1020 fb0eaffc bellard
        gen_op_set_Rc1();
1021 79aceca5 bellard
}
1022 79aceca5 bellard
1023 79aceca5 bellard
/* mtfsf */
1024 79aceca5 bellard
GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
1025 79aceca5 bellard
{
1026 3cc62370 bellard
    if (!ctx->fpu_enabled) {
1027 3cc62370 bellard
        RET_EXCP(ctx, EXCP_NO_FP, 0);
1028 3cc62370 bellard
        return;
1029 3cc62370 bellard
    }
1030 fb0eaffc bellard
    gen_op_load_fpr_FT0(rB(ctx->opcode));
1031 28b6751f bellard
    gen_op_store_fpscr(FM(ctx->opcode));
1032 fb0eaffc bellard
    if (Rc(ctx->opcode))
1033 fb0eaffc bellard
        gen_op_set_Rc1();
1034 79aceca5 bellard
}
1035 79aceca5 bellard
1036 79aceca5 bellard
/* mtfsfi */
1037 79aceca5 bellard
GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
1038 79aceca5 bellard
{
1039 3cc62370 bellard
    if (!ctx->fpu_enabled) {
1040 3cc62370 bellard
        RET_EXCP(ctx, EXCP_NO_FP, 0);
1041 3cc62370 bellard
        return;
1042 3cc62370 bellard
    }
1043 fb0eaffc bellard
    gen_op_store_T0_fpscri(crbD(ctx->opcode) >> 2, FPIMM(ctx->opcode));
1044 fb0eaffc bellard
    if (Rc(ctx->opcode))
1045 fb0eaffc bellard
        gen_op_set_Rc1();
1046 79aceca5 bellard
}
1047 79aceca5 bellard
1048 79aceca5 bellard
/***                             Integer load                              ***/
1049 111bfab3 bellard
#define op_ldst(name)        (*gen_op_##name[ctx->mem_idx])()
1050 9a64fbe4 bellard
#if defined(CONFIG_USER_ONLY)
1051 111bfab3 bellard
#define OP_LD_TABLE(width)                                                    \
1052 111bfab3 bellard
static GenOpFunc *gen_op_l##width[] = {                                       \
1053 111bfab3 bellard
    &gen_op_l##width##_raw,                                                   \
1054 111bfab3 bellard
    &gen_op_l##width##_le_raw,                                                \
1055 111bfab3 bellard
};
1056 111bfab3 bellard
#define OP_ST_TABLE(width)                                                    \
1057 111bfab3 bellard
static GenOpFunc *gen_op_st##width[] = {                                      \
1058 111bfab3 bellard
    &gen_op_st##width##_raw,                                                  \
1059 111bfab3 bellard
    &gen_op_st##width##_le_raw,                                               \
1060 111bfab3 bellard
};
1061 111bfab3 bellard
/* Byte access routine are endian safe */
1062 111bfab3 bellard
#define gen_op_stb_le_raw gen_op_stb_raw
1063 111bfab3 bellard
#define gen_op_lbz_le_raw gen_op_lbz_raw
1064 9a64fbe4 bellard
#else
1065 9a64fbe4 bellard
#define OP_LD_TABLE(width)                                                    \
1066 9a64fbe4 bellard
static GenOpFunc *gen_op_l##width[] = {                                       \
1067 9a64fbe4 bellard
    &gen_op_l##width##_user,                                                  \
1068 111bfab3 bellard
    &gen_op_l##width##_le_user,                                               \
1069 9a64fbe4 bellard
    &gen_op_l##width##_kernel,                                                \
1070 111bfab3 bellard
    &gen_op_l##width##_le_kernel,                                             \
1071 111bfab3 bellard
};
1072 9a64fbe4 bellard
#define OP_ST_TABLE(width)                                                    \
1073 9a64fbe4 bellard
static GenOpFunc *gen_op_st##width[] = {                                      \
1074 9a64fbe4 bellard
    &gen_op_st##width##_user,                                                 \
1075 111bfab3 bellard
    &gen_op_st##width##_le_user,                                              \
1076 9a64fbe4 bellard
    &gen_op_st##width##_kernel,                                               \
1077 111bfab3 bellard
    &gen_op_st##width##_le_kernel,                                            \
1078 111bfab3 bellard
};
1079 111bfab3 bellard
/* Byte access routine are endian safe */
1080 111bfab3 bellard
#define gen_op_stb_le_user gen_op_stb_user
1081 111bfab3 bellard
#define gen_op_lbz_le_user gen_op_lbz_user
1082 111bfab3 bellard
#define gen_op_stb_le_kernel gen_op_stb_kernel
1083 111bfab3 bellard
#define gen_op_lbz_le_kernel gen_op_lbz_kernel
1084 9a64fbe4 bellard
#endif
1085 9a64fbe4 bellard
1086 9a64fbe4 bellard
#define GEN_LD(width, opc)                                                    \
1087 79aceca5 bellard
GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)               \
1088 79aceca5 bellard
{                                                                             \
1089 79aceca5 bellard
    uint32_t simm = SIMM(ctx->opcode);                                        \
1090 79aceca5 bellard
    if (rA(ctx->opcode) == 0) {                                               \
1091 9a64fbe4 bellard
        gen_op_set_T0(simm);                                                  \
1092 79aceca5 bellard
    } else {                                                                  \
1093 79aceca5 bellard
        gen_op_load_gpr_T0(rA(ctx->opcode));                                  \
1094 9a64fbe4 bellard
        if (simm != 0)                                                        \
1095 9a64fbe4 bellard
            gen_op_addi(simm);                                                \
1096 79aceca5 bellard
    }                                                                         \
1097 9a64fbe4 bellard
    op_ldst(l##width);                                                        \
1098 79aceca5 bellard
    gen_op_store_T1_gpr(rD(ctx->opcode));                                     \
1099 79aceca5 bellard
}
1100 79aceca5 bellard
1101 9a64fbe4 bellard
#define GEN_LDU(width, opc)                                                   \
1102 79aceca5 bellard
GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)            \
1103 79aceca5 bellard
{                                                                             \
1104 9a64fbe4 bellard
    uint32_t simm = SIMM(ctx->opcode);                                        \
1105 79aceca5 bellard
    if (rA(ctx->opcode) == 0 ||                                               \
1106 9a64fbe4 bellard
        rA(ctx->opcode) == rD(ctx->opcode)) {                                 \
1107 9fddaa0c bellard
        RET_INVAL(ctx);                                                       \
1108 9fddaa0c bellard
        return;                                                               \
1109 9a64fbe4 bellard
    }                                                                         \
1110 79aceca5 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
1111 9a64fbe4 bellard
    if (simm != 0)                                                            \
1112 9a64fbe4 bellard
        gen_op_addi(simm);                                                    \
1113 9a64fbe4 bellard
    op_ldst(l##width);                                                        \
1114 79aceca5 bellard
    gen_op_store_T1_gpr(rD(ctx->opcode));                                     \
1115 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
1116 79aceca5 bellard
}
1117 79aceca5 bellard
1118 9a64fbe4 bellard
#define GEN_LDUX(width, opc)                                                  \
1119 79aceca5 bellard
GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER)           \
1120 79aceca5 bellard
{                                                                             \
1121 79aceca5 bellard
    if (rA(ctx->opcode) == 0 ||                                               \
1122 9a64fbe4 bellard
        rA(ctx->opcode) == rD(ctx->opcode)) {                                 \
1123 9fddaa0c bellard
        RET_INVAL(ctx);                                                       \
1124 9fddaa0c bellard
        return;                                                               \
1125 9a64fbe4 bellard
    }                                                                         \
1126 79aceca5 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
1127 79aceca5 bellard
    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
1128 9a64fbe4 bellard
    gen_op_add();                                                             \
1129 9a64fbe4 bellard
    op_ldst(l##width);                                                        \
1130 79aceca5 bellard
    gen_op_store_T1_gpr(rD(ctx->opcode));                                     \
1131 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
1132 79aceca5 bellard
}
1133 79aceca5 bellard
1134 9a64fbe4 bellard
#define GEN_LDX(width, opc2, opc3)                                            \
1135 79aceca5 bellard
GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER)           \
1136 79aceca5 bellard
{                                                                             \
1137 79aceca5 bellard
    if (rA(ctx->opcode) == 0) {                                               \
1138 79aceca5 bellard
        gen_op_load_gpr_T0(rB(ctx->opcode));                                  \
1139 79aceca5 bellard
    } else {                                                                  \
1140 79aceca5 bellard
        gen_op_load_gpr_T0(rA(ctx->opcode));                                  \
1141 79aceca5 bellard
        gen_op_load_gpr_T1(rB(ctx->opcode));                                  \
1142 9a64fbe4 bellard
        gen_op_add();                                                         \
1143 79aceca5 bellard
    }                                                                         \
1144 9a64fbe4 bellard
    op_ldst(l##width);                                                        \
1145 79aceca5 bellard
    gen_op_store_T1_gpr(rD(ctx->opcode));                                     \
1146 79aceca5 bellard
}
1147 79aceca5 bellard
1148 9a64fbe4 bellard
#define GEN_LDS(width, op)                                                    \
1149 9a64fbe4 bellard
OP_LD_TABLE(width);                                                           \
1150 9a64fbe4 bellard
GEN_LD(width, op | 0x20);                                                     \
1151 9a64fbe4 bellard
GEN_LDU(width, op | 0x21);                                                    \
1152 9a64fbe4 bellard
GEN_LDUX(width, op | 0x01);                                                   \
1153 9a64fbe4 bellard
GEN_LDX(width, 0x17, op | 0x00)
1154 79aceca5 bellard
1155 79aceca5 bellard
/* lbz lbzu lbzux lbzx */
1156 9a64fbe4 bellard
GEN_LDS(bz, 0x02);
1157 79aceca5 bellard
/* lha lhau lhaux lhax */
1158 9a64fbe4 bellard
GEN_LDS(ha, 0x0A);
1159 79aceca5 bellard
/* lhz lhzu lhzux lhzx */
1160 9a64fbe4 bellard
GEN_LDS(hz, 0x08);
1161 79aceca5 bellard
/* lwz lwzu lwzux lwzx */
1162 9a64fbe4 bellard
GEN_LDS(wz, 0x00);
1163 79aceca5 bellard
1164 79aceca5 bellard
/***                              Integer store                            ***/
1165 9a64fbe4 bellard
#define GEN_ST(width, opc)                                                    \
1166 79aceca5 bellard
GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)              \
1167 79aceca5 bellard
{                                                                             \
1168 79aceca5 bellard
    uint32_t simm = SIMM(ctx->opcode);                                        \
1169 79aceca5 bellard
    if (rA(ctx->opcode) == 0) {                                               \
1170 9a64fbe4 bellard
        gen_op_set_T0(simm);                                                  \
1171 79aceca5 bellard
    } else {                                                                  \
1172 79aceca5 bellard
        gen_op_load_gpr_T0(rA(ctx->opcode));                                  \
1173 9a64fbe4 bellard
        if (simm != 0)                                                        \
1174 9a64fbe4 bellard
            gen_op_addi(simm);                                                \
1175 79aceca5 bellard
    }                                                                         \
1176 9a64fbe4 bellard
    gen_op_load_gpr_T1(rS(ctx->opcode));                                      \
1177 9a64fbe4 bellard
    op_ldst(st##width);                                                       \
1178 79aceca5 bellard
}
1179 79aceca5 bellard
1180 9a64fbe4 bellard
#define GEN_STU(width, opc)                                                   \
1181 79aceca5 bellard
GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)           \
1182 79aceca5 bellard
{                                                                             \
1183 9a64fbe4 bellard
    uint32_t simm = SIMM(ctx->opcode);                                        \
1184 9a64fbe4 bellard
    if (rA(ctx->opcode) == 0) {                                               \
1185 9fddaa0c bellard
        RET_INVAL(ctx);                                                       \
1186 9fddaa0c bellard
        return;                                                               \
1187 9a64fbe4 bellard
    }                                                                         \
1188 79aceca5 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
1189 9a64fbe4 bellard
    if (simm != 0)                                                            \
1190 9a64fbe4 bellard
        gen_op_addi(simm);                                                    \
1191 79aceca5 bellard
    gen_op_load_gpr_T1(rS(ctx->opcode));                                      \
1192 9a64fbe4 bellard
    op_ldst(st##width);                                                       \
1193 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
1194 79aceca5 bellard
}
1195 79aceca5 bellard
1196 9a64fbe4 bellard
#define GEN_STUX(width, opc)                                                  \
1197 79aceca5 bellard
GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER)          \
1198 79aceca5 bellard
{                                                                             \
1199 9a64fbe4 bellard
    if (rA(ctx->opcode) == 0) {                                               \
1200 9fddaa0c bellard
        RET_INVAL(ctx);                                                       \
1201 9fddaa0c bellard
        return;                                                               \
1202 9a64fbe4 bellard
    }                                                                         \
1203 79aceca5 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
1204 79aceca5 bellard
    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
1205 9a64fbe4 bellard
    gen_op_add();                                                             \
1206 9a64fbe4 bellard
    gen_op_load_gpr_T1(rS(ctx->opcode));                                      \
1207 9a64fbe4 bellard
    op_ldst(st##width);                                                       \
1208 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
1209 79aceca5 bellard
}
1210 79aceca5 bellard
1211 9a64fbe4 bellard
#define GEN_STX(width, opc2, opc3)                                            \
1212 79aceca5 bellard
GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER)          \
1213 79aceca5 bellard
{                                                                             \
1214 79aceca5 bellard
    if (rA(ctx->opcode) == 0) {                                               \
1215 79aceca5 bellard
        gen_op_load_gpr_T0(rB(ctx->opcode));                                  \
1216 79aceca5 bellard
    } else {                                                                  \
1217 79aceca5 bellard
        gen_op_load_gpr_T0(rA(ctx->opcode));                                  \
1218 79aceca5 bellard
        gen_op_load_gpr_T1(rB(ctx->opcode));                                  \
1219 9a64fbe4 bellard
        gen_op_add();                                                         \
1220 79aceca5 bellard
    }                                                                         \
1221 9a64fbe4 bellard
    gen_op_load_gpr_T1(rS(ctx->opcode));                                      \
1222 9a64fbe4 bellard
    op_ldst(st##width);                                                       \
1223 79aceca5 bellard
}
1224 79aceca5 bellard
1225 9a64fbe4 bellard
#define GEN_STS(width, op)                                                    \
1226 9a64fbe4 bellard
OP_ST_TABLE(width);                                                           \
1227 9a64fbe4 bellard
GEN_ST(width, op | 0x20);                                                     \
1228 9a64fbe4 bellard
GEN_STU(width, op | 0x21);                                                    \
1229 9a64fbe4 bellard
GEN_STUX(width, op | 0x01);                                                   \
1230 9a64fbe4 bellard
GEN_STX(width, 0x17, op | 0x00)
1231 79aceca5 bellard
1232 79aceca5 bellard
/* stb stbu stbux stbx */
1233 9a64fbe4 bellard
GEN_STS(b, 0x06);
1234 79aceca5 bellard
/* sth sthu sthux sthx */
1235 9a64fbe4 bellard
GEN_STS(h, 0x0C);
1236 79aceca5 bellard
/* stw stwu stwux stwx */
1237 9a64fbe4 bellard
GEN_STS(w, 0x04);
1238 79aceca5 bellard
1239 79aceca5 bellard
/***                Integer load and store with byte reverse               ***/
1240 79aceca5 bellard
/* lhbrx */
1241 9a64fbe4 bellard
OP_LD_TABLE(hbr);
1242 9a64fbe4 bellard
GEN_LDX(hbr, 0x16, 0x18);
1243 79aceca5 bellard
/* lwbrx */
1244 9a64fbe4 bellard
OP_LD_TABLE(wbr);
1245 9a64fbe4 bellard
GEN_LDX(wbr, 0x16, 0x10);
1246 79aceca5 bellard
/* sthbrx */
1247 9a64fbe4 bellard
OP_ST_TABLE(hbr);
1248 9a64fbe4 bellard
GEN_STX(hbr, 0x16, 0x1C);
1249 79aceca5 bellard
/* stwbrx */
1250 9a64fbe4 bellard
OP_ST_TABLE(wbr);
1251 9a64fbe4 bellard
GEN_STX(wbr, 0x16, 0x14);
1252 79aceca5 bellard
1253 79aceca5 bellard
/***                    Integer load and store multiple                    ***/
1254 111bfab3 bellard
#define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
1255 9a64fbe4 bellard
#if defined(CONFIG_USER_ONLY)
1256 111bfab3 bellard
static GenOpFunc1 *gen_op_lmw[] = {
1257 111bfab3 bellard
    &gen_op_lmw_raw,
1258 111bfab3 bellard
    &gen_op_lmw_le_raw,
1259 111bfab3 bellard
};
1260 111bfab3 bellard
static GenOpFunc1 *gen_op_stmw[] = {
1261 111bfab3 bellard
    &gen_op_stmw_raw,
1262 111bfab3 bellard
    &gen_op_stmw_le_raw,
1263 111bfab3 bellard
};
1264 9a64fbe4 bellard
#else
1265 9a64fbe4 bellard
static GenOpFunc1 *gen_op_lmw[] = {
1266 9a64fbe4 bellard
    &gen_op_lmw_user,
1267 111bfab3 bellard
    &gen_op_lmw_le_user,
1268 9a64fbe4 bellard
    &gen_op_lmw_kernel,
1269 111bfab3 bellard
    &gen_op_lmw_le_kernel,
1270 9a64fbe4 bellard
};
1271 9a64fbe4 bellard
static GenOpFunc1 *gen_op_stmw[] = {
1272 9a64fbe4 bellard
    &gen_op_stmw_user,
1273 111bfab3 bellard
    &gen_op_stmw_le_user,
1274 9a64fbe4 bellard
    &gen_op_stmw_kernel,
1275 111bfab3 bellard
    &gen_op_stmw_le_kernel,
1276 9a64fbe4 bellard
};
1277 9a64fbe4 bellard
#endif
1278 9a64fbe4 bellard
1279 79aceca5 bellard
/* lmw */
1280 79aceca5 bellard
GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1281 79aceca5 bellard
{
1282 9a64fbe4 bellard
    int simm = SIMM(ctx->opcode);
1283 9a64fbe4 bellard
1284 79aceca5 bellard
    if (rA(ctx->opcode) == 0) {
1285 9a64fbe4 bellard
        gen_op_set_T0(simm);
1286 79aceca5 bellard
    } else {
1287 79aceca5 bellard
        gen_op_load_gpr_T0(rA(ctx->opcode));
1288 9a64fbe4 bellard
        if (simm != 0)
1289 9a64fbe4 bellard
            gen_op_addi(simm);
1290 79aceca5 bellard
    }
1291 9a64fbe4 bellard
    op_ldstm(lmw, rD(ctx->opcode));
1292 79aceca5 bellard
}
1293 79aceca5 bellard
1294 79aceca5 bellard
/* stmw */
1295 79aceca5 bellard
GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1296 79aceca5 bellard
{
1297 9a64fbe4 bellard
    int simm = SIMM(ctx->opcode);
1298 9a64fbe4 bellard
1299 79aceca5 bellard
    if (rA(ctx->opcode) == 0) {
1300 9a64fbe4 bellard
        gen_op_set_T0(simm);
1301 79aceca5 bellard
    } else {
1302 79aceca5 bellard
        gen_op_load_gpr_T0(rA(ctx->opcode));
1303 9a64fbe4 bellard
        if (simm != 0)
1304 9a64fbe4 bellard
            gen_op_addi(simm);
1305 79aceca5 bellard
    }
1306 9a64fbe4 bellard
    op_ldstm(stmw, rS(ctx->opcode));
1307 79aceca5 bellard
}
1308 79aceca5 bellard
1309 79aceca5 bellard
/***                    Integer load and store strings                     ***/
1310 9a64fbe4 bellard
#define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
1311 9a64fbe4 bellard
#define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
1312 111bfab3 bellard
#if defined(CONFIG_USER_ONLY)
1313 111bfab3 bellard
static GenOpFunc1 *gen_op_lswi[] = {
1314 111bfab3 bellard
    &gen_op_lswi_raw,
1315 111bfab3 bellard
    &gen_op_lswi_le_raw,
1316 111bfab3 bellard
};
1317 111bfab3 bellard
static GenOpFunc3 *gen_op_lswx[] = {
1318 111bfab3 bellard
    &gen_op_lswx_raw,
1319 111bfab3 bellard
    &gen_op_lswx_le_raw,
1320 111bfab3 bellard
};
1321 111bfab3 bellard
static GenOpFunc1 *gen_op_stsw[] = {
1322 111bfab3 bellard
    &gen_op_stsw_raw,
1323 111bfab3 bellard
    &gen_op_stsw_le_raw,
1324 111bfab3 bellard
};
1325 111bfab3 bellard
#else
1326 9a64fbe4 bellard
static GenOpFunc1 *gen_op_lswi[] = {
1327 9a64fbe4 bellard
    &gen_op_lswi_user,
1328 111bfab3 bellard
    &gen_op_lswi_le_user,
1329 9a64fbe4 bellard
    &gen_op_lswi_kernel,
1330 111bfab3 bellard
    &gen_op_lswi_le_kernel,
1331 9a64fbe4 bellard
};
1332 9a64fbe4 bellard
static GenOpFunc3 *gen_op_lswx[] = {
1333 9a64fbe4 bellard
    &gen_op_lswx_user,
1334 111bfab3 bellard
    &gen_op_lswx_le_user,
1335 9a64fbe4 bellard
    &gen_op_lswx_kernel,
1336 111bfab3 bellard
    &gen_op_lswx_le_kernel,
1337 9a64fbe4 bellard
};
1338 9a64fbe4 bellard
static GenOpFunc1 *gen_op_stsw[] = {
1339 9a64fbe4 bellard
    &gen_op_stsw_user,
1340 111bfab3 bellard
    &gen_op_stsw_le_user,
1341 9a64fbe4 bellard
    &gen_op_stsw_kernel,
1342 111bfab3 bellard
    &gen_op_stsw_le_kernel,
1343 9a64fbe4 bellard
};
1344 9a64fbe4 bellard
#endif
1345 9a64fbe4 bellard
1346 79aceca5 bellard
/* lswi */
1347 9a64fbe4 bellard
/* PPC32 specification says we must generate an exception if
1348 9a64fbe4 bellard
 * rA is in the range of registers to be loaded.
1349 9a64fbe4 bellard
 * In an other hand, IBM says this is valid, but rA won't be loaded.
1350 9a64fbe4 bellard
 * For now, I'll follow the spec...
1351 9a64fbe4 bellard
 */
1352 79aceca5 bellard
GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_INTEGER)
1353 79aceca5 bellard
{
1354 79aceca5 bellard
    int nb = NB(ctx->opcode);
1355 79aceca5 bellard
    int start = rD(ctx->opcode);
1356 9a64fbe4 bellard
    int ra = rA(ctx->opcode);
1357 79aceca5 bellard
    int nr;
1358 79aceca5 bellard
1359 79aceca5 bellard
    if (nb == 0)
1360 79aceca5 bellard
        nb = 32;
1361 79aceca5 bellard
    nr = nb / 4;
1362 297d8e62 bellard
    if (((start + nr) > 32  && start <= ra && (start + nr - 32) > ra) ||
1363 297d8e62 bellard
        ((start + nr) <= 32 && start <= ra && (start + nr) > ra)) {
1364 9fddaa0c bellard
        RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_LSWX);
1365 9fddaa0c bellard
        return;
1366 297d8e62 bellard
    }
1367 9a64fbe4 bellard
    if (ra == 0) {
1368 79aceca5 bellard
        gen_op_set_T0(0);
1369 79aceca5 bellard
    } else {
1370 9a64fbe4 bellard
        gen_op_load_gpr_T0(ra);
1371 79aceca5 bellard
    }
1372 9a64fbe4 bellard
    gen_op_set_T1(nb);
1373 9a64fbe4 bellard
    op_ldsts(lswi, start);
1374 79aceca5 bellard
}
1375 79aceca5 bellard
1376 79aceca5 bellard
/* lswx */
1377 79aceca5 bellard
GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_INTEGER)
1378 79aceca5 bellard
{
1379 9a64fbe4 bellard
    int ra = rA(ctx->opcode);
1380 9a64fbe4 bellard
    int rb = rB(ctx->opcode);
1381 9a64fbe4 bellard
1382 9a64fbe4 bellard
    if (ra == 0) {
1383 9a64fbe4 bellard
        gen_op_load_gpr_T0(rb);
1384 9a64fbe4 bellard
        ra = rb;
1385 79aceca5 bellard
    } else {
1386 9a64fbe4 bellard
        gen_op_load_gpr_T0(ra);
1387 9a64fbe4 bellard
        gen_op_load_gpr_T1(rb);
1388 9a64fbe4 bellard
        gen_op_add();
1389 79aceca5 bellard
    }
1390 9a64fbe4 bellard
    gen_op_load_xer_bc();
1391 9a64fbe4 bellard
    op_ldstsx(lswx, rD(ctx->opcode), ra, rb);
1392 79aceca5 bellard
}
1393 79aceca5 bellard
1394 79aceca5 bellard
/* stswi */
1395 79aceca5 bellard
GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_INTEGER)
1396 79aceca5 bellard
{
1397 4b3686fa bellard
    int nb = NB(ctx->opcode);
1398 4b3686fa bellard
1399 79aceca5 bellard
    if (rA(ctx->opcode) == 0) {
1400 79aceca5 bellard
        gen_op_set_T0(0);
1401 79aceca5 bellard
    } else {
1402 79aceca5 bellard
        gen_op_load_gpr_T0(rA(ctx->opcode));
1403 79aceca5 bellard
    }
1404 4b3686fa bellard
    if (nb == 0)
1405 4b3686fa bellard
        nb = 32;
1406 4b3686fa bellard
    gen_op_set_T1(nb);
1407 9a64fbe4 bellard
    op_ldsts(stsw, rS(ctx->opcode));
1408 79aceca5 bellard
}
1409 79aceca5 bellard
1410 79aceca5 bellard
/* stswx */
1411 79aceca5 bellard
GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_INTEGER)
1412 79aceca5 bellard
{
1413 9a64fbe4 bellard
    int ra = rA(ctx->opcode);
1414 9a64fbe4 bellard
1415 9a64fbe4 bellard
    if (ra == 0) {
1416 9a64fbe4 bellard
        gen_op_load_gpr_T0(rB(ctx->opcode));
1417 9a64fbe4 bellard
        ra = rB(ctx->opcode);
1418 79aceca5 bellard
    } else {
1419 9a64fbe4 bellard
        gen_op_load_gpr_T0(ra);
1420 9a64fbe4 bellard
        gen_op_load_gpr_T1(rB(ctx->opcode));
1421 9a64fbe4 bellard
        gen_op_add();
1422 79aceca5 bellard
    }
1423 9a64fbe4 bellard
    gen_op_load_xer_bc();
1424 9a64fbe4 bellard
    op_ldsts(stsw, rS(ctx->opcode));
1425 79aceca5 bellard
}
1426 79aceca5 bellard
1427 79aceca5 bellard
/***                        Memory synchronisation                         ***/
1428 79aceca5 bellard
/* eieio */
1429 79aceca5 bellard
GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FF0801, PPC_MEM)
1430 79aceca5 bellard
{
1431 79aceca5 bellard
}
1432 79aceca5 bellard
1433 79aceca5 bellard
/* isync */
1434 79aceca5 bellard
GEN_HANDLER(isync, 0x13, 0x16, 0xFF, 0x03FF0801, PPC_MEM)
1435 79aceca5 bellard
{
1436 79aceca5 bellard
}
1437 79aceca5 bellard
1438 111bfab3 bellard
#define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
1439 111bfab3 bellard
#define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
1440 9a64fbe4 bellard
#if defined(CONFIG_USER_ONLY)
1441 111bfab3 bellard
static GenOpFunc *gen_op_lwarx[] = {
1442 111bfab3 bellard
    &gen_op_lwarx_raw,
1443 111bfab3 bellard
    &gen_op_lwarx_le_raw,
1444 111bfab3 bellard
};
1445 111bfab3 bellard
static GenOpFunc *gen_op_stwcx[] = {
1446 111bfab3 bellard
    &gen_op_stwcx_raw,
1447 111bfab3 bellard
    &gen_op_stwcx_le_raw,
1448 111bfab3 bellard
};
1449 9a64fbe4 bellard
#else
1450 985a19d6 bellard
static GenOpFunc *gen_op_lwarx[] = {
1451 985a19d6 bellard
    &gen_op_lwarx_user,
1452 111bfab3 bellard
    &gen_op_lwarx_le_user,
1453 985a19d6 bellard
    &gen_op_lwarx_kernel,
1454 111bfab3 bellard
    &gen_op_lwarx_le_kernel,
1455 985a19d6 bellard
};
1456 9a64fbe4 bellard
static GenOpFunc *gen_op_stwcx[] = {
1457 9a64fbe4 bellard
    &gen_op_stwcx_user,
1458 111bfab3 bellard
    &gen_op_stwcx_le_user,
1459 9a64fbe4 bellard
    &gen_op_stwcx_kernel,
1460 111bfab3 bellard
    &gen_op_stwcx_le_kernel,
1461 9a64fbe4 bellard
};
1462 9a64fbe4 bellard
#endif
1463 9a64fbe4 bellard
1464 111bfab3 bellard
/* lwarx */
1465 9a64fbe4 bellard
GEN_HANDLER(lwarx, 0x1F, 0x14, 0xFF, 0x00000001, PPC_RES)
1466 79aceca5 bellard
{
1467 79aceca5 bellard
    if (rA(ctx->opcode) == 0) {
1468 79aceca5 bellard
        gen_op_load_gpr_T0(rB(ctx->opcode));
1469 79aceca5 bellard
    } else {
1470 79aceca5 bellard
        gen_op_load_gpr_T0(rA(ctx->opcode));
1471 79aceca5 bellard
        gen_op_load_gpr_T1(rB(ctx->opcode));
1472 9a64fbe4 bellard
        gen_op_add();
1473 79aceca5 bellard
    }
1474 985a19d6 bellard
    op_lwarx();
1475 79aceca5 bellard
    gen_op_store_T1_gpr(rD(ctx->opcode));
1476 79aceca5 bellard
}
1477 79aceca5 bellard
1478 79aceca5 bellard
/* stwcx. */
1479 9a64fbe4 bellard
GEN_HANDLER(stwcx_, 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
1480 79aceca5 bellard
{
1481 79aceca5 bellard
        if (rA(ctx->opcode) == 0) {
1482 79aceca5 bellard
            gen_op_load_gpr_T0(rB(ctx->opcode));
1483 79aceca5 bellard
        } else {
1484 79aceca5 bellard
            gen_op_load_gpr_T0(rA(ctx->opcode));
1485 79aceca5 bellard
            gen_op_load_gpr_T1(rB(ctx->opcode));
1486 9a64fbe4 bellard
        gen_op_add();
1487 79aceca5 bellard
        }
1488 9a64fbe4 bellard
    gen_op_load_gpr_T1(rS(ctx->opcode));
1489 9a64fbe4 bellard
    op_stwcx();
1490 79aceca5 bellard
}
1491 79aceca5 bellard
1492 79aceca5 bellard
/* sync */
1493 79aceca5 bellard
GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x03FF0801, PPC_MEM)
1494 79aceca5 bellard
{
1495 79aceca5 bellard
}
1496 79aceca5 bellard
1497 79aceca5 bellard
/***                         Floating-point load                           ***/
1498 9a64fbe4 bellard
#define GEN_LDF(width, opc)                                                   \
1499 c7d344af bellard
GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT)                 \
1500 79aceca5 bellard
{                                                                             \
1501 79aceca5 bellard
    uint32_t simm = SIMM(ctx->opcode);                                        \
1502 4ecc3190 bellard
    if (!ctx->fpu_enabled) {                                                  \
1503 4ecc3190 bellard
        RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \
1504 4ecc3190 bellard
        return;                                                               \
1505 4ecc3190 bellard
    }                                                                         \
1506 79aceca5 bellard
    if (rA(ctx->opcode) == 0) {                                               \
1507 9a64fbe4 bellard
        gen_op_set_T0(simm);                                                  \
1508 79aceca5 bellard
    } else {                                                                  \
1509 79aceca5 bellard
        gen_op_load_gpr_T0(rA(ctx->opcode));                                  \
1510 9a64fbe4 bellard
        if (simm != 0)                                                        \
1511 9a64fbe4 bellard
            gen_op_addi(simm);                                                \
1512 79aceca5 bellard
    }                                                                         \
1513 9a64fbe4 bellard
    op_ldst(l##width);                                                        \
1514 9a64fbe4 bellard
    gen_op_store_FT1_fpr(rD(ctx->opcode));                                    \
1515 79aceca5 bellard
}
1516 79aceca5 bellard
1517 9a64fbe4 bellard
#define GEN_LDUF(width, opc)                                                  \
1518 c7d344af bellard
GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT)              \
1519 79aceca5 bellard
{                                                                             \
1520 9a64fbe4 bellard
    uint32_t simm = SIMM(ctx->opcode);                                        \
1521 4ecc3190 bellard
    if (!ctx->fpu_enabled) {                                                  \
1522 4ecc3190 bellard
        RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \
1523 4ecc3190 bellard
        return;                                                               \
1524 4ecc3190 bellard
    }                                                                         \
1525 79aceca5 bellard
    if (rA(ctx->opcode) == 0 ||                                               \
1526 9a64fbe4 bellard
        rA(ctx->opcode) == rD(ctx->opcode)) {                                 \
1527 9fddaa0c bellard
        RET_INVAL(ctx);                                                       \
1528 9fddaa0c bellard
        return;                                                               \
1529 9a64fbe4 bellard
    }                                                                         \
1530 79aceca5 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
1531 9a64fbe4 bellard
    if (simm != 0)                                                            \
1532 9a64fbe4 bellard
        gen_op_addi(simm);                                                    \
1533 9a64fbe4 bellard
    op_ldst(l##width);                                                        \
1534 9a64fbe4 bellard
    gen_op_store_FT1_fpr(rD(ctx->opcode));                                    \
1535 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
1536 79aceca5 bellard
}
1537 79aceca5 bellard
1538 9a64fbe4 bellard
#define GEN_LDUXF(width, opc)                                                 \
1539 c7d344af bellard
GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_FLOAT)             \
1540 79aceca5 bellard
{                                                                             \
1541 4ecc3190 bellard
    if (!ctx->fpu_enabled) {                                                  \
1542 4ecc3190 bellard
        RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \
1543 4ecc3190 bellard
        return;                                                               \
1544 4ecc3190 bellard
    }                                                                         \
1545 79aceca5 bellard
    if (rA(ctx->opcode) == 0 ||                                               \
1546 9a64fbe4 bellard
        rA(ctx->opcode) == rD(ctx->opcode)) {                                 \
1547 9fddaa0c bellard
        RET_INVAL(ctx);                                                       \
1548 9fddaa0c bellard
        return;                                                               \
1549 9a64fbe4 bellard
    }                                                                         \
1550 79aceca5 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
1551 79aceca5 bellard
    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
1552 9a64fbe4 bellard
    gen_op_add();                                                             \
1553 9a64fbe4 bellard
    op_ldst(l##width);                                                        \
1554 9a64fbe4 bellard
    gen_op_store_FT1_fpr(rD(ctx->opcode));                                    \
1555 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
1556 79aceca5 bellard
}
1557 79aceca5 bellard
1558 9a64fbe4 bellard
#define GEN_LDXF(width, opc2, opc3)                                           \
1559 c7d344af bellard
GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_FLOAT)             \
1560 79aceca5 bellard
{                                                                             \
1561 4ecc3190 bellard
    if (!ctx->fpu_enabled) {                                                  \
1562 4ecc3190 bellard
        RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \
1563 4ecc3190 bellard
        return;                                                               \
1564 4ecc3190 bellard
    }                                                                         \
1565 79aceca5 bellard
    if (rA(ctx->opcode) == 0) {                                               \
1566 79aceca5 bellard
        gen_op_load_gpr_T0(rB(ctx->opcode));                                  \
1567 79aceca5 bellard
    } else {                                                                  \
1568 79aceca5 bellard
        gen_op_load_gpr_T0(rA(ctx->opcode));                                  \
1569 79aceca5 bellard
        gen_op_load_gpr_T1(rB(ctx->opcode));                                  \
1570 9a64fbe4 bellard
        gen_op_add();                                                         \
1571 79aceca5 bellard
    }                                                                         \
1572 9a64fbe4 bellard
    op_ldst(l##width);                                                        \
1573 9a64fbe4 bellard
    gen_op_store_FT1_fpr(rD(ctx->opcode));                                    \
1574 79aceca5 bellard
}
1575 79aceca5 bellard
1576 9a64fbe4 bellard
#define GEN_LDFS(width, op)                                                   \
1577 9a64fbe4 bellard
OP_LD_TABLE(width);                                                           \
1578 9a64fbe4 bellard
GEN_LDF(width, op | 0x20);                                                    \
1579 9a64fbe4 bellard
GEN_LDUF(width, op | 0x21);                                                   \
1580 9a64fbe4 bellard
GEN_LDUXF(width, op | 0x01);                                                  \
1581 9a64fbe4 bellard
GEN_LDXF(width, 0x17, op | 0x00)
1582 79aceca5 bellard
1583 79aceca5 bellard
/* lfd lfdu lfdux lfdx */
1584 9a64fbe4 bellard
GEN_LDFS(fd, 0x12);
1585 79aceca5 bellard
/* lfs lfsu lfsux lfsx */
1586 9a64fbe4 bellard
GEN_LDFS(fs, 0x10);
1587 79aceca5 bellard
1588 79aceca5 bellard
/***                         Floating-point store                          ***/
1589 79aceca5 bellard
#define GEN_STF(width, opc)                                                   \
1590 c7d344af bellard
GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT)                \
1591 79aceca5 bellard
{                                                                             \
1592 79aceca5 bellard
    uint32_t simm = SIMM(ctx->opcode);                                        \
1593 4ecc3190 bellard
    if (!ctx->fpu_enabled) {                                                  \
1594 4ecc3190 bellard
        RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \
1595 4ecc3190 bellard
        return;                                                               \
1596 4ecc3190 bellard
    }                                                                         \
1597 79aceca5 bellard
    if (rA(ctx->opcode) == 0) {                                               \
1598 9a64fbe4 bellard
        gen_op_set_T0(simm);                                                  \
1599 79aceca5 bellard
    } else {                                                                  \
1600 79aceca5 bellard
        gen_op_load_gpr_T0(rA(ctx->opcode));                                  \
1601 9a64fbe4 bellard
        if (simm != 0)                                                        \
1602 9a64fbe4 bellard
            gen_op_addi(simm);                                                \
1603 79aceca5 bellard
    }                                                                         \
1604 9a64fbe4 bellard
    gen_op_load_fpr_FT1(rS(ctx->opcode));                                     \
1605 9a64fbe4 bellard
    op_ldst(st##width);                                                       \
1606 79aceca5 bellard
}
1607 79aceca5 bellard
1608 9a64fbe4 bellard
#define GEN_STUF(width, opc)                                                  \
1609 c7d344af bellard
GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT)             \
1610 79aceca5 bellard
{                                                                             \
1611 9a64fbe4 bellard
    uint32_t simm = SIMM(ctx->opcode);                                        \
1612 4ecc3190 bellard
    if (!ctx->fpu_enabled) {                                                  \
1613 4ecc3190 bellard
        RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \
1614 4ecc3190 bellard
        return;                                                               \
1615 4ecc3190 bellard
    }                                                                         \
1616 9a64fbe4 bellard
    if (rA(ctx->opcode) == 0) {                                               \
1617 9fddaa0c bellard
        RET_INVAL(ctx);                                                       \
1618 9fddaa0c bellard
        return;                                                               \
1619 9a64fbe4 bellard
    }                                                                         \
1620 79aceca5 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
1621 9a64fbe4 bellard
    if (simm != 0)                                                            \
1622 9a64fbe4 bellard
        gen_op_addi(simm);                                                    \
1623 9a64fbe4 bellard
    gen_op_load_fpr_FT1(rS(ctx->opcode));                                     \
1624 9a64fbe4 bellard
    op_ldst(st##width);                                                       \
1625 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
1626 79aceca5 bellard
}
1627 79aceca5 bellard
1628 9a64fbe4 bellard
#define GEN_STUXF(width, opc)                                                 \
1629 c7d344af bellard
GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_FLOAT)            \
1630 79aceca5 bellard
{                                                                             \
1631 4ecc3190 bellard
    if (!ctx->fpu_enabled) {                                                  \
1632 4ecc3190 bellard
        RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \
1633 4ecc3190 bellard
        return;                                                               \
1634 4ecc3190 bellard
    }                                                                         \
1635 9a64fbe4 bellard
    if (rA(ctx->opcode) == 0) {                                               \
1636 9fddaa0c bellard
        RET_INVAL(ctx);                                                       \
1637 9fddaa0c bellard
        return;                                                               \
1638 9a64fbe4 bellard
    }                                                                         \
1639 79aceca5 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
1640 79aceca5 bellard
    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
1641 9a64fbe4 bellard
    gen_op_add();                                                             \
1642 9a64fbe4 bellard
    gen_op_load_fpr_FT1(rS(ctx->opcode));                                     \
1643 9a64fbe4 bellard
    op_ldst(st##width);                                                       \
1644 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
1645 79aceca5 bellard
}
1646 79aceca5 bellard
1647 9a64fbe4 bellard
#define GEN_STXF(width, opc2, opc3)                                           \
1648 c7d344af bellard
GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_FLOAT)            \
1649 79aceca5 bellard
{                                                                             \
1650 4ecc3190 bellard
    if (!ctx->fpu_enabled) {                                                  \
1651 4ecc3190 bellard
        RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \
1652 4ecc3190 bellard
        return;                                                               \
1653 4ecc3190 bellard
    }                                                                         \
1654 79aceca5 bellard
    if (rA(ctx->opcode) == 0) {                                               \
1655 79aceca5 bellard
        gen_op_load_gpr_T0(rB(ctx->opcode));                                  \
1656 79aceca5 bellard
    } else {                                                                  \
1657 79aceca5 bellard
        gen_op_load_gpr_T0(rA(ctx->opcode));                                  \
1658 79aceca5 bellard
        gen_op_load_gpr_T1(rB(ctx->opcode));                                  \
1659 9a64fbe4 bellard
        gen_op_add();                                                         \
1660 79aceca5 bellard
    }                                                                         \
1661 9a64fbe4 bellard
    gen_op_load_fpr_FT1(rS(ctx->opcode));                                     \
1662 9a64fbe4 bellard
    op_ldst(st##width);                                                       \
1663 79aceca5 bellard
}
1664 79aceca5 bellard
1665 9a64fbe4 bellard
#define GEN_STFS(width, op)                                                   \
1666 9a64fbe4 bellard
OP_ST_TABLE(width);                                                           \
1667 9a64fbe4 bellard
GEN_STF(width, op | 0x20);                                                    \
1668 9a64fbe4 bellard
GEN_STUF(width, op | 0x21);                                                   \
1669 9a64fbe4 bellard
GEN_STUXF(width, op | 0x01);                                                  \
1670 9a64fbe4 bellard
GEN_STXF(width, 0x17, op | 0x00)
1671 79aceca5 bellard
1672 79aceca5 bellard
/* stfd stfdu stfdux stfdx */
1673 9a64fbe4 bellard
GEN_STFS(fd, 0x16);
1674 79aceca5 bellard
/* stfs stfsu stfsux stfsx */
1675 9a64fbe4 bellard
GEN_STFS(fs, 0x14);
1676 79aceca5 bellard
1677 79aceca5 bellard
/* Optional: */
1678 79aceca5 bellard
/* stfiwx */
1679 79aceca5 bellard
GEN_HANDLER(stfiwx, 0x1F, 0x17, 0x1E, 0x00000001, PPC_FLOAT)
1680 79aceca5 bellard
{
1681 3cc62370 bellard
    if (!ctx->fpu_enabled) {
1682 3cc62370 bellard
        RET_EXCP(ctx, EXCP_NO_FP, 0);
1683 3cc62370 bellard
        return;
1684 3cc62370 bellard
    }
1685 9fddaa0c bellard
    RET_INVAL(ctx);
1686 79aceca5 bellard
}
1687 79aceca5 bellard
1688 79aceca5 bellard
/***                                Branch                                 ***/
1689 79aceca5 bellard
1690 79aceca5 bellard
/* b ba bl bla */
1691 79aceca5 bellard
GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1692 79aceca5 bellard
{
1693 38a64f9d bellard
    uint32_t li, target;
1694 38a64f9d bellard
1695 38a64f9d bellard
    /* sign extend LI */
1696 38a64f9d bellard
    li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
1697 79aceca5 bellard
1698 79aceca5 bellard
    if (AA(ctx->opcode) == 0)
1699 046d6672 bellard
        target = ctx->nip + li - 4;
1700 79aceca5 bellard
    else
1701 9a64fbe4 bellard
        target = li;
1702 9a64fbe4 bellard
    if (LK(ctx->opcode)) {
1703 046d6672 bellard
        gen_op_setlr(ctx->nip);
1704 9a64fbe4 bellard
    }
1705 e98a6e40 bellard
    gen_op_b((long)ctx->tb, target);
1706 9a64fbe4 bellard
    ctx->exception = EXCP_BRANCH;
1707 79aceca5 bellard
}
1708 79aceca5 bellard
1709 e98a6e40 bellard
#define BCOND_IM  0
1710 e98a6e40 bellard
#define BCOND_LR  1
1711 e98a6e40 bellard
#define BCOND_CTR 2
1712 e98a6e40 bellard
1713 e98a6e40 bellard
static inline void gen_bcond(DisasContext *ctx, int type) 
1714 e98a6e40 bellard
{                                                                             
1715 e98a6e40 bellard
    uint32_t target = 0;
1716 e98a6e40 bellard
    uint32_t bo = BO(ctx->opcode);                                            
1717 e98a6e40 bellard
    uint32_t bi = BI(ctx->opcode);                                            
1718 e98a6e40 bellard
    uint32_t mask;                                                            
1719 e98a6e40 bellard
    uint32_t li;
1720 e98a6e40 bellard
1721 e98a6e40 bellard
    if ((bo & 0x4) == 0)
1722 e98a6e40 bellard
        gen_op_dec_ctr();                                                     
1723 e98a6e40 bellard
    switch(type) {
1724 e98a6e40 bellard
    case BCOND_IM:
1725 18fba28c bellard
        li = (int32_t)((int16_t)(BD(ctx->opcode)));
1726 e98a6e40 bellard
        if (AA(ctx->opcode) == 0) {
1727 046d6672 bellard
            target = ctx->nip + li - 4;
1728 e98a6e40 bellard
        } else {
1729 e98a6e40 bellard
            target = li;
1730 e98a6e40 bellard
        }
1731 e98a6e40 bellard
        break;
1732 e98a6e40 bellard
    case BCOND_CTR:
1733 e98a6e40 bellard
        gen_op_movl_T1_ctr();
1734 e98a6e40 bellard
        break;
1735 e98a6e40 bellard
    default:
1736 e98a6e40 bellard
    case BCOND_LR:
1737 e98a6e40 bellard
        gen_op_movl_T1_lr();
1738 e98a6e40 bellard
        break;
1739 e98a6e40 bellard
    }
1740 e98a6e40 bellard
    if (LK(ctx->opcode)) {                                        
1741 046d6672 bellard
        gen_op_setlr(ctx->nip);
1742 e98a6e40 bellard
    }
1743 e98a6e40 bellard
    if (bo & 0x10) {
1744 e98a6e40 bellard
        /* No CR condition */                                                 
1745 e98a6e40 bellard
        switch (bo & 0x6) {                                                   
1746 e98a6e40 bellard
        case 0:                                                               
1747 e98a6e40 bellard
            gen_op_test_ctr();
1748 e98a6e40 bellard
            break;
1749 e98a6e40 bellard
        case 2:                                                               
1750 e98a6e40 bellard
            gen_op_test_ctrz();
1751 e98a6e40 bellard
            break;                                                            
1752 e98a6e40 bellard
        default:
1753 e98a6e40 bellard
        case 4:                                                               
1754 e98a6e40 bellard
        case 6:                                                               
1755 e98a6e40 bellard
            if (type == BCOND_IM) {
1756 e98a6e40 bellard
                gen_op_b((long)ctx->tb, target);
1757 e98a6e40 bellard
            } else {
1758 e98a6e40 bellard
                gen_op_b_T1();
1759 e98a6e40 bellard
            }
1760 e98a6e40 bellard
            goto no_test;
1761 e98a6e40 bellard
        }
1762 e98a6e40 bellard
    } else {                                                                  
1763 e98a6e40 bellard
        mask = 1 << (3 - (bi & 0x03));                                        
1764 e98a6e40 bellard
        gen_op_load_crf_T0(bi >> 2);                                          
1765 e98a6e40 bellard
        if (bo & 0x8) {                                                       
1766 e98a6e40 bellard
            switch (bo & 0x6) {                                               
1767 e98a6e40 bellard
            case 0:                                                           
1768 e98a6e40 bellard
                gen_op_test_ctr_true(mask);
1769 e98a6e40 bellard
                break;                                                        
1770 e98a6e40 bellard
            case 2:                                                           
1771 e98a6e40 bellard
                gen_op_test_ctrz_true(mask);
1772 e98a6e40 bellard
                break;                                                        
1773 e98a6e40 bellard
            default:                                                          
1774 e98a6e40 bellard
            case 4:                                                           
1775 e98a6e40 bellard
            case 6:                                                           
1776 e98a6e40 bellard
                gen_op_test_true(mask);
1777 e98a6e40 bellard
                break;                                                        
1778 e98a6e40 bellard
            }                                                                 
1779 e98a6e40 bellard
        } else {                                                              
1780 e98a6e40 bellard
            switch (bo & 0x6) {                                               
1781 e98a6e40 bellard
            case 0:                                                           
1782 e98a6e40 bellard
                gen_op_test_ctr_false(mask);
1783 e98a6e40 bellard
                break;                                                        
1784 e98a6e40 bellard
            case 2:                                                           
1785 e98a6e40 bellard
                gen_op_test_ctrz_false(mask);
1786 e98a6e40 bellard
                break;                                                        
1787 e98a6e40 bellard
            default:
1788 e98a6e40 bellard
            case 4:                                                           
1789 e98a6e40 bellard
            case 6:                                                           
1790 e98a6e40 bellard
                gen_op_test_false(mask);
1791 e98a6e40 bellard
                break;                                                        
1792 e98a6e40 bellard
            }                                                                 
1793 e98a6e40 bellard
        }                                                                     
1794 e98a6e40 bellard
    }                                                                         
1795 e98a6e40 bellard
    if (type == BCOND_IM) {
1796 046d6672 bellard
        gen_op_btest((long)ctx->tb, target, ctx->nip);
1797 e98a6e40 bellard
    } else {
1798 046d6672 bellard
        gen_op_btest_T1(ctx->nip);
1799 e98a6e40 bellard
    }
1800 e98a6e40 bellard
 no_test:
1801 e98a6e40 bellard
    ctx->exception = EXCP_BRANCH;                                             
1802 e98a6e40 bellard
}
1803 e98a6e40 bellard
1804 e98a6e40 bellard
GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1805 e98a6e40 bellard
{                                                                             
1806 e98a6e40 bellard
    gen_bcond(ctx, BCOND_IM);
1807 e98a6e40 bellard
}
1808 e98a6e40 bellard
1809 e98a6e40 bellard
GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
1810 e98a6e40 bellard
{                                                                             
1811 e98a6e40 bellard
    gen_bcond(ctx, BCOND_CTR);
1812 e98a6e40 bellard
}
1813 e98a6e40 bellard
1814 e98a6e40 bellard
GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
1815 e98a6e40 bellard
{                                                                             
1816 e98a6e40 bellard
    gen_bcond(ctx, BCOND_LR);
1817 e98a6e40 bellard
}
1818 79aceca5 bellard
1819 79aceca5 bellard
/***                      Condition register logical                       ***/
1820 79aceca5 bellard
#define GEN_CRLOGIC(op, opc)                                                  \
1821 79aceca5 bellard
GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)                 \
1822 79aceca5 bellard
{                                                                             \
1823 79aceca5 bellard
    gen_op_load_crf_T0(crbA(ctx->opcode) >> 2);                               \
1824 79aceca5 bellard
    gen_op_getbit_T0(3 - (crbA(ctx->opcode) & 0x03));                         \
1825 79aceca5 bellard
    gen_op_load_crf_T1(crbB(ctx->opcode) >> 2);                               \
1826 79aceca5 bellard
    gen_op_getbit_T1(3 - (crbB(ctx->opcode) & 0x03));                         \
1827 79aceca5 bellard
    gen_op_##op();                                                            \
1828 79aceca5 bellard
    gen_op_load_crf_T1(crbD(ctx->opcode) >> 2);                               \
1829 79aceca5 bellard
    gen_op_setcrfbit(~(1 << (3 - (crbD(ctx->opcode) & 0x03))),                \
1830 79aceca5 bellard
                     3 - (crbD(ctx->opcode) & 0x03));                         \
1831 79aceca5 bellard
    gen_op_store_T1_crf(crbD(ctx->opcode) >> 2);                              \
1832 79aceca5 bellard
}
1833 79aceca5 bellard
1834 79aceca5 bellard
/* crand */
1835 79aceca5 bellard
GEN_CRLOGIC(and, 0x08)
1836 79aceca5 bellard
/* crandc */
1837 79aceca5 bellard
GEN_CRLOGIC(andc, 0x04)
1838 79aceca5 bellard
/* creqv */
1839 79aceca5 bellard
GEN_CRLOGIC(eqv, 0x09)
1840 79aceca5 bellard
/* crnand */
1841 79aceca5 bellard
GEN_CRLOGIC(nand, 0x07)
1842 79aceca5 bellard
/* crnor */
1843 79aceca5 bellard
GEN_CRLOGIC(nor, 0x01)
1844 79aceca5 bellard
/* cror */
1845 79aceca5 bellard
GEN_CRLOGIC(or, 0x0E)
1846 79aceca5 bellard
/* crorc */
1847 79aceca5 bellard
GEN_CRLOGIC(orc, 0x0D)
1848 79aceca5 bellard
/* crxor */
1849 79aceca5 bellard
GEN_CRLOGIC(xor, 0x06)
1850 79aceca5 bellard
/* mcrf */
1851 79aceca5 bellard
GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
1852 79aceca5 bellard
{
1853 79aceca5 bellard
    gen_op_load_crf_T0(crfS(ctx->opcode));
1854 79aceca5 bellard
    gen_op_store_T0_crf(crfD(ctx->opcode));
1855 79aceca5 bellard
}
1856 79aceca5 bellard
1857 79aceca5 bellard
/***                           System linkage                              ***/
1858 79aceca5 bellard
/* rfi (supervisor only) */
1859 79aceca5 bellard
GEN_HANDLER(rfi, 0x13, 0x12, 0xFF, 0x03FF8001, PPC_FLOW)
1860 79aceca5 bellard
{
1861 9a64fbe4 bellard
#if defined(CONFIG_USER_ONLY)
1862 9fddaa0c bellard
    RET_PRIVOPC(ctx);
1863 9a64fbe4 bellard
#else
1864 9a64fbe4 bellard
    /* Restore CPU state */
1865 9a64fbe4 bellard
    if (!ctx->supervisor) {
1866 9fddaa0c bellard
        RET_PRIVOPC(ctx);
1867 9fddaa0c bellard
        return;
1868 9a64fbe4 bellard
    }
1869 9a64fbe4 bellard
    gen_op_rfi();
1870 9fddaa0c bellard
    RET_EXCP(ctx, EXCP_RFI, 0);
1871 9a64fbe4 bellard
#endif
1872 79aceca5 bellard
}
1873 79aceca5 bellard
1874 79aceca5 bellard
/* sc */
1875 79aceca5 bellard
GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFFFFD, PPC_FLOW)
1876 79aceca5 bellard
{
1877 9a64fbe4 bellard
#if defined(CONFIG_USER_ONLY)
1878 9fddaa0c bellard
    RET_EXCP(ctx, EXCP_SYSCALL_USER, 0);
1879 9a64fbe4 bellard
#else
1880 9fddaa0c bellard
    RET_EXCP(ctx, EXCP_SYSCALL, 0);
1881 9a64fbe4 bellard
#endif
1882 79aceca5 bellard
}
1883 79aceca5 bellard
1884 79aceca5 bellard
/***                                Trap                                   ***/
1885 79aceca5 bellard
/* tw */
1886 79aceca5 bellard
GEN_HANDLER(tw, 0x1F, 0x04, 0xFF, 0x00000001, PPC_FLOW)
1887 79aceca5 bellard
{
1888 9a64fbe4 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));
1889 9a64fbe4 bellard
    gen_op_load_gpr_T1(rB(ctx->opcode));
1890 9a64fbe4 bellard
    gen_op_tw(TO(ctx->opcode));
1891 79aceca5 bellard
}
1892 79aceca5 bellard
1893 79aceca5 bellard
/* twi */
1894 79aceca5 bellard
GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1895 79aceca5 bellard
{
1896 9a64fbe4 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));
1897 9a64fbe4 bellard
#if 0
1898 9a64fbe4 bellard
    printf("%s: param=0x%04x T0=0x%04x\n", __func__,
1899 9a64fbe4 bellard
           SIMM(ctx->opcode), TO(ctx->opcode));
1900 9a64fbe4 bellard
#endif
1901 9a64fbe4 bellard
    gen_op_twi(SIMM(ctx->opcode), TO(ctx->opcode));
1902 79aceca5 bellard
}
1903 79aceca5 bellard
1904 79aceca5 bellard
/***                          Processor control                            ***/
1905 79aceca5 bellard
static inline int check_spr_access (int spr, int rw, int supervisor)
1906 79aceca5 bellard
{
1907 79aceca5 bellard
    uint32_t rights = spr_access[spr >> 1] >> (4 * (spr & 1));
1908 79aceca5 bellard
1909 9a64fbe4 bellard
#if 0
1910 9a64fbe4 bellard
    if (spr != LR && spr != CTR) {
1911 9a64fbe4 bellard
    if (loglevel > 0) {
1912 9a64fbe4 bellard
        fprintf(logfile, "%s reg=%d s=%d rw=%d r=0x%02x 0x%02x\n", __func__,
1913 9a64fbe4 bellard
                SPR_ENCODE(spr), supervisor, rw, rights,
1914 9a64fbe4 bellard
                (rights >> ((2 * supervisor) + rw)) & 1);
1915 9a64fbe4 bellard
    } else {
1916 9a64fbe4 bellard
        printf("%s reg=%d s=%d rw=%d r=0x%02x 0x%02x\n", __func__,
1917 9a64fbe4 bellard
               SPR_ENCODE(spr), supervisor, rw, rights,
1918 9a64fbe4 bellard
               (rights >> ((2 * supervisor) + rw)) & 1);
1919 9a64fbe4 bellard
    }
1920 9a64fbe4 bellard
    }
1921 9a64fbe4 bellard
#endif
1922 9a64fbe4 bellard
    if (rights == 0)
1923 9a64fbe4 bellard
        return -1;
1924 79aceca5 bellard
    rights = rights >> (2 * supervisor);
1925 79aceca5 bellard
    rights = rights >> rw;
1926 79aceca5 bellard
1927 79aceca5 bellard
    return rights & 1;
1928 79aceca5 bellard
}
1929 79aceca5 bellard
1930 79aceca5 bellard
/* mcrxr */
1931 79aceca5 bellard
GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
1932 79aceca5 bellard
{
1933 79aceca5 bellard
    gen_op_load_xer_cr();
1934 79aceca5 bellard
    gen_op_store_T0_crf(crfD(ctx->opcode));
1935 79aceca5 bellard
    gen_op_clear_xer_cr();
1936 79aceca5 bellard
}
1937 79aceca5 bellard
1938 79aceca5 bellard
/* mfcr */
1939 79aceca5 bellard
GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x001FF801, PPC_MISC)
1940 79aceca5 bellard
{
1941 79aceca5 bellard
    gen_op_load_cr();
1942 79aceca5 bellard
    gen_op_store_T0_gpr(rD(ctx->opcode));
1943 79aceca5 bellard
}
1944 79aceca5 bellard
1945 79aceca5 bellard
/* mfmsr */
1946 79aceca5 bellard
GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
1947 79aceca5 bellard
{
1948 9a64fbe4 bellard
#if defined(CONFIG_USER_ONLY)
1949 9fddaa0c bellard
    RET_PRIVREG(ctx);
1950 9a64fbe4 bellard
#else
1951 9a64fbe4 bellard
    if (!ctx->supervisor) {
1952 9fddaa0c bellard
        RET_PRIVREG(ctx);
1953 9fddaa0c bellard
        return;
1954 9a64fbe4 bellard
    }
1955 79aceca5 bellard
    gen_op_load_msr();
1956 79aceca5 bellard
    gen_op_store_T0_gpr(rD(ctx->opcode));
1957 9a64fbe4 bellard
#endif
1958 79aceca5 bellard
}
1959 79aceca5 bellard
1960 79aceca5 bellard
/* mfspr */
1961 79aceca5 bellard
GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
1962 79aceca5 bellard
{
1963 79aceca5 bellard
    uint32_t sprn = SPR(ctx->opcode);
1964 79aceca5 bellard
1965 9a64fbe4 bellard
#if defined(CONFIG_USER_ONLY)
1966 9a64fbe4 bellard
    switch (check_spr_access(sprn, 0, 0))
1967 9a64fbe4 bellard
#else
1968 9a64fbe4 bellard
    switch (check_spr_access(sprn, 0, ctx->supervisor))
1969 9a64fbe4 bellard
#endif
1970 9a64fbe4 bellard
    {
1971 9a64fbe4 bellard
    case -1:
1972 9fddaa0c bellard
        RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_SPR);
1973 9fddaa0c bellard
        return;
1974 9a64fbe4 bellard
    case 0:
1975 9fddaa0c bellard
        RET_PRIVREG(ctx);
1976 9fddaa0c bellard
        return;
1977 9a64fbe4 bellard
    default:
1978 9a64fbe4 bellard
        break;
1979 79aceca5 bellard
        }
1980 9a64fbe4 bellard
    switch (sprn) {
1981 9a64fbe4 bellard
    case XER:
1982 79aceca5 bellard
        gen_op_load_xer();
1983 79aceca5 bellard
        break;
1984 9a64fbe4 bellard
    case LR:
1985 9a64fbe4 bellard
        gen_op_load_lr();
1986 9a64fbe4 bellard
        break;
1987 9a64fbe4 bellard
    case CTR:
1988 9a64fbe4 bellard
        gen_op_load_ctr();
1989 9a64fbe4 bellard
        break;
1990 9a64fbe4 bellard
    case IBAT0U:
1991 9a64fbe4 bellard
        gen_op_load_ibat(0, 0);
1992 9a64fbe4 bellard
        break;
1993 9a64fbe4 bellard
    case IBAT1U:
1994 9a64fbe4 bellard
        gen_op_load_ibat(0, 1);
1995 9a64fbe4 bellard
        break;
1996 9a64fbe4 bellard
    case IBAT2U:
1997 9a64fbe4 bellard
        gen_op_load_ibat(0, 2);
1998 9a64fbe4 bellard
        break;
1999 9a64fbe4 bellard
    case IBAT3U:
2000 9a64fbe4 bellard
        gen_op_load_ibat(0, 3);
2001 9a64fbe4 bellard
        break;
2002 9a64fbe4 bellard
    case IBAT4U:
2003 9a64fbe4 bellard
        gen_op_load_ibat(0, 4);
2004 9a64fbe4 bellard
        break;
2005 9a64fbe4 bellard
    case IBAT5U:
2006 9a64fbe4 bellard
        gen_op_load_ibat(0, 5);
2007 9a64fbe4 bellard
        break;
2008 9a64fbe4 bellard
    case IBAT6U:
2009 9a64fbe4 bellard
        gen_op_load_ibat(0, 6);
2010 9a64fbe4 bellard
        break;
2011 9a64fbe4 bellard
    case IBAT7U:
2012 9a64fbe4 bellard
        gen_op_load_ibat(0, 7);
2013 9a64fbe4 bellard
        break;
2014 9a64fbe4 bellard
    case IBAT0L:
2015 9a64fbe4 bellard
        gen_op_load_ibat(1, 0);
2016 9a64fbe4 bellard
        break;
2017 9a64fbe4 bellard
    case IBAT1L:
2018 9a64fbe4 bellard
        gen_op_load_ibat(1, 1);
2019 9a64fbe4 bellard
        break;
2020 9a64fbe4 bellard
    case IBAT2L:
2021 9a64fbe4 bellard
        gen_op_load_ibat(1, 2);
2022 9a64fbe4 bellard
        break;
2023 9a64fbe4 bellard
    case IBAT3L:
2024 9a64fbe4 bellard
        gen_op_load_ibat(1, 3);
2025 9a64fbe4 bellard
        break;
2026 9a64fbe4 bellard
    case IBAT4L:
2027 9a64fbe4 bellard
        gen_op_load_ibat(1, 4);
2028 9a64fbe4 bellard
        break;
2029 9a64fbe4 bellard
    case IBAT5L:
2030 9a64fbe4 bellard
        gen_op_load_ibat(1, 5);
2031 9a64fbe4 bellard
        break;
2032 9a64fbe4 bellard
    case IBAT6L:
2033 9a64fbe4 bellard
        gen_op_load_ibat(1, 6);
2034 9a64fbe4 bellard
        break;
2035 9a64fbe4 bellard
    case IBAT7L:
2036 9a64fbe4 bellard
        gen_op_load_ibat(1, 7);
2037 9a64fbe4 bellard
        break;
2038 9a64fbe4 bellard
    case DBAT0U:
2039 9a64fbe4 bellard
        gen_op_load_dbat(0, 0);
2040 9a64fbe4 bellard
        break;
2041 9a64fbe4 bellard
    case DBAT1U:
2042 9a64fbe4 bellard
        gen_op_load_dbat(0, 1);
2043 9a64fbe4 bellard
        break;
2044 9a64fbe4 bellard
    case DBAT2U:
2045 9a64fbe4 bellard
        gen_op_load_dbat(0, 2);
2046 9a64fbe4 bellard
        break;
2047 9a64fbe4 bellard
    case DBAT3U:
2048 9a64fbe4 bellard
        gen_op_load_dbat(0, 3);
2049 9a64fbe4 bellard
        break;
2050 9a64fbe4 bellard
    case DBAT4U:
2051 9a64fbe4 bellard
        gen_op_load_dbat(0, 4);
2052 9a64fbe4 bellard
        break;
2053 9a64fbe4 bellard
    case DBAT5U:
2054 9a64fbe4 bellard
        gen_op_load_dbat(0, 5);
2055 9a64fbe4 bellard
        break;
2056 9a64fbe4 bellard
    case DBAT6U:
2057 9a64fbe4 bellard
        gen_op_load_dbat(0, 6);
2058 9a64fbe4 bellard
        break;
2059 9a64fbe4 bellard
    case DBAT7U:
2060 9a64fbe4 bellard
        gen_op_load_dbat(0, 7);
2061 9a64fbe4 bellard
        break;
2062 9a64fbe4 bellard
    case DBAT0L:
2063 9a64fbe4 bellard
        gen_op_load_dbat(1, 0);
2064 9a64fbe4 bellard
        break;
2065 9a64fbe4 bellard
    case DBAT1L:
2066 9a64fbe4 bellard
        gen_op_load_dbat(1, 1);
2067 9a64fbe4 bellard
        break;
2068 9a64fbe4 bellard
    case DBAT2L:
2069 9a64fbe4 bellard
        gen_op_load_dbat(1, 2);
2070 9a64fbe4 bellard
        break;
2071 9a64fbe4 bellard
    case DBAT3L:
2072 9a64fbe4 bellard
        gen_op_load_dbat(1, 3);
2073 9a64fbe4 bellard
        break;
2074 9a64fbe4 bellard
    case DBAT4L:
2075 9a64fbe4 bellard
        gen_op_load_dbat(1, 4);
2076 9a64fbe4 bellard
        break;
2077 9a64fbe4 bellard
    case DBAT5L:
2078 9a64fbe4 bellard
        gen_op_load_dbat(1, 5);
2079 9a64fbe4 bellard
        break;
2080 9a64fbe4 bellard
    case DBAT6L:
2081 9a64fbe4 bellard
        gen_op_load_dbat(1, 6);
2082 9a64fbe4 bellard
        break;
2083 9a64fbe4 bellard
    case DBAT7L:
2084 9a64fbe4 bellard
        gen_op_load_dbat(1, 7);
2085 9a64fbe4 bellard
        break;
2086 9a64fbe4 bellard
    case SDR1:
2087 9a64fbe4 bellard
        gen_op_load_sdr1();
2088 9a64fbe4 bellard
        break;
2089 9a64fbe4 bellard
    case V_TBL:
2090 9fddaa0c bellard
        gen_op_load_tbl();
2091 79aceca5 bellard
        break;
2092 9a64fbe4 bellard
    case V_TBU:
2093 9fddaa0c bellard
        gen_op_load_tbu();
2094 9a64fbe4 bellard
        break;
2095 9a64fbe4 bellard
    case DECR:
2096 9fddaa0c bellard
        gen_op_load_decr();
2097 79aceca5 bellard
        break;
2098 79aceca5 bellard
    default:
2099 79aceca5 bellard
        gen_op_load_spr(sprn);
2100 79aceca5 bellard
        break;
2101 79aceca5 bellard
    }
2102 9a64fbe4 bellard
    gen_op_store_T0_gpr(rD(ctx->opcode));
2103 79aceca5 bellard
}
2104 79aceca5 bellard
2105 79aceca5 bellard
/* mftb */
2106 79aceca5 bellard
GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MISC)
2107 79aceca5 bellard
{
2108 79aceca5 bellard
    uint32_t sprn = SPR(ctx->opcode);
2109 79aceca5 bellard
2110 79aceca5 bellard
        /* We need to update the time base before reading it */
2111 9a64fbe4 bellard
    switch (sprn) {
2112 9a64fbe4 bellard
    case V_TBL:
2113 9fddaa0c bellard
        gen_op_load_tbl();
2114 79aceca5 bellard
        break;
2115 9a64fbe4 bellard
    case V_TBU:
2116 9fddaa0c bellard
        gen_op_load_tbu();
2117 79aceca5 bellard
        break;
2118 79aceca5 bellard
    default:
2119 9fddaa0c bellard
        RET_INVAL(ctx);
2120 9fddaa0c bellard
        return;
2121 79aceca5 bellard
    }
2122 9a64fbe4 bellard
    gen_op_store_T0_gpr(rD(ctx->opcode));
2123 79aceca5 bellard
}
2124 79aceca5 bellard
2125 79aceca5 bellard
/* mtcrf */
2126 79aceca5 bellard
GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00100801, PPC_MISC)
2127 79aceca5 bellard
{
2128 79aceca5 bellard
    gen_op_load_gpr_T0(rS(ctx->opcode));
2129 79aceca5 bellard
    gen_op_store_cr(CRM(ctx->opcode));
2130 79aceca5 bellard
}
2131 79aceca5 bellard
2132 79aceca5 bellard
/* mtmsr */
2133 79aceca5 bellard
GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
2134 79aceca5 bellard
{
2135 9a64fbe4 bellard
#if defined(CONFIG_USER_ONLY)
2136 9fddaa0c bellard
    RET_PRIVREG(ctx);
2137 9a64fbe4 bellard
#else
2138 9a64fbe4 bellard
    if (!ctx->supervisor) {
2139 9fddaa0c bellard
        RET_PRIVREG(ctx);
2140 9fddaa0c bellard
        return;
2141 9a64fbe4 bellard
    }
2142 79aceca5 bellard
    gen_op_load_gpr_T0(rS(ctx->opcode));
2143 79aceca5 bellard
    gen_op_store_msr();
2144 79aceca5 bellard
    /* Must stop the translation as machine state (may have) changed */
2145 9fddaa0c bellard
    RET_MTMSR(ctx);
2146 9a64fbe4 bellard
#endif
2147 79aceca5 bellard
}
2148 79aceca5 bellard
2149 79aceca5 bellard
/* mtspr */
2150 79aceca5 bellard
GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
2151 79aceca5 bellard
{
2152 79aceca5 bellard
    uint32_t sprn = SPR(ctx->opcode);
2153 79aceca5 bellard
2154 9a64fbe4 bellard
#if 0
2155 9a64fbe4 bellard
    if (loglevel > 0) {
2156 9a64fbe4 bellard
        fprintf(logfile, "MTSPR %d src=%d (%d)\n", SPR_ENCODE(sprn),
2157 9a64fbe4 bellard
                rS(ctx->opcode), sprn);
2158 9a64fbe4 bellard
    }
2159 9a64fbe4 bellard
#endif
2160 9a64fbe4 bellard
#if defined(CONFIG_USER_ONLY)
2161 9a64fbe4 bellard
    switch (check_spr_access(sprn, 1, 0))
2162 9a64fbe4 bellard
#else
2163 9a64fbe4 bellard
    switch (check_spr_access(sprn, 1, ctx->supervisor))
2164 9a64fbe4 bellard
#endif
2165 9a64fbe4 bellard
    {
2166 9a64fbe4 bellard
    case -1:
2167 9fddaa0c bellard
        RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_SPR);
2168 9a64fbe4 bellard
        break;
2169 9a64fbe4 bellard
    case 0:
2170 9fddaa0c bellard
        RET_PRIVREG(ctx);
2171 9a64fbe4 bellard
        break;
2172 9a64fbe4 bellard
    default:
2173 9a64fbe4 bellard
        break;
2174 9a64fbe4 bellard
    }
2175 79aceca5 bellard
    gen_op_load_gpr_T0(rS(ctx->opcode));
2176 9a64fbe4 bellard
    switch (sprn) {
2177 9a64fbe4 bellard
    case XER:
2178 79aceca5 bellard
        gen_op_store_xer();
2179 9a64fbe4 bellard
        break;
2180 9a64fbe4 bellard
    case LR:
2181 9a64fbe4 bellard
        gen_op_store_lr();
2182 9a64fbe4 bellard
        break;
2183 9a64fbe4 bellard
    case CTR:
2184 9a64fbe4 bellard
        gen_op_store_ctr();
2185 9a64fbe4 bellard
        break;
2186 9a64fbe4 bellard
    case IBAT0U:
2187 9a64fbe4 bellard
        gen_op_store_ibat(0, 0);
2188 4b3686fa bellard
        RET_MTMSR(ctx);
2189 9a64fbe4 bellard
        break;
2190 9a64fbe4 bellard
    case IBAT1U:
2191 9a64fbe4 bellard
        gen_op_store_ibat(0, 1);
2192 4b3686fa bellard
        RET_MTMSR(ctx);
2193 9a64fbe4 bellard
        break;
2194 9a64fbe4 bellard
    case IBAT2U:
2195 9a64fbe4 bellard
        gen_op_store_ibat(0, 2);
2196 4b3686fa bellard
        RET_MTMSR(ctx);
2197 9a64fbe4 bellard
        break;
2198 9a64fbe4 bellard
    case IBAT3U:
2199 9a64fbe4 bellard
        gen_op_store_ibat(0, 3);
2200 4b3686fa bellard
        RET_MTMSR(ctx);
2201 9a64fbe4 bellard
        break;
2202 9a64fbe4 bellard
    case IBAT4U:
2203 9a64fbe4 bellard
        gen_op_store_ibat(0, 4);
2204 4b3686fa bellard
        RET_MTMSR(ctx);
2205 9a64fbe4 bellard
        break;
2206 9a64fbe4 bellard
    case IBAT5U:
2207 9a64fbe4 bellard
        gen_op_store_ibat(0, 5);
2208 4b3686fa bellard
        RET_MTMSR(ctx);
2209 9a64fbe4 bellard
        break;
2210 9a64fbe4 bellard
    case IBAT6U:
2211 9a64fbe4 bellard
        gen_op_store_ibat(0, 6);
2212 4b3686fa bellard
        RET_MTMSR(ctx);
2213 9a64fbe4 bellard
        break;
2214 9a64fbe4 bellard
    case IBAT7U:
2215 9a64fbe4 bellard
        gen_op_store_ibat(0, 7);
2216 4b3686fa bellard
        RET_MTMSR(ctx);
2217 9a64fbe4 bellard
        break;
2218 9a64fbe4 bellard
    case IBAT0L:
2219 9a64fbe4 bellard
        gen_op_store_ibat(1, 0);
2220 4b3686fa bellard
        RET_MTMSR(ctx);
2221 9a64fbe4 bellard
        break;
2222 9a64fbe4 bellard
    case IBAT1L:
2223 9a64fbe4 bellard
        gen_op_store_ibat(1, 1);
2224 4b3686fa bellard
        RET_MTMSR(ctx);
2225 9a64fbe4 bellard
        break;
2226 9a64fbe4 bellard
    case IBAT2L:
2227 9a64fbe4 bellard
        gen_op_store_ibat(1, 2);
2228 4b3686fa bellard
        RET_MTMSR(ctx);
2229 9a64fbe4 bellard
        break;
2230 9a64fbe4 bellard
    case IBAT3L:
2231 9a64fbe4 bellard
        gen_op_store_ibat(1, 3);
2232 4b3686fa bellard
        RET_MTMSR(ctx);
2233 9a64fbe4 bellard
        break;
2234 9a64fbe4 bellard
    case IBAT4L:
2235 9a64fbe4 bellard
        gen_op_store_ibat(1, 4);
2236 4b3686fa bellard
        RET_MTMSR(ctx);
2237 9a64fbe4 bellard
        break;
2238 9a64fbe4 bellard
    case IBAT5L:
2239 9a64fbe4 bellard
        gen_op_store_ibat(1, 5);
2240 4b3686fa bellard
        RET_MTMSR(ctx);
2241 9a64fbe4 bellard
        break;
2242 9a64fbe4 bellard
    case IBAT6L:
2243 9a64fbe4 bellard
        gen_op_store_ibat(1, 6);
2244 4b3686fa bellard
        RET_MTMSR(ctx);
2245 9a64fbe4 bellard
        break;
2246 9a64fbe4 bellard
    case IBAT7L:
2247 9a64fbe4 bellard
        gen_op_store_ibat(1, 7);
2248 4b3686fa bellard
        RET_MTMSR(ctx);
2249 9a64fbe4 bellard
        break;
2250 9a64fbe4 bellard
    case DBAT0U:
2251 9a64fbe4 bellard
        gen_op_store_dbat(0, 0);
2252 4b3686fa bellard
        RET_MTMSR(ctx);
2253 9a64fbe4 bellard
        break;
2254 9a64fbe4 bellard
    case DBAT1U:
2255 9a64fbe4 bellard
        gen_op_store_dbat(0, 1);
2256 4b3686fa bellard
        RET_MTMSR(ctx);
2257 9a64fbe4 bellard
        break;
2258 9a64fbe4 bellard
    case DBAT2U:
2259 9a64fbe4 bellard
        gen_op_store_dbat(0, 2);
2260 4b3686fa bellard
        RET_MTMSR(ctx);
2261 9a64fbe4 bellard
        break;
2262 9a64fbe4 bellard
    case DBAT3U:
2263 9a64fbe4 bellard
        gen_op_store_dbat(0, 3);
2264 4b3686fa bellard
        RET_MTMSR(ctx);
2265 9a64fbe4 bellard
        break;
2266 9a64fbe4 bellard
    case DBAT4U:
2267 9a64fbe4 bellard
        gen_op_store_dbat(0, 4);
2268 4b3686fa bellard
        RET_MTMSR(ctx);
2269 9a64fbe4 bellard
        break;
2270 9a64fbe4 bellard
    case DBAT5U:
2271 9a64fbe4 bellard
        gen_op_store_dbat(0, 5);
2272 4b3686fa bellard
        RET_MTMSR(ctx);
2273 9a64fbe4 bellard
        break;
2274 9a64fbe4 bellard
    case DBAT6U:
2275 9a64fbe4 bellard
        gen_op_store_dbat(0, 6);
2276 4b3686fa bellard
        RET_MTMSR(ctx);
2277 9a64fbe4 bellard
        break;
2278 9a64fbe4 bellard
    case DBAT7U:
2279 9a64fbe4 bellard
        gen_op_store_dbat(0, 7);
2280 4b3686fa bellard
        RET_MTMSR(ctx);
2281 9a64fbe4 bellard
        break;
2282 9a64fbe4 bellard
    case DBAT0L:
2283 9a64fbe4 bellard
        gen_op_store_dbat(1, 0);
2284 4b3686fa bellard
        RET_MTMSR(ctx);
2285 9a64fbe4 bellard
        break;
2286 9a64fbe4 bellard
    case DBAT1L:
2287 9a64fbe4 bellard
        gen_op_store_dbat(1, 1);
2288 4b3686fa bellard
        RET_MTMSR(ctx);
2289 9a64fbe4 bellard
        break;
2290 9a64fbe4 bellard
    case DBAT2L:
2291 9a64fbe4 bellard
        gen_op_store_dbat(1, 2);
2292 4b3686fa bellard
        RET_MTMSR(ctx);
2293 9a64fbe4 bellard
        break;
2294 9a64fbe4 bellard
    case DBAT3L:
2295 9a64fbe4 bellard
        gen_op_store_dbat(1, 3);
2296 4b3686fa bellard
        RET_MTMSR(ctx);
2297 9a64fbe4 bellard
        break;
2298 9a64fbe4 bellard
    case DBAT4L:
2299 9a64fbe4 bellard
        gen_op_store_dbat(1, 4);
2300 4b3686fa bellard
        RET_MTMSR(ctx);
2301 9a64fbe4 bellard
        break;
2302 9a64fbe4 bellard
    case DBAT5L:
2303 9a64fbe4 bellard
        gen_op_store_dbat(1, 5);
2304 4b3686fa bellard
        RET_MTMSR(ctx);
2305 9a64fbe4 bellard
        break;
2306 9a64fbe4 bellard
    case DBAT6L:
2307 9a64fbe4 bellard
        gen_op_store_dbat(1, 6);
2308 4b3686fa bellard
        RET_MTMSR(ctx);
2309 9a64fbe4 bellard
        break;
2310 9a64fbe4 bellard
    case DBAT7L:
2311 9a64fbe4 bellard
        gen_op_store_dbat(1, 7);
2312 4b3686fa bellard
        RET_MTMSR(ctx);
2313 9a64fbe4 bellard
        break;
2314 9a64fbe4 bellard
    case SDR1:
2315 9a64fbe4 bellard
        gen_op_store_sdr1();
2316 4b3686fa bellard
        RET_MTMSR(ctx);
2317 9a64fbe4 bellard
        break;
2318 9a64fbe4 bellard
    case O_TBL:
2319 9fddaa0c bellard
        gen_op_store_tbl();
2320 9a64fbe4 bellard
        break;
2321 9a64fbe4 bellard
    case O_TBU:
2322 9fddaa0c bellard
        gen_op_store_tbu();
2323 9a64fbe4 bellard
        break;
2324 9a64fbe4 bellard
    case DECR:
2325 9a64fbe4 bellard
        gen_op_store_decr();
2326 9a64fbe4 bellard
        break;
2327 9a64fbe4 bellard
    default:
2328 79aceca5 bellard
        gen_op_store_spr(sprn);
2329 9a64fbe4 bellard
        break;
2330 79aceca5 bellar