root / target-ppc / helper.c @ 71be0fc3
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/*
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* PPC emulation helpers for qemu.
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*
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* Copyright (c) 2003 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include "exec.h" |
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//#define DEBUG_MMU
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//#define DEBUG_BATS
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//#define DEBUG_EXCEPTIONS
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/* accurate but slower TLB flush in exceptions */
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//#define ACCURATE_TLB_FLUSH
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/*****************************************************************************/
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/* PPC MMU emulation */
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/* Perform BAT hit & translation */
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static int get_bat (CPUState *env, uint32_t *real, int *prot, |
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uint32_t virtual, int rw, int type) |
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{ |
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uint32_t *BATlt, *BATut, *BATu, *BATl; |
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uint32_t base, BEPIl, BEPIu, bl; |
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int i;
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int ret = -1; |
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#if defined (DEBUG_BATS)
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if (loglevel > 0) { |
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fprintf(logfile, "%s: %cBAT v 0x%08x\n", __func__,
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type == ACCESS_CODE ? 'I' : 'D', virtual); |
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} |
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#endif
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switch (type) {
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case ACCESS_CODE:
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BATlt = env->IBAT[1];
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BATut = env->IBAT[0];
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break;
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default:
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BATlt = env->DBAT[1];
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BATut = env->DBAT[0];
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break;
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} |
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#if defined (DEBUG_BATS)
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if (loglevel > 0) { |
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fprintf(logfile, "%s...: %cBAT v 0x%08x\n", __func__,
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type == ACCESS_CODE ? 'I' : 'D', virtual); |
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} |
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#endif
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base = virtual & 0xFFFC0000;
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for (i = 0; i < 4; i++) { |
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BATu = &BATut[i]; |
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BATl = &BATlt[i]; |
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BEPIu = *BATu & 0xF0000000;
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BEPIl = *BATu & 0x0FFE0000;
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bl = (*BATu & 0x00001FFC) << 15; |
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#if defined (DEBUG_BATS)
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if (loglevel > 0) { |
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fprintf(logfile, "%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x\n",
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__func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual, |
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*BATu, *BATl); |
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} |
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#endif
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if ((virtual & 0xF0000000) == BEPIu && |
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((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
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/* BAT matches */
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if ((msr_pr == 0 && (*BATu & 0x00000002)) || |
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(msr_pr == 1 && (*BATu & 0x00000001))) { |
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/* Get physical address */
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*real = (*BATl & 0xF0000000) |
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((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) | |
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(virtual & 0x0001F000);
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if (*BATl & 0x00000001) |
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*prot = PAGE_READ; |
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if (*BATl & 0x00000002) |
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*prot = PAGE_WRITE | PAGE_READ; |
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#if defined (DEBUG_BATS)
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if (loglevel > 0) { |
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fprintf(logfile, "BAT %d match: r 0x%08x prot=%c%c\n",
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i, *real, *prot & PAGE_READ ? 'R' : '-', |
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*prot & PAGE_WRITE ? 'W' : '-'); |
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} |
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#endif
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ret = 0;
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break;
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} |
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} |
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} |
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if (ret < 0) { |
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#if defined (DEBUG_BATS)
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printf("no BAT match for 0x%08x:\n", virtual);
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for (i = 0; i < 4; i++) { |
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BATu = &BATut[i]; |
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BATl = &BATlt[i]; |
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BEPIu = *BATu & 0xF0000000;
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BEPIl = *BATu & 0x0FFE0000;
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bl = (*BATu & 0x00001FFC) << 15; |
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printf("%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x \n\t"
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"0x%08x 0x%08x 0x%08x\n",
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__func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual, |
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*BATu, *BATl, BEPIu, BEPIl, bl); |
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} |
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#endif
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} |
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/* No hit */
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return ret;
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} |
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/* PTE table lookup */
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static int find_pte (uint32_t *RPN, int *prot, uint32_t base, uint32_t va, |
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int h, int key, int rw) |
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{ |
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uint32_t pte0, pte1, keep = 0, access = 0; |
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int i, good = -1, store = 0; |
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int ret = -1; /* No entry found */ |
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for (i = 0; i < 8; i++) { |
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pte0 = ldl_phys(base + (i * 8));
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pte1 = ldl_phys(base + (i * 8) + 4); |
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#if defined (DEBUG_MMU)
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if (loglevel > 0) { |
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fprintf(logfile, "Load pte from 0x%08x => 0x%08x 0x%08x "
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"%d %d %d 0x%08x\n", base + (i * 8), pte0, pte1, |
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pte0 >> 31, h, (pte0 >> 6) & 1, va); |
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} |
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#endif
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/* Check validity and table match */
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if (pte0 & 0x80000000 && (h == ((pte0 >> 6) & 1))) { |
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/* Check vsid & api */
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if ((pte0 & 0x7FFFFFBF) == va) { |
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if (good == -1) { |
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good = i; |
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keep = pte1; |
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} else {
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/* All matches should have equal RPN, WIMG & PP */
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if ((keep & 0xFFFFF07B) != (pte1 & 0xFFFFF07B)) { |
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if (loglevel > 0) |
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fprintf(logfile, "Bad RPN/WIMG/PP\n");
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return -1; |
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} |
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} |
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/* Check access rights */
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if (key == 0) { |
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access = PAGE_READ; |
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if ((pte1 & 0x00000003) != 0x3) |
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access |= PAGE_WRITE; |
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} else {
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switch (pte1 & 0x00000003) { |
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case 0x0: |
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access = 0;
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break;
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case 0x1: |
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case 0x3: |
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access = PAGE_READ; |
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break;
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case 0x2: |
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access = PAGE_READ | PAGE_WRITE; |
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break;
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} |
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} |
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if (ret < 0) { |
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if ((rw == 0 && (access & PAGE_READ)) || |
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(rw == 1 && (access & PAGE_WRITE))) {
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#if defined (DEBUG_MMU)
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if (loglevel > 0) |
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fprintf(logfile, "PTE access granted !\n");
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#endif
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good = i; |
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keep = pte1; |
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ret = 0;
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} else {
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/* Access right violation */
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ret = -2;
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#if defined (DEBUG_MMU)
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if (loglevel > 0) |
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fprintf(logfile, "PTE access rejected\n");
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#endif
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} |
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*prot = access; |
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} |
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} |
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} |
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} |
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if (good != -1) { |
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*RPN = keep & 0xFFFFF000;
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#if defined (DEBUG_MMU)
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if (loglevel > 0) { |
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fprintf(logfile, "found PTE at addr 0x%08x prot=0x%01x ret=%d\n",
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*RPN, *prot, ret); |
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} |
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#endif
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/* Update page flags */
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if (!(keep & 0x00000100)) { |
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/* Access flag */
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keep |= 0x00000100;
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store = 1;
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} |
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if (!(keep & 0x00000080)) { |
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if (rw && ret == 0) { |
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/* Change flag */
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keep |= 0x00000080;
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store = 1;
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} else {
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/* Force page fault for first write access */
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*prot &= ~PAGE_WRITE; |
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} |
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} |
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if (store) {
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stl_phys_notdirty(base + (good * 8) + 4, keep); |
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} |
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} |
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return ret;
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} |
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static inline uint32_t get_pgaddr (uint32_t sdr1, uint32_t hash, uint32_t mask) |
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{ |
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return (sdr1 & 0xFFFF0000) | (hash & mask); |
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} |
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/* Perform segment based translation */
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static int get_segment (CPUState *env, uint32_t *real, int *prot, |
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uint32_t virtual, int rw, int type) |
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{ |
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uint32_t pg_addr, sdr, ptem, vsid, pgidx; |
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uint32_t hash, mask; |
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uint32_t sr; |
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int key;
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int ret = -1, ret2; |
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sr = env->sr[virtual >> 28];
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#if defined (DEBUG_MMU)
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if (loglevel > 0) { |
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fprintf(logfile, "Check segment v=0x%08x %d 0x%08x nip=0x%08x "
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"lr=0x%08x ir=%d dr=%d pr=%d %d t=%d\n",
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virtual, virtual >> 28, sr, env->nip,
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env->lr, msr_ir, msr_dr, msr_pr, rw, type); |
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} |
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#endif
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key = (((sr & 0x20000000) && msr_pr == 1) || |
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((sr & 0x40000000) && msr_pr == 0)) ? 1 : 0; |
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if ((sr & 0x80000000) == 0) { |
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#if defined (DEBUG_MMU)
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if (loglevel > 0) |
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fprintf(logfile, "pte segment: key=%d n=0x%08x\n",
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key, sr & 0x10000000);
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#endif
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/* Check if instruction fetch is allowed, if needed */
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if (type != ACCESS_CODE || (sr & 0x10000000) == 0) { |
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/* Page address translation */
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vsid = sr & 0x00FFFFFF;
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pgidx = (virtual >> 12) & 0xFFFF; |
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sdr = env->sdr1; |
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hash = ((vsid ^ pgidx) & 0x0007FFFF) << 6; |
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mask = ((sdr & 0x000001FF) << 16) | 0xFFC0; |
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pg_addr = get_pgaddr(sdr, hash, mask); |
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ptem = (vsid << 7) | (pgidx >> 10); |
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#if defined (DEBUG_MMU)
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if (loglevel > 0) { |
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fprintf(logfile, "0 sdr1=0x%08x vsid=0x%06x api=0x%04x "
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"hash=0x%07x pg_addr=0x%08x\n", sdr, vsid, pgidx, hash,
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pg_addr); |
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} |
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#endif
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/* Primary table lookup */
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ret = find_pte(real, prot, pg_addr, ptem, 0, key, rw);
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if (ret < 0) { |
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/* Secondary table lookup */
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hash = (~hash) & 0x01FFFFC0;
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pg_addr = get_pgaddr(sdr, hash, mask); |
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#if defined (DEBUG_MMU)
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if (virtual != 0xEFFFFFFF && loglevel > 0) { |
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fprintf(logfile, "1 sdr1=0x%08x vsid=0x%06x api=0x%04x "
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"hash=0x%05x pg_addr=0x%08x\n", sdr, vsid, pgidx,
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hash, pg_addr); |
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} |
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#endif
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ret2 = find_pte(real, prot, pg_addr, ptem, 1, key, rw);
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if (ret2 != -1) |
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ret = ret2; |
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} |
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} else {
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#if defined (DEBUG_MMU)
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if (loglevel > 0) |
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fprintf(logfile, "No access allowed\n");
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#endif
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ret = -3;
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} |
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} else {
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#if defined (DEBUG_MMU)
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if (loglevel > 0) |
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fprintf(logfile, "direct store...\n");
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#endif
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/* Direct-store segment : absolutely *BUGGY* for now */
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switch (type) {
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case ACCESS_INT:
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/* Integer load/store : only access allowed */
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break;
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case ACCESS_CODE:
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/* No code fetch is allowed in direct-store areas */
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return -4; |
314 |
case ACCESS_FLOAT:
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/* Floating point load/store */
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return -4; |
317 |
case ACCESS_RES:
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/* lwarx, ldarx or srwcx. */
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return -4; |
320 |
case ACCESS_CACHE:
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/* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
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/* Should make the instruction do no-op.
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* As it already do no-op, it's quite easy :-)
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*/
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*real = virtual; |
326 |
return 0; |
327 |
case ACCESS_EXT:
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/* eciwx or ecowx */
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return -4; |
330 |
default:
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331 |
if (logfile) {
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fprintf(logfile, "ERROR: instruction should not need "
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"address translation\n");
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} |
335 |
printf("ERROR: instruction should not need "
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336 |
"address translation\n");
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337 |
return -4; |
338 |
} |
339 |
if ((rw == 1 || key != 1) && (rw == 0 || key != 0)) { |
340 |
*real = virtual; |
341 |
ret = 2;
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342 |
} else {
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343 |
ret = -2;
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344 |
} |
345 |
} |
346 |
|
347 |
return ret;
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} |
349 |
|
350 |
int get_physical_address (CPUState *env, uint32_t *physical, int *prot, |
351 |
uint32_t address, int rw, int access_type) |
352 |
{ |
353 |
int ret;
|
354 |
#if 0
|
355 |
if (loglevel > 0) {
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356 |
fprintf(logfile, "%s\n", __func__);
|
357 |
}
|
358 |
#endif
|
359 |
if ((access_type == ACCESS_CODE && msr_ir == 0) || |
360 |
(access_type != ACCESS_CODE && msr_dr == 0)) {
|
361 |
/* No address translation */
|
362 |
*physical = address & ~0xFFF;
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363 |
*prot = PAGE_READ | PAGE_WRITE; |
364 |
ret = 0;
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365 |
} else {
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366 |
/* Try to find a BAT */
|
367 |
ret = get_bat(env, physical, prot, address, rw, access_type); |
368 |
if (ret < 0) { |
369 |
/* We didn't match any BAT entry */
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370 |
ret = get_segment(env, physical, prot, address, rw, access_type); |
371 |
} |
372 |
} |
373 |
#if 0
|
374 |
if (loglevel > 0) {
|
375 |
fprintf(logfile, "%s address %08x => %08x\n",
|
376 |
__func__, address, *physical);
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377 |
}
|
378 |
#endif
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379 |
return ret;
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} |
381 |
|
382 |
#if defined(CONFIG_USER_ONLY)
|
383 |
target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
384 |
{ |
385 |
return addr;
|
386 |
} |
387 |
#else
|
388 |
target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
389 |
{ |
390 |
uint32_t phys_addr; |
391 |
int prot;
|
392 |
|
393 |
if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0) |
394 |
return -1; |
395 |
return phys_addr;
|
396 |
} |
397 |
#endif
|
398 |
|
399 |
#if !defined(CONFIG_USER_ONLY)
|
400 |
|
401 |
#define MMUSUFFIX _mmu
|
402 |
#define GETPC() (__builtin_return_address(0)) |
403 |
|
404 |
#define SHIFT 0 |
405 |
#include "softmmu_template.h" |
406 |
|
407 |
#define SHIFT 1 |
408 |
#include "softmmu_template.h" |
409 |
|
410 |
#define SHIFT 2 |
411 |
#include "softmmu_template.h" |
412 |
|
413 |
#define SHIFT 3 |
414 |
#include "softmmu_template.h" |
415 |
|
416 |
/* try to fill the TLB and return an exception if error. If retaddr is
|
417 |
NULL, it means that the function was called in C code (i.e. not
|
418 |
from generated code or from helper.c) */
|
419 |
/* XXX: fix it to restore all registers */
|
420 |
void tlb_fill(target_ulong addr, int is_write, int is_user, void *retaddr) |
421 |
{ |
422 |
TranslationBlock *tb; |
423 |
CPUState *saved_env; |
424 |
unsigned long pc; |
425 |
int ret;
|
426 |
|
427 |
/* XXX: hack to restore env in all cases, even if not called from
|
428 |
generated code */
|
429 |
saved_env = env; |
430 |
env = cpu_single_env; |
431 |
#if 0
|
432 |
{
|
433 |
unsigned long tlb_addrr, tlb_addrw;
|
434 |
int index;
|
435 |
index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
|
436 |
tlb_addrr = env->tlb_read[is_user][index].address;
|
437 |
tlb_addrw = env->tlb_write[is_user][index].address;
|
438 |
if (loglevel) {
|
439 |
fprintf(logfile,
|
440 |
"%s 1 %p %p idx=%d addr=0x%08lx tbl_addr=0x%08lx 0x%08lx "
|
441 |
"(0x%08lx 0x%08lx)\n", __func__, env,
|
442 |
&env->tlb_read[is_user][index], index, addr,
|
443 |
tlb_addrr, tlb_addrw, addr & TARGET_PAGE_MASK,
|
444 |
tlb_addrr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
|
445 |
}
|
446 |
}
|
447 |
#endif
|
448 |
ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, is_user, 1);
|
449 |
if (ret) {
|
450 |
if (retaddr) {
|
451 |
/* now we have a real cpu fault */
|
452 |
pc = (unsigned long)retaddr; |
453 |
tb = tb_find_pc(pc); |
454 |
if (tb) {
|
455 |
/* the PC is inside the translated code. It means that we have
|
456 |
a virtual CPU fault */
|
457 |
cpu_restore_state(tb, env, pc, NULL);
|
458 |
} |
459 |
} |
460 |
do_raise_exception_err(env->exception_index, env->error_code); |
461 |
} |
462 |
#if 0
|
463 |
{
|
464 |
unsigned long tlb_addrr, tlb_addrw;
|
465 |
int index;
|
466 |
index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
|
467 |
tlb_addrr = env->tlb_read[is_user][index].address;
|
468 |
tlb_addrw = env->tlb_write[is_user][index].address;
|
469 |
printf("%s 2 %p %p idx=%d addr=0x%08lx tbl_addr=0x%08lx 0x%08lx "
|
470 |
"(0x%08lx 0x%08lx)\n", __func__, env,
|
471 |
&env->tlb_read[is_user][index], index, addr,
|
472 |
tlb_addrr, tlb_addrw, addr & TARGET_PAGE_MASK,
|
473 |
tlb_addrr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
|
474 |
}
|
475 |
#endif
|
476 |
env = saved_env; |
477 |
} |
478 |
|
479 |
void cpu_ppc_init_mmu(CPUState *env)
|
480 |
{ |
481 |
/* Nothing to do: all translation are disabled */
|
482 |
} |
483 |
#endif
|
484 |
|
485 |
/* Perform address translation */
|
486 |
int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw, |
487 |
int is_user, int is_softmmu) |
488 |
{ |
489 |
uint32_t physical; |
490 |
int prot;
|
491 |
int exception = 0, error_code = 0; |
492 |
int access_type;
|
493 |
int ret = 0; |
494 |
|
495 |
if (rw == 2) { |
496 |
/* code access */
|
497 |
rw = 0;
|
498 |
access_type = ACCESS_CODE; |
499 |
} else {
|
500 |
/* data access */
|
501 |
/* XXX: put correct access by using cpu_restore_state()
|
502 |
correctly */
|
503 |
access_type = ACCESS_INT; |
504 |
// access_type = env->access_type;
|
505 |
} |
506 |
if (env->user_mode_only) {
|
507 |
/* user mode only emulation */
|
508 |
ret = -2;
|
509 |
goto do_fault;
|
510 |
} |
511 |
ret = get_physical_address(env, &physical, &prot, |
512 |
address, rw, access_type); |
513 |
if (ret == 0) { |
514 |
ret = tlb_set_page(env, address & ~0xFFF, physical, prot,
|
515 |
is_user, is_softmmu); |
516 |
} else if (ret < 0) { |
517 |
do_fault:
|
518 |
#if defined (DEBUG_MMU)
|
519 |
if (loglevel > 0) |
520 |
cpu_dump_state(env, logfile, fprintf, 0);
|
521 |
#endif
|
522 |
if (access_type == ACCESS_CODE) {
|
523 |
exception = EXCP_ISI; |
524 |
switch (ret) {
|
525 |
case -1: |
526 |
/* No matches in page tables */
|
527 |
error_code = EXCP_ISI_TRANSLATE; |
528 |
break;
|
529 |
case -2: |
530 |
/* Access rights violation */
|
531 |
error_code = EXCP_ISI_PROT; |
532 |
break;
|
533 |
case -3: |
534 |
/* No execute protection violation */
|
535 |
error_code = EXCP_ISI_NOEXEC; |
536 |
break;
|
537 |
case -4: |
538 |
/* Direct store exception */
|
539 |
/* No code fetch is allowed in direct-store areas */
|
540 |
error_code = EXCP_ISI_DIRECT; |
541 |
break;
|
542 |
} |
543 |
} else {
|
544 |
exception = EXCP_DSI; |
545 |
switch (ret) {
|
546 |
case -1: |
547 |
/* No matches in page tables */
|
548 |
error_code = EXCP_DSI_TRANSLATE; |
549 |
break;
|
550 |
case -2: |
551 |
/* Access rights violation */
|
552 |
error_code = EXCP_DSI_PROT; |
553 |
break;
|
554 |
case -4: |
555 |
/* Direct store exception */
|
556 |
switch (access_type) {
|
557 |
case ACCESS_FLOAT:
|
558 |
/* Floating point load/store */
|
559 |
exception = EXCP_ALIGN; |
560 |
error_code = EXCP_ALIGN_FP; |
561 |
break;
|
562 |
case ACCESS_RES:
|
563 |
/* lwarx, ldarx or srwcx. */
|
564 |
exception = EXCP_DSI; |
565 |
error_code = EXCP_DSI_NOTSUP | EXCP_DSI_DIRECT; |
566 |
break;
|
567 |
case ACCESS_EXT:
|
568 |
/* eciwx or ecowx */
|
569 |
exception = EXCP_DSI; |
570 |
error_code = EXCP_DSI_NOTSUP | EXCP_DSI_DIRECT | |
571 |
EXCP_DSI_ECXW; |
572 |
break;
|
573 |
default:
|
574 |
printf("DSI: invalid exception (%d)\n", ret);
|
575 |
exception = EXCP_PROGRAM; |
576 |
error_code = EXCP_INVAL | EXCP_INVAL_INVAL; |
577 |
break;
|
578 |
} |
579 |
} |
580 |
if (rw)
|
581 |
error_code |= EXCP_DSI_STORE; |
582 |
/* Store fault address */
|
583 |
env->spr[DAR] = address; |
584 |
} |
585 |
#if 0
|
586 |
printf("%s: set exception to %d %02x\n",
|
587 |
__func__, exception, error_code);
|
588 |
#endif
|
589 |
env->exception_index = exception; |
590 |
env->error_code = error_code; |
591 |
ret = 1;
|
592 |
} |
593 |
return ret;
|
594 |
} |
595 |
|
596 |
uint32_t _load_xer (CPUState *env) |
597 |
{ |
598 |
return (xer_so << XER_SO) |
|
599 |
(xer_ov << XER_OV) | |
600 |
(xer_ca << XER_CA) | |
601 |
(xer_bc << XER_BC); |
602 |
} |
603 |
|
604 |
void _store_xer (CPUState *env, uint32_t value)
|
605 |
{ |
606 |
xer_so = (value >> XER_SO) & 0x01;
|
607 |
xer_ov = (value >> XER_OV) & 0x01;
|
608 |
xer_ca = (value >> XER_CA) & 0x01;
|
609 |
xer_bc = (value >> XER_BC) & 0x3f;
|
610 |
} |
611 |
|
612 |
uint32_t _load_msr (CPUState *env) |
613 |
{ |
614 |
return (msr_pow << MSR_POW) |
|
615 |
(msr_ile << MSR_ILE) | |
616 |
(msr_ee << MSR_EE) | |
617 |
(msr_pr << MSR_PR) | |
618 |
(msr_fp << MSR_FP) | |
619 |
(msr_me << MSR_ME) | |
620 |
(msr_fe0 << MSR_FE0) | |
621 |
(msr_se << MSR_SE) | |
622 |
(msr_be << MSR_BE) | |
623 |
(msr_fe1 << MSR_FE1) | |
624 |
(msr_ip << MSR_IP) | |
625 |
(msr_ir << MSR_IR) | |
626 |
(msr_dr << MSR_DR) | |
627 |
(msr_ri << MSR_RI) | |
628 |
(msr_le << MSR_LE); |
629 |
} |
630 |
|
631 |
void _store_msr (CPUState *env, uint32_t value)
|
632 |
{ |
633 |
#ifdef ACCURATE_TLB_FLUSH
|
634 |
if (((value >> MSR_IR) & 0x01) != msr_ir || |
635 |
((value >> MSR_DR) & 0x01) != msr_dr)
|
636 |
{ |
637 |
/* Flush all tlb when changing translation mode or privilege level */
|
638 |
tlb_flush(env, 1);
|
639 |
} |
640 |
#endif
|
641 |
msr_pow = (value >> MSR_POW) & 0x03;
|
642 |
msr_ile = (value >> MSR_ILE) & 0x01;
|
643 |
msr_ee = (value >> MSR_EE) & 0x01;
|
644 |
msr_pr = (value >> MSR_PR) & 0x01;
|
645 |
msr_fp = (value >> MSR_FP) & 0x01;
|
646 |
msr_me = (value >> MSR_ME) & 0x01;
|
647 |
msr_fe0 = (value >> MSR_FE0) & 0x01;
|
648 |
msr_se = (value >> MSR_SE) & 0x01;
|
649 |
msr_be = (value >> MSR_BE) & 0x01;
|
650 |
msr_fe1 = (value >> MSR_FE1) & 0x01;
|
651 |
msr_ip = (value >> MSR_IP) & 0x01;
|
652 |
msr_ir = (value >> MSR_IR) & 0x01;
|
653 |
msr_dr = (value >> MSR_DR) & 0x01;
|
654 |
msr_ri = (value >> MSR_RI) & 0x01;
|
655 |
msr_le = (value >> MSR_LE) & 0x01;
|
656 |
/* XXX: should enter PM state if msr_pow has been set */
|
657 |
} |
658 |
|
659 |
#if defined (CONFIG_USER_ONLY)
|
660 |
void do_interrupt (CPUState *env)
|
661 |
{ |
662 |
env->exception_index = -1;
|
663 |
} |
664 |
#else
|
665 |
static void dump_syscall(CPUState *env) |
666 |
{ |
667 |
fprintf(logfile, "syscall r0=0x%08x r3=0x%08x r4=0x%08x r5=0x%08x r6=0x%08x nip=0x%08x\n",
|
668 |
env->gpr[0], env->gpr[3], env->gpr[4], |
669 |
env->gpr[5], env->gpr[6], env->nip); |
670 |
} |
671 |
|
672 |
void do_interrupt (CPUState *env)
|
673 |
{ |
674 |
uint32_t msr; |
675 |
int excp;
|
676 |
|
677 |
excp = env->exception_index; |
678 |
msr = _load_msr(env); |
679 |
#if defined (DEBUG_EXCEPTIONS)
|
680 |
if ((excp == EXCP_PROGRAM || excp == EXCP_DSI) && msr_pr == 1) |
681 |
{ |
682 |
if (loglevel > 0) { |
683 |
fprintf(logfile, "Raise exception at 0x%08x => 0x%08x (%02x)\n",
|
684 |
env->nip, excp << 8, env->error_code);
|
685 |
} |
686 |
if (loglevel > 0) |
687 |
cpu_dump_state(env, logfile, fprintf, 0);
|
688 |
} |
689 |
#endif
|
690 |
if (loglevel & CPU_LOG_INT) {
|
691 |
fprintf(logfile, "Raise exception at 0x%08x => 0x%08x (%02x)\n",
|
692 |
env->nip, excp << 8, env->error_code);
|
693 |
} |
694 |
/* Generate informations in save/restore registers */
|
695 |
switch (excp) {
|
696 |
case EXCP_NONE:
|
697 |
/* Do nothing */
|
698 |
#if defined (DEBUG_EXCEPTIONS)
|
699 |
printf("%s: escape EXCP_NONE\n", __func__);
|
700 |
#endif
|
701 |
return;
|
702 |
case EXCP_RESET:
|
703 |
if (msr_ip)
|
704 |
excp += 0xFFC00;
|
705 |
goto store_next;
|
706 |
case EXCP_MACHINE_CHECK:
|
707 |
if (msr_me == 0) { |
708 |
cpu_abort(env, "Machine check exception while not allowed\n");
|
709 |
} |
710 |
msr_me = 0;
|
711 |
break;
|
712 |
case EXCP_DSI:
|
713 |
/* Store exception cause */
|
714 |
/* data location address has been stored
|
715 |
* when the fault has been detected
|
716 |
*/
|
717 |
msr &= ~0xFFFF0000;
|
718 |
env->spr[DSISR] = 0;
|
719 |
if ((env->error_code & 0x0f) == EXCP_DSI_TRANSLATE) |
720 |
env->spr[DSISR] |= 0x40000000;
|
721 |
else if ((env->error_code & 0x0f) == EXCP_DSI_PROT) |
722 |
env->spr[DSISR] |= 0x08000000;
|
723 |
else if ((env->error_code & 0x0f) == EXCP_DSI_NOTSUP) { |
724 |
env->spr[DSISR] |= 0x80000000;
|
725 |
if (env->error_code & EXCP_DSI_DIRECT)
|
726 |
env->spr[DSISR] |= 0x04000000;
|
727 |
} |
728 |
if (env->error_code & EXCP_DSI_STORE)
|
729 |
env->spr[DSISR] |= 0x02000000;
|
730 |
if ((env->error_code & 0xF) == EXCP_DSI_DABR) |
731 |
env->spr[DSISR] |= 0x00400000;
|
732 |
if (env->error_code & EXCP_DSI_ECXW)
|
733 |
env->spr[DSISR] |= 0x00100000;
|
734 |
#if defined (DEBUG_EXCEPTIONS)
|
735 |
if (loglevel) {
|
736 |
fprintf(logfile, "DSI exception: DSISR=0x%08x, DAR=0x%08x\n",
|
737 |
env->spr[DSISR], env->spr[DAR]); |
738 |
} else {
|
739 |
printf("DSI exception: DSISR=0x%08x, DAR=0x%08x nip=0x%08x\n",
|
740 |
env->spr[DSISR], env->spr[DAR], env->nip); |
741 |
} |
742 |
#endif
|
743 |
goto store_next;
|
744 |
case EXCP_ISI:
|
745 |
/* Store exception cause */
|
746 |
msr &= ~0xFFFF0000;
|
747 |
if (env->error_code == EXCP_ISI_TRANSLATE)
|
748 |
msr |= 0x40000000;
|
749 |
else if (env->error_code == EXCP_ISI_NOEXEC || |
750 |
env->error_code == EXCP_ISI_GUARD || |
751 |
env->error_code == EXCP_ISI_DIRECT) |
752 |
msr |= 0x10000000;
|
753 |
else
|
754 |
msr |= 0x08000000;
|
755 |
#if defined (DEBUG_EXCEPTIONS)
|
756 |
if (loglevel) {
|
757 |
fprintf(logfile, "ISI exception: msr=0x%08x, nip=0x%08x\n",
|
758 |
msr, env->nip); |
759 |
} else {
|
760 |
printf("ISI exception: msr=0x%08x, nip=0x%08x tbl:0x%08x\n",
|
761 |
msr, env->nip, env->spr[V_TBL]); |
762 |
} |
763 |
#endif
|
764 |
goto store_next;
|
765 |
case EXCP_EXTERNAL:
|
766 |
if (msr_ee == 0) { |
767 |
#if defined (DEBUG_EXCEPTIONS)
|
768 |
if (loglevel > 0) { |
769 |
fprintf(logfile, "Skipping hardware interrupt\n");
|
770 |
} |
771 |
#endif
|
772 |
/* Requeue it */
|
773 |
do_raise_exception(EXCP_EXTERNAL); |
774 |
return;
|
775 |
} |
776 |
goto store_next;
|
777 |
case EXCP_ALIGN:
|
778 |
/* Store exception cause */
|
779 |
/* Get rS/rD and rA from faulting opcode */
|
780 |
env->spr[DSISR] |= |
781 |
(ldl_code((env->nip - 4)) & 0x03FF0000) >> 16; |
782 |
/* data location address has been stored
|
783 |
* when the fault has been detected
|
784 |
*/
|
785 |
goto store_current;
|
786 |
case EXCP_PROGRAM:
|
787 |
msr &= ~0xFFFF0000;
|
788 |
switch (env->error_code & ~0xF) { |
789 |
case EXCP_FP:
|
790 |
if (msr_fe0 == 0 && msr_fe1 == 0) { |
791 |
#if defined (DEBUG_EXCEPTIONS)
|
792 |
printf("Ignore floating point exception\n");
|
793 |
#endif
|
794 |
return;
|
795 |
} |
796 |
msr |= 0x00100000;
|
797 |
/* Set FX */
|
798 |
env->fpscr[7] |= 0x8; |
799 |
/* Finally, update FEX */
|
800 |
if ((((env->fpscr[7] & 0x3) << 3) | (env->fpscr[6] >> 1)) & |
801 |
((env->fpscr[1] << 1) | (env->fpscr[0] >> 3))) |
802 |
env->fpscr[7] |= 0x4; |
803 |
break;
|
804 |
case EXCP_INVAL:
|
805 |
// printf("Invalid instruction at 0x%08x\n", env->nip);
|
806 |
msr |= 0x00080000;
|
807 |
break;
|
808 |
case EXCP_PRIV:
|
809 |
msr |= 0x00040000;
|
810 |
break;
|
811 |
case EXCP_TRAP:
|
812 |
msr |= 0x00020000;
|
813 |
break;
|
814 |
default:
|
815 |
/* Should never occur */
|
816 |
break;
|
817 |
} |
818 |
msr |= 0x00010000;
|
819 |
goto store_current;
|
820 |
case EXCP_NO_FP:
|
821 |
msr &= ~0xFFFF0000;
|
822 |
goto store_current;
|
823 |
case EXCP_DECR:
|
824 |
if (msr_ee == 0) { |
825 |
/* Requeue it */
|
826 |
do_raise_exception(EXCP_DECR); |
827 |
return;
|
828 |
} |
829 |
goto store_next;
|
830 |
case EXCP_SYSCALL:
|
831 |
/* NOTE: this is a temporary hack to support graphics OSI
|
832 |
calls from the MOL driver */
|
833 |
if (env->gpr[3] == 0x113724fa && env->gpr[4] == 0x77810f9b && |
834 |
env->osi_call) { |
835 |
if (env->osi_call(env) != 0) |
836 |
return;
|
837 |
} |
838 |
if (loglevel & CPU_LOG_INT) {
|
839 |
dump_syscall(env); |
840 |
} |
841 |
goto store_next;
|
842 |
case EXCP_TRACE:
|
843 |
goto store_next;
|
844 |
case EXCP_FP_ASSIST:
|
845 |
goto store_next;
|
846 |
case EXCP_MTMSR:
|
847 |
/* Nothing to do */
|
848 |
return;
|
849 |
case EXCP_BRANCH:
|
850 |
/* Nothing to do */
|
851 |
return;
|
852 |
case EXCP_RFI:
|
853 |
/* Restore user-mode state */
|
854 |
#if defined (DEBUG_EXCEPTIONS)
|
855 |
if (msr_pr == 1) |
856 |
printf("Return from exception => 0x%08x\n", (uint32_t)env->nip);
|
857 |
#endif
|
858 |
return;
|
859 |
store_current:
|
860 |
/* SRR0 is set to current instruction */
|
861 |
env->spr[SRR0] = (uint32_t)env->nip - 4;
|
862 |
break;
|
863 |
store_next:
|
864 |
/* SRR0 is set to next instruction */
|
865 |
env->spr[SRR0] = (uint32_t)env->nip; |
866 |
break;
|
867 |
} |
868 |
env->spr[SRR1] = msr; |
869 |
/* reload MSR with correct bits */
|
870 |
msr_pow = 0;
|
871 |
msr_ee = 0;
|
872 |
msr_pr = 0;
|
873 |
msr_fp = 0;
|
874 |
msr_fe0 = 0;
|
875 |
msr_se = 0;
|
876 |
msr_be = 0;
|
877 |
msr_fe1 = 0;
|
878 |
msr_ir = 0;
|
879 |
msr_dr = 0;
|
880 |
msr_ri = 0;
|
881 |
msr_le = msr_ile; |
882 |
/* Jump to handler */
|
883 |
env->nip = excp << 8;
|
884 |
env->exception_index = EXCP_NONE; |
885 |
/* Invalidate all TLB as we may have changed translation mode */
|
886 |
#ifdef ACCURATE_TLB_FLUSH
|
887 |
tlb_flush(env, 1);
|
888 |
#endif
|
889 |
/* ensure that no TB jump will be modified as
|
890 |
the program flow was changed */
|
891 |
#ifdef __sparc__
|
892 |
tmp_T0 = 0;
|
893 |
#else
|
894 |
T0 = 0;
|
895 |
#endif
|
896 |
env->exception_index = -1;
|
897 |
} |
898 |
#endif /* !CONFIG_USER_ONLY */ |