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1
/*
2
 * Copyright (C) 2010 Red Hat, Inc.
3
 *
4
 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann
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 * maintained by Gerd Hoffmann <kraxel@redhat.com>
6
 *
7
 * This program is free software; you can redistribute it and/or
8
 * modify it under the terms of the GNU General Public License as
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 * published by the Free Software Foundation; either version 2 or
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 * (at your option) version 3 of the License.
11
 *
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 * This program is distributed in the hope that it will be useful,
13
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 *
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 * You should have received a copy of the GNU General Public License
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 * along with this program; if not, see <http://www.gnu.org/licenses/>.
19
 */
20

    
21
#include <pthread.h>
22

    
23
#include "qemu-common.h"
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#include "qemu-timer.h"
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#include "qemu-queue.h"
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#include "monitor.h"
27
#include "sysemu.h"
28

    
29
#include "qxl.h"
30

    
31
#undef SPICE_RING_PROD_ITEM
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#define SPICE_RING_PROD_ITEM(r, ret) {                                  \
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        typeof(r) start = r;                                            \
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        typeof(r) end = r + 1;                                          \
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        uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r);           \
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        typeof(&(r)->items[prod]) m_item = &(r)->items[prod];           \
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        if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \
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            abort();                                                    \
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        }                                                               \
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        ret = &m_item->el;                                              \
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    }
42

    
43
#undef SPICE_RING_CONS_ITEM
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#define SPICE_RING_CONS_ITEM(r, ret) {                                  \
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        typeof(r) start = r;                                            \
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        typeof(r) end = r + 1;                                          \
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        uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r);           \
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        typeof(&(r)->items[cons]) m_item = &(r)->items[cons];           \
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        if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \
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            abort();                                                    \
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        }                                                               \
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        ret = &m_item->el;                                              \
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    }
54

    
55
#undef ALIGN
56
#define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1))
57

    
58
#define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9" 
59

    
60
#define QXL_MODE(_x, _y, _b, _o)                  \
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    {   .x_res = _x,                              \
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        .y_res = _y,                              \
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        .bits  = _b,                              \
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        .stride = (_x) * (_b) / 8,                \
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        .x_mili = PIXEL_SIZE * (_x),              \
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        .y_mili = PIXEL_SIZE * (_y),              \
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        .orientation = _o,                        \
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    }
69

    
70
#define QXL_MODE_16_32(x_res, y_res, orientation) \
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    QXL_MODE(x_res, y_res, 16, orientation),      \
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    QXL_MODE(x_res, y_res, 32, orientation)
73

    
74
#define QXL_MODE_EX(x_res, y_res)                 \
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    QXL_MODE_16_32(x_res, y_res, 0),              \
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    QXL_MODE_16_32(y_res, x_res, 1),              \
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    QXL_MODE_16_32(x_res, y_res, 2),              \
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    QXL_MODE_16_32(y_res, x_res, 3)
79

    
80
static QXLMode qxl_modes[] = {
81
    QXL_MODE_EX(640, 480),
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    QXL_MODE_EX(800, 480),
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    QXL_MODE_EX(800, 600),
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    QXL_MODE_EX(832, 624),
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    QXL_MODE_EX(960, 640),
86
    QXL_MODE_EX(1024, 600),
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    QXL_MODE_EX(1024, 768),
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    QXL_MODE_EX(1152, 864),
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    QXL_MODE_EX(1152, 870),
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    QXL_MODE_EX(1280, 720),
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    QXL_MODE_EX(1280, 760),
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    QXL_MODE_EX(1280, 768),
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    QXL_MODE_EX(1280, 800),
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    QXL_MODE_EX(1280, 960),
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    QXL_MODE_EX(1280, 1024),
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    QXL_MODE_EX(1360, 768),
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    QXL_MODE_EX(1366, 768),
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    QXL_MODE_EX(1400, 1050),
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    QXL_MODE_EX(1440, 900),
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    QXL_MODE_EX(1600, 900),
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    QXL_MODE_EX(1600, 1200),
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    QXL_MODE_EX(1680, 1050),
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    QXL_MODE_EX(1920, 1080),
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#if VGA_RAM_SIZE >= (16 * 1024 * 1024)
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    /* these modes need more than 8 MB video memory */
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    QXL_MODE_EX(1920, 1200),
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    QXL_MODE_EX(1920, 1440),
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    QXL_MODE_EX(2048, 1536),
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    QXL_MODE_EX(2560, 1440),
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    QXL_MODE_EX(2560, 1600),
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#endif
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#if VGA_RAM_SIZE >= (32 * 1024 * 1024)
113
    /* these modes need more than 16 MB video memory */
114
    QXL_MODE_EX(2560, 2048),
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    QXL_MODE_EX(2800, 2100),
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    QXL_MODE_EX(3200, 2400),
117
#endif
118
};
119

    
120
static PCIQXLDevice *qxl0;
121

    
122
static void qxl_send_events(PCIQXLDevice *d, uint32_t events);
123
static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async);
124
static void qxl_reset_memslots(PCIQXLDevice *d);
125
static void qxl_reset_surfaces(PCIQXLDevice *d);
126
static void qxl_ring_set_dirty(PCIQXLDevice *qxl);
127

    
128
void qxl_guest_bug(PCIQXLDevice *qxl, const char *msg, ...)
129
{
130
#if SPICE_INTERFACE_QXL_MINOR >= 1
131
    qxl_send_events(qxl, QXL_INTERRUPT_ERROR);
132
#endif
133
    if (qxl->guestdebug) {
134
        va_list ap;
135
        va_start(ap, msg);
136
        fprintf(stderr, "qxl-%d: guest bug: ", qxl->id);
137
        vfprintf(stderr, msg, ap);
138
        fprintf(stderr, "\n");
139
        va_end(ap);
140
    }
141
}
142

    
143

    
144
void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id,
145
                           struct QXLRect *area, struct QXLRect *dirty_rects,
146
                           uint32_t num_dirty_rects,
147
                           uint32_t clear_dirty_region,
148
                           qxl_async_io async)
149
{
150
    if (async == QXL_SYNC) {
151
        qxl->ssd.worker->update_area(qxl->ssd.worker, surface_id, area,
152
                        dirty_rects, num_dirty_rects, clear_dirty_region);
153
    } else {
154
#if SPICE_INTERFACE_QXL_MINOR >= 1
155
        spice_qxl_update_area_async(&qxl->ssd.qxl, surface_id, area,
156
                                    clear_dirty_region, 0);
157
#else
158
        abort();
159
#endif
160
    }
161
}
162

    
163
static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice *qxl,
164
                                                    uint32_t id)
165
{
166
    qemu_mutex_lock(&qxl->track_lock);
167
    qxl->guest_surfaces.cmds[id] = 0;
168
    qxl->guest_surfaces.count--;
169
    qemu_mutex_unlock(&qxl->track_lock);
170
}
171

    
172
static void qxl_spice_destroy_surface_wait(PCIQXLDevice *qxl, uint32_t id,
173
                                           qxl_async_io async)
174
{
175
    if (async) {
176
#if SPICE_INTERFACE_QXL_MINOR < 1
177
        abort();
178
#else
179
        spice_qxl_destroy_surface_async(&qxl->ssd.qxl, id,
180
                                        (uint64_t)id);
181
#endif
182
    } else {
183
        qxl->ssd.worker->destroy_surface_wait(qxl->ssd.worker, id);
184
        qxl_spice_destroy_surface_wait_complete(qxl, id);
185
    }
186
}
187

    
188
#if SPICE_INTERFACE_QXL_MINOR >= 1
189
static void qxl_spice_flush_surfaces_async(PCIQXLDevice *qxl)
190
{
191
    spice_qxl_flush_surfaces_async(&qxl->ssd.qxl, 0);
192
}
193
#endif
194

    
195
void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext,
196
                               uint32_t count)
197
{
198
    qxl->ssd.worker->loadvm_commands(qxl->ssd.worker, ext, count);
199
}
200

    
201
void qxl_spice_oom(PCIQXLDevice *qxl)
202
{
203
    qxl->ssd.worker->oom(qxl->ssd.worker);
204
}
205

    
206
void qxl_spice_reset_memslots(PCIQXLDevice *qxl)
207
{
208
    qxl->ssd.worker->reset_memslots(qxl->ssd.worker);
209
}
210

    
211
static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice *qxl)
212
{
213
    qemu_mutex_lock(&qxl->track_lock);
214
    memset(&qxl->guest_surfaces.cmds, 0, sizeof(qxl->guest_surfaces.cmds));
215
    qxl->guest_surfaces.count = 0;
216
    qemu_mutex_unlock(&qxl->track_lock);
217
}
218

    
219
static void qxl_spice_destroy_surfaces(PCIQXLDevice *qxl, qxl_async_io async)
220
{
221
    if (async) {
222
#if SPICE_INTERFACE_QXL_MINOR < 1
223
        abort();
224
#else
225
        spice_qxl_destroy_surfaces_async(&qxl->ssd.qxl, 0);
226
#endif
227
    } else {
228
        qxl->ssd.worker->destroy_surfaces(qxl->ssd.worker);
229
        qxl_spice_destroy_surfaces_complete(qxl);
230
    }
231
}
232

    
233
void qxl_spice_reset_image_cache(PCIQXLDevice *qxl)
234
{
235
    qxl->ssd.worker->reset_image_cache(qxl->ssd.worker);
236
}
237

    
238
void qxl_spice_reset_cursor(PCIQXLDevice *qxl)
239
{
240
    qxl->ssd.worker->reset_cursor(qxl->ssd.worker);
241
}
242

    
243

    
244
static inline uint32_t msb_mask(uint32_t val)
245
{
246
    uint32_t mask;
247

    
248
    do {
249
        mask = ~(val - 1) & val;
250
        val &= ~mask;
251
    } while (mask < val);
252

    
253
    return mask;
254
}
255

    
256
static ram_addr_t qxl_rom_size(void)
257
{
258
    uint32_t rom_size = sizeof(QXLRom) + sizeof(QXLModes) + sizeof(qxl_modes);
259
    rom_size = MAX(rom_size, TARGET_PAGE_SIZE);
260
    rom_size = msb_mask(rom_size * 2 - 1);
261
    return rom_size;
262
}
263

    
264
static void init_qxl_rom(PCIQXLDevice *d)
265
{
266
    QXLRom *rom = memory_region_get_ram_ptr(&d->rom_bar);
267
    QXLModes *modes = (QXLModes *)(rom + 1);
268
    uint32_t ram_header_size;
269
    uint32_t surface0_area_size;
270
    uint32_t num_pages;
271
    uint32_t fb, maxfb = 0;
272
    int i;
273

    
274
    memset(rom, 0, d->rom_size);
275

    
276
    rom->magic         = cpu_to_le32(QXL_ROM_MAGIC);
277
    rom->id            = cpu_to_le32(d->id);
278
    rom->log_level     = cpu_to_le32(d->guestdebug);
279
    rom->modes_offset  = cpu_to_le32(sizeof(QXLRom));
280

    
281
    rom->slot_gen_bits = MEMSLOT_GENERATION_BITS;
282
    rom->slot_id_bits  = MEMSLOT_SLOT_BITS;
283
    rom->slots_start   = 1;
284
    rom->slots_end     = NUM_MEMSLOTS - 1;
285
    rom->n_surfaces    = cpu_to_le32(NUM_SURFACES);
286

    
287
    modes->n_modes     = cpu_to_le32(ARRAY_SIZE(qxl_modes));
288
    for (i = 0; i < modes->n_modes; i++) {
289
        fb = qxl_modes[i].y_res * qxl_modes[i].stride;
290
        if (maxfb < fb) {
291
            maxfb = fb;
292
        }
293
        modes->modes[i].id          = cpu_to_le32(i);
294
        modes->modes[i].x_res       = cpu_to_le32(qxl_modes[i].x_res);
295
        modes->modes[i].y_res       = cpu_to_le32(qxl_modes[i].y_res);
296
        modes->modes[i].bits        = cpu_to_le32(qxl_modes[i].bits);
297
        modes->modes[i].stride      = cpu_to_le32(qxl_modes[i].stride);
298
        modes->modes[i].x_mili      = cpu_to_le32(qxl_modes[i].x_mili);
299
        modes->modes[i].y_mili      = cpu_to_le32(qxl_modes[i].y_mili);
300
        modes->modes[i].orientation = cpu_to_le32(qxl_modes[i].orientation);
301
    }
302
    if (maxfb < VGA_RAM_SIZE && d->id == 0)
303
        maxfb = VGA_RAM_SIZE;
304

    
305
    ram_header_size    = ALIGN(sizeof(QXLRam), 4096);
306
    surface0_area_size = ALIGN(maxfb, 4096);
307
    num_pages          = d->vga.vram_size;
308
    num_pages         -= ram_header_size;
309
    num_pages         -= surface0_area_size;
310
    num_pages          = num_pages / TARGET_PAGE_SIZE;
311

    
312
    rom->draw_area_offset   = cpu_to_le32(0);
313
    rom->surface0_area_size = cpu_to_le32(surface0_area_size);
314
    rom->pages_offset       = cpu_to_le32(surface0_area_size);
315
    rom->num_pages          = cpu_to_le32(num_pages);
316
    rom->ram_header_offset  = cpu_to_le32(d->vga.vram_size - ram_header_size);
317

    
318
    d->shadow_rom = *rom;
319
    d->rom        = rom;
320
    d->modes      = modes;
321
}
322

    
323
static void init_qxl_ram(PCIQXLDevice *d)
324
{
325
    uint8_t *buf;
326
    uint64_t *item;
327

    
328
    buf = d->vga.vram_ptr;
329
    d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset));
330
    d->ram->magic       = cpu_to_le32(QXL_RAM_MAGIC);
331
    d->ram->int_pending = cpu_to_le32(0);
332
    d->ram->int_mask    = cpu_to_le32(0);
333
    SPICE_RING_INIT(&d->ram->cmd_ring);
334
    SPICE_RING_INIT(&d->ram->cursor_ring);
335
    SPICE_RING_INIT(&d->ram->release_ring);
336
    SPICE_RING_PROD_ITEM(&d->ram->release_ring, item);
337
    *item = 0;
338
    qxl_ring_set_dirty(d);
339
}
340

    
341
/* can be called from spice server thread context */
342
static void qxl_set_dirty(MemoryRegion *mr, ram_addr_t addr, ram_addr_t end)
343
{
344
    while (addr < end) {
345
        memory_region_set_dirty(mr, addr);
346
        addr += TARGET_PAGE_SIZE;
347
    }
348
}
349

    
350
static void qxl_rom_set_dirty(PCIQXLDevice *qxl)
351
{
352
    qxl_set_dirty(&qxl->rom_bar, 0, qxl->rom_size);
353
}
354

    
355
/* called from spice server thread context only */
356
static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr)
357
{
358
    void *base = qxl->vga.vram_ptr;
359
    intptr_t offset;
360

    
361
    offset = ptr - base;
362
    offset &= ~(TARGET_PAGE_SIZE-1);
363
    assert(offset < qxl->vga.vram_size);
364
    qxl_set_dirty(&qxl->vga.vram, offset, offset + TARGET_PAGE_SIZE);
365
}
366

    
367
/* can be called from spice server thread context */
368
static void qxl_ring_set_dirty(PCIQXLDevice *qxl)
369
{
370
    ram_addr_t addr = qxl->shadow_rom.ram_header_offset;
371
    ram_addr_t end  = qxl->vga.vram_size;
372
    qxl_set_dirty(&qxl->vga.vram, addr, end);
373
}
374

    
375
/*
376
 * keep track of some command state, for savevm/loadvm.
377
 * called from spice server thread context only
378
 */
379
static void qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext)
380
{
381
    switch (le32_to_cpu(ext->cmd.type)) {
382
    case QXL_CMD_SURFACE:
383
    {
384
        QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
385
        uint32_t id = le32_to_cpu(cmd->surface_id);
386
        PANIC_ON(id >= NUM_SURFACES);
387
        qemu_mutex_lock(&qxl->track_lock);
388
        if (cmd->type == QXL_SURFACE_CMD_CREATE) {
389
            qxl->guest_surfaces.cmds[id] = ext->cmd.data;
390
            qxl->guest_surfaces.count++;
391
            if (qxl->guest_surfaces.max < qxl->guest_surfaces.count)
392
                qxl->guest_surfaces.max = qxl->guest_surfaces.count;
393
        }
394
        if (cmd->type == QXL_SURFACE_CMD_DESTROY) {
395
            qxl->guest_surfaces.cmds[id] = 0;
396
            qxl->guest_surfaces.count--;
397
        }
398
        qemu_mutex_unlock(&qxl->track_lock);
399
        break;
400
    }
401
    case QXL_CMD_CURSOR:
402
    {
403
        QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
404
        if (cmd->type == QXL_CURSOR_SET) {
405
            qxl->guest_cursor = ext->cmd.data;
406
        }
407
        break;
408
    }
409
    }
410
}
411

    
412
/* spice display interface callbacks */
413

    
414
static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker)
415
{
416
    PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
417

    
418
    dprint(qxl, 1, "%s:\n", __FUNCTION__);
419
    qxl->ssd.worker = qxl_worker;
420
}
421

    
422
static void interface_set_compression_level(QXLInstance *sin, int level)
423
{
424
    PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
425

    
426
    dprint(qxl, 1, "%s: %d\n", __FUNCTION__, level);
427
    qxl->shadow_rom.compression_level = cpu_to_le32(level);
428
    qxl->rom->compression_level = cpu_to_le32(level);
429
    qxl_rom_set_dirty(qxl);
430
}
431

    
432
static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time)
433
{
434
    PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
435

    
436
    qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time);
437
    qxl->rom->mm_clock = cpu_to_le32(mm_time);
438
    qxl_rom_set_dirty(qxl);
439
}
440

    
441
static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info)
442
{
443
    PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
444

    
445
    dprint(qxl, 1, "%s:\n", __FUNCTION__);
446
    info->memslot_gen_bits = MEMSLOT_GENERATION_BITS;
447
    info->memslot_id_bits = MEMSLOT_SLOT_BITS;
448
    info->num_memslots = NUM_MEMSLOTS;
449
    info->num_memslots_groups = NUM_MEMSLOTS_GROUPS;
450
    info->internal_groupslot_id = 0;
451
    info->qxl_ram_size = le32_to_cpu(qxl->shadow_rom.num_pages) << TARGET_PAGE_BITS;
452
    info->n_surfaces = NUM_SURFACES;
453
}
454

    
455
static const char *qxl_mode_to_string(int mode)
456
{
457
    switch (mode) {
458
    case QXL_MODE_COMPAT:
459
        return "compat";
460
    case QXL_MODE_NATIVE:
461
        return "native";
462
    case QXL_MODE_UNDEFINED:
463
        return "undefined";
464
    case QXL_MODE_VGA:
465
        return "vga";
466
    }
467
    return "INVALID";
468
}
469

    
470
static const char *io_port_to_string(uint32_t io_port)
471
{
472
    if (io_port >= QXL_IO_RANGE_SIZE) {
473
        return "out of range";
474
    }
475
    static const char *io_port_to_string[QXL_IO_RANGE_SIZE + 1] = {
476
        [QXL_IO_NOTIFY_CMD]             = "QXL_IO_NOTIFY_CMD",
477
        [QXL_IO_NOTIFY_CURSOR]          = "QXL_IO_NOTIFY_CURSOR",
478
        [QXL_IO_UPDATE_AREA]            = "QXL_IO_UPDATE_AREA",
479
        [QXL_IO_UPDATE_IRQ]             = "QXL_IO_UPDATE_IRQ",
480
        [QXL_IO_NOTIFY_OOM]             = "QXL_IO_NOTIFY_OOM",
481
        [QXL_IO_RESET]                  = "QXL_IO_RESET",
482
        [QXL_IO_SET_MODE]               = "QXL_IO_SET_MODE",
483
        [QXL_IO_LOG]                    = "QXL_IO_LOG",
484
        [QXL_IO_MEMSLOT_ADD]            = "QXL_IO_MEMSLOT_ADD",
485
        [QXL_IO_MEMSLOT_DEL]            = "QXL_IO_MEMSLOT_DEL",
486
        [QXL_IO_DETACH_PRIMARY]         = "QXL_IO_DETACH_PRIMARY",
487
        [QXL_IO_ATTACH_PRIMARY]         = "QXL_IO_ATTACH_PRIMARY",
488
        [QXL_IO_CREATE_PRIMARY]         = "QXL_IO_CREATE_PRIMARY",
489
        [QXL_IO_DESTROY_PRIMARY]        = "QXL_IO_DESTROY_PRIMARY",
490
        [QXL_IO_DESTROY_SURFACE_WAIT]   = "QXL_IO_DESTROY_SURFACE_WAIT",
491
        [QXL_IO_DESTROY_ALL_SURFACES]   = "QXL_IO_DESTROY_ALL_SURFACES",
492
#if SPICE_INTERFACE_QXL_MINOR >= 1
493
        [QXL_IO_UPDATE_AREA_ASYNC]      = "QXL_IO_UPDATE_AREA_ASYNC",
494
        [QXL_IO_MEMSLOT_ADD_ASYNC]      = "QXL_IO_MEMSLOT_ADD_ASYNC",
495
        [QXL_IO_CREATE_PRIMARY_ASYNC]   = "QXL_IO_CREATE_PRIMARY_ASYNC",
496
        [QXL_IO_DESTROY_PRIMARY_ASYNC]  = "QXL_IO_DESTROY_PRIMARY_ASYNC",
497
        [QXL_IO_DESTROY_SURFACE_ASYNC]  = "QXL_IO_DESTROY_SURFACE_ASYNC",
498
        [QXL_IO_DESTROY_ALL_SURFACES_ASYNC]
499
                                        = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC",
500
        [QXL_IO_FLUSH_SURFACES_ASYNC]   = "QXL_IO_FLUSH_SURFACES_ASYNC",
501
        [QXL_IO_FLUSH_RELEASE]          = "QXL_IO_FLUSH_RELEASE",
502
#endif
503
    };
504
    return io_port_to_string[io_port];
505
}
506

    
507
/* called from spice server thread context only */
508
static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext)
509
{
510
    PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
511
    SimpleSpiceUpdate *update;
512
    QXLCommandRing *ring;
513
    QXLCommand *cmd;
514
    int notify, ret;
515

    
516
    switch (qxl->mode) {
517
    case QXL_MODE_VGA:
518
        dprint(qxl, 2, "%s: vga\n", __FUNCTION__);
519
        ret = false;
520
        qemu_mutex_lock(&qxl->ssd.lock);
521
        if (qxl->ssd.update != NULL) {
522
            update = qxl->ssd.update;
523
            qxl->ssd.update = NULL;
524
            *ext = update->ext;
525
            ret = true;
526
        }
527
        qemu_mutex_unlock(&qxl->ssd.lock);
528
        if (ret) {
529
            dprint(qxl, 2, "%s %s\n", __FUNCTION__, qxl_mode_to_string(qxl->mode));
530
            qxl_log_command(qxl, "vga", ext);
531
        }
532
        return ret;
533
    case QXL_MODE_COMPAT:
534
    case QXL_MODE_NATIVE:
535
    case QXL_MODE_UNDEFINED:
536
        dprint(qxl, 4, "%s: %s\n", __FUNCTION__, qxl_mode_to_string(qxl->mode));
537
        ring = &qxl->ram->cmd_ring;
538
        if (SPICE_RING_IS_EMPTY(ring)) {
539
            return false;
540
        }
541
        dprint(qxl, 2, "%s: %s\n", __FUNCTION__, qxl_mode_to_string(qxl->mode));
542
        SPICE_RING_CONS_ITEM(ring, cmd);
543
        ext->cmd      = *cmd;
544
        ext->group_id = MEMSLOT_GROUP_GUEST;
545
        ext->flags    = qxl->cmdflags;
546
        SPICE_RING_POP(ring, notify);
547
        qxl_ring_set_dirty(qxl);
548
        if (notify) {
549
            qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY);
550
        }
551
        qxl->guest_primary.commands++;
552
        qxl_track_command(qxl, ext);
553
        qxl_log_command(qxl, "cmd", ext);
554
        return true;
555
    default:
556
        return false;
557
    }
558
}
559

    
560
/* called from spice server thread context only */
561
static int interface_req_cmd_notification(QXLInstance *sin)
562
{
563
    PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
564
    int wait = 1;
565

    
566
    switch (qxl->mode) {
567
    case QXL_MODE_COMPAT:
568
    case QXL_MODE_NATIVE:
569
    case QXL_MODE_UNDEFINED:
570
        SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait);
571
        qxl_ring_set_dirty(qxl);
572
        break;
573
    default:
574
        /* nothing */
575
        break;
576
    }
577
    return wait;
578
}
579

    
580
/* called from spice server thread context only */
581
static inline void qxl_push_free_res(PCIQXLDevice *d, int flush)
582
{
583
    QXLReleaseRing *ring = &d->ram->release_ring;
584
    uint64_t *item;
585
    int notify;
586

    
587
#define QXL_FREE_BUNCH_SIZE 32
588

    
589
    if (ring->prod - ring->cons + 1 == ring->num_items) {
590
        /* ring full -- can't push */
591
        return;
592
    }
593
    if (!flush && d->oom_running) {
594
        /* collect everything from oom handler before pushing */
595
        return;
596
    }
597
    if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) {
598
        /* collect a bit more before pushing */
599
        return;
600
    }
601

    
602
    SPICE_RING_PUSH(ring, notify);
603
    dprint(d, 2, "free: push %d items, notify %s, ring %d/%d [%d,%d]\n",
604
           d->num_free_res, notify ? "yes" : "no",
605
           ring->prod - ring->cons, ring->num_items,
606
           ring->prod, ring->cons);
607
    if (notify) {
608
        qxl_send_events(d, QXL_INTERRUPT_DISPLAY);
609
    }
610
    SPICE_RING_PROD_ITEM(ring, item);
611
    *item = 0;
612
    d->num_free_res = 0;
613
    d->last_release = NULL;
614
    qxl_ring_set_dirty(d);
615
}
616

    
617
/* called from spice server thread context only */
618
static void interface_release_resource(QXLInstance *sin,
619
                                       struct QXLReleaseInfoExt ext)
620
{
621
    PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
622
    QXLReleaseRing *ring;
623
    uint64_t *item, id;
624

    
625
    if (ext.group_id == MEMSLOT_GROUP_HOST) {
626
        /* host group -> vga mode update request */
627
        qemu_spice_destroy_update(&qxl->ssd, (void*)ext.info->id);
628
        return;
629
    }
630

    
631
    /*
632
     * ext->info points into guest-visible memory
633
     * pci bar 0, $command.release_info
634
     */
635
    ring = &qxl->ram->release_ring;
636
    SPICE_RING_PROD_ITEM(ring, item);
637
    if (*item == 0) {
638
        /* stick head into the ring */
639
        id = ext.info->id;
640
        ext.info->next = 0;
641
        qxl_ram_set_dirty(qxl, &ext.info->next);
642
        *item = id;
643
        qxl_ring_set_dirty(qxl);
644
    } else {
645
        /* append item to the list */
646
        qxl->last_release->next = ext.info->id;
647
        qxl_ram_set_dirty(qxl, &qxl->last_release->next);
648
        ext.info->next = 0;
649
        qxl_ram_set_dirty(qxl, &ext.info->next);
650
    }
651
    qxl->last_release = ext.info;
652
    qxl->num_free_res++;
653
    dprint(qxl, 3, "%4d\r", qxl->num_free_res);
654
    qxl_push_free_res(qxl, 0);
655
}
656

    
657
/* called from spice server thread context only */
658
static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext)
659
{
660
    PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
661
    QXLCursorRing *ring;
662
    QXLCommand *cmd;
663
    int notify;
664

    
665
    switch (qxl->mode) {
666
    case QXL_MODE_COMPAT:
667
    case QXL_MODE_NATIVE:
668
    case QXL_MODE_UNDEFINED:
669
        ring = &qxl->ram->cursor_ring;
670
        if (SPICE_RING_IS_EMPTY(ring)) {
671
            return false;
672
        }
673
        SPICE_RING_CONS_ITEM(ring, cmd);
674
        ext->cmd      = *cmd;
675
        ext->group_id = MEMSLOT_GROUP_GUEST;
676
        ext->flags    = qxl->cmdflags;
677
        SPICE_RING_POP(ring, notify);
678
        qxl_ring_set_dirty(qxl);
679
        if (notify) {
680
            qxl_send_events(qxl, QXL_INTERRUPT_CURSOR);
681
        }
682
        qxl->guest_primary.commands++;
683
        qxl_track_command(qxl, ext);
684
        qxl_log_command(qxl, "csr", ext);
685
        if (qxl->id == 0) {
686
            qxl_render_cursor(qxl, ext);
687
        }
688
        return true;
689
    default:
690
        return false;
691
    }
692
}
693

    
694
/* called from spice server thread context only */
695
static int interface_req_cursor_notification(QXLInstance *sin)
696
{
697
    PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
698
    int wait = 1;
699

    
700
    switch (qxl->mode) {
701
    case QXL_MODE_COMPAT:
702
    case QXL_MODE_NATIVE:
703
    case QXL_MODE_UNDEFINED:
704
        SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait);
705
        qxl_ring_set_dirty(qxl);
706
        break;
707
    default:
708
        /* nothing */
709
        break;
710
    }
711
    return wait;
712
}
713

    
714
/* called from spice server thread context */
715
static void interface_notify_update(QXLInstance *sin, uint32_t update_id)
716
{
717
    fprintf(stderr, "%s: abort()\n", __FUNCTION__);
718
    abort();
719
}
720

    
721
/* called from spice server thread context only */
722
static int interface_flush_resources(QXLInstance *sin)
723
{
724
    PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
725
    int ret;
726

    
727
    dprint(qxl, 1, "free: guest flush (have %d)\n", qxl->num_free_res);
728
    ret = qxl->num_free_res;
729
    if (ret) {
730
        qxl_push_free_res(qxl, 1);
731
    }
732
    return ret;
733
}
734

    
735
static void qxl_create_guest_primary_complete(PCIQXLDevice *d);
736

    
737
#if SPICE_INTERFACE_QXL_MINOR >= 1
738

    
739
/* called from spice server thread context only */
740
static void interface_async_complete(QXLInstance *sin, uint64_t cookie)
741
{
742
    PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
743
    uint32_t current_async;
744

    
745
    qemu_mutex_lock(&qxl->async_lock);
746
    current_async = qxl->current_async;
747
    qxl->current_async = QXL_UNDEFINED_IO;
748
    qemu_mutex_unlock(&qxl->async_lock);
749

    
750
    dprint(qxl, 2, "async_complete: %d (%ld) done\n", current_async, cookie);
751
    switch (current_async) {
752
    case QXL_IO_CREATE_PRIMARY_ASYNC:
753
        qxl_create_guest_primary_complete(qxl);
754
        break;
755
    case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
756
        qxl_spice_destroy_surfaces_complete(qxl);
757
        break;
758
    case QXL_IO_DESTROY_SURFACE_ASYNC:
759
        qxl_spice_destroy_surface_wait_complete(qxl, (uint32_t)cookie);
760
        break;
761
    }
762
    qxl_send_events(qxl, QXL_INTERRUPT_IO_CMD);
763
}
764

    
765
#endif
766

    
767
static const QXLInterface qxl_interface = {
768
    .base.type               = SPICE_INTERFACE_QXL,
769
    .base.description        = "qxl gpu",
770
    .base.major_version      = SPICE_INTERFACE_QXL_MAJOR,
771
    .base.minor_version      = SPICE_INTERFACE_QXL_MINOR,
772

    
773
    .attache_worker          = interface_attach_worker,
774
    .set_compression_level   = interface_set_compression_level,
775
    .set_mm_time             = interface_set_mm_time,
776
    .get_init_info           = interface_get_init_info,
777

    
778
    /* the callbacks below are called from spice server thread context */
779
    .get_command             = interface_get_command,
780
    .req_cmd_notification    = interface_req_cmd_notification,
781
    .release_resource        = interface_release_resource,
782
    .get_cursor_command      = interface_get_cursor_command,
783
    .req_cursor_notification = interface_req_cursor_notification,
784
    .notify_update           = interface_notify_update,
785
    .flush_resources         = interface_flush_resources,
786
#if SPICE_INTERFACE_QXL_MINOR >= 1
787
    .async_complete          = interface_async_complete,
788
#endif
789
};
790

    
791
static void qxl_enter_vga_mode(PCIQXLDevice *d)
792
{
793
    if (d->mode == QXL_MODE_VGA) {
794
        return;
795
    }
796
    dprint(d, 1, "%s\n", __FUNCTION__);
797
    qemu_spice_create_host_primary(&d->ssd);
798
    d->mode = QXL_MODE_VGA;
799
    memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
800
}
801

    
802
static void qxl_exit_vga_mode(PCIQXLDevice *d)
803
{
804
    if (d->mode != QXL_MODE_VGA) {
805
        return;
806
    }
807
    dprint(d, 1, "%s\n", __FUNCTION__);
808
    qxl_destroy_primary(d, QXL_SYNC);
809
}
810

    
811
static void qxl_set_irq(PCIQXLDevice *d)
812
{
813
    uint32_t pending = le32_to_cpu(d->ram->int_pending);
814
    uint32_t mask    = le32_to_cpu(d->ram->int_mask);
815
    int level = !!(pending & mask);
816
    qemu_set_irq(d->pci.irq[0], level);
817
    qxl_ring_set_dirty(d);
818
}
819

    
820
static void qxl_check_state(PCIQXLDevice *d)
821
{
822
    QXLRam *ram = d->ram;
823

    
824
    assert(!d->ssd.running || SPICE_RING_IS_EMPTY(&ram->cmd_ring));
825
    assert(!d->ssd.running || SPICE_RING_IS_EMPTY(&ram->cursor_ring));
826
}
827

    
828
static void qxl_reset_state(PCIQXLDevice *d)
829
{
830
    QXLRom *rom = d->rom;
831

    
832
    qxl_check_state(d);
833
    d->shadow_rom.update_id = cpu_to_le32(0);
834
    *rom = d->shadow_rom;
835
    qxl_rom_set_dirty(d);
836
    init_qxl_ram(d);
837
    d->num_free_res = 0;
838
    d->last_release = NULL;
839
    memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
840
}
841

    
842
static void qxl_soft_reset(PCIQXLDevice *d)
843
{
844
    dprint(d, 1, "%s:\n", __FUNCTION__);
845
    qxl_check_state(d);
846

    
847
    if (d->id == 0) {
848
        qxl_enter_vga_mode(d);
849
    } else {
850
        d->mode = QXL_MODE_UNDEFINED;
851
    }
852
}
853

    
854
static void qxl_hard_reset(PCIQXLDevice *d, int loadvm)
855
{
856
    dprint(d, 1, "%s: start%s\n", __FUNCTION__,
857
           loadvm ? " (loadvm)" : "");
858

    
859
    qxl_spice_reset_cursor(d);
860
    qxl_spice_reset_image_cache(d);
861
    qxl_reset_surfaces(d);
862
    qxl_reset_memslots(d);
863

    
864
    /* pre loadvm reset must not touch QXLRam.  This lives in
865
     * device memory, is migrated together with RAM and thus
866
     * already loaded at this point */
867
    if (!loadvm) {
868
        qxl_reset_state(d);
869
    }
870
    qemu_spice_create_host_memslot(&d->ssd);
871
    qxl_soft_reset(d);
872

    
873
    dprint(d, 1, "%s: done\n", __FUNCTION__);
874
}
875

    
876
static void qxl_reset_handler(DeviceState *dev)
877
{
878
    PCIQXLDevice *d = DO_UPCAST(PCIQXLDevice, pci.qdev, dev);
879
    qxl_hard_reset(d, 0);
880
}
881

    
882
static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
883
{
884
    VGACommonState *vga = opaque;
885
    PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga);
886

    
887
    if (qxl->mode != QXL_MODE_VGA) {
888
        dprint(qxl, 1, "%s\n", __FUNCTION__);
889
        qxl_destroy_primary(qxl, QXL_SYNC);
890
        qxl_soft_reset(qxl);
891
    }
892
    vga_ioport_write(opaque, addr, val);
893
}
894

    
895
static void qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta,
896
                            qxl_async_io async)
897
{
898
    static const int regions[] = {
899
        QXL_RAM_RANGE_INDEX,
900
        QXL_VRAM_RANGE_INDEX,
901
    };
902
    uint64_t guest_start;
903
    uint64_t guest_end;
904
    int pci_region;
905
    pcibus_t pci_start;
906
    pcibus_t pci_end;
907
    intptr_t virt_start;
908
    QXLDevMemSlot memslot;
909
    int i;
910

    
911
    guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start);
912
    guest_end   = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end);
913

    
914
    dprint(d, 1, "%s: slot %d: guest phys 0x%" PRIx64 " - 0x%" PRIx64 "\n",
915
           __FUNCTION__, slot_id,
916
           guest_start, guest_end);
917

    
918
    PANIC_ON(slot_id >= NUM_MEMSLOTS);
919
    PANIC_ON(guest_start > guest_end);
920

    
921
    for (i = 0; i < ARRAY_SIZE(regions); i++) {
922
        pci_region = regions[i];
923
        pci_start = d->pci.io_regions[pci_region].addr;
924
        pci_end = pci_start + d->pci.io_regions[pci_region].size;
925
        /* mapped? */
926
        if (pci_start == -1) {
927
            continue;
928
        }
929
        /* start address in range ? */
930
        if (guest_start < pci_start || guest_start > pci_end) {
931
            continue;
932
        }
933
        /* end address in range ? */
934
        if (guest_end > pci_end) {
935
            continue;
936
        }
937
        /* passed */
938
        break;
939
    }
940
    PANIC_ON(i == ARRAY_SIZE(regions)); /* finished loop without match */
941

    
942
    switch (pci_region) {
943
    case QXL_RAM_RANGE_INDEX:
944
        virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vga.vram);
945
        break;
946
    case QXL_VRAM_RANGE_INDEX:
947
        virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vram_bar);
948
        break;
949
    default:
950
        /* should not happen */
951
        abort();
952
    }
953

    
954
    memslot.slot_id = slot_id;
955
    memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */
956
    memslot.virt_start = virt_start + (guest_start - pci_start);
957
    memslot.virt_end   = virt_start + (guest_end   - pci_start);
958
    memslot.addr_delta = memslot.virt_start - delta;
959
    memslot.generation = d->rom->slot_generation = 0;
960
    qxl_rom_set_dirty(d);
961

    
962
    dprint(d, 1, "%s: slot %d: host virt 0x%" PRIx64 " - 0x%" PRIx64 "\n",
963
           __FUNCTION__, memslot.slot_id,
964
           memslot.virt_start, memslot.virt_end);
965

    
966
    qemu_spice_add_memslot(&d->ssd, &memslot, async);
967
    d->guest_slots[slot_id].ptr = (void*)memslot.virt_start;
968
    d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start;
969
    d->guest_slots[slot_id].delta = delta;
970
    d->guest_slots[slot_id].active = 1;
971
}
972

    
973
static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id)
974
{
975
    dprint(d, 1, "%s: slot %d\n", __FUNCTION__, slot_id);
976
    qemu_spice_del_memslot(&d->ssd, MEMSLOT_GROUP_HOST, slot_id);
977
    d->guest_slots[slot_id].active = 0;
978
}
979

    
980
static void qxl_reset_memslots(PCIQXLDevice *d)
981
{
982
    dprint(d, 1, "%s:\n", __FUNCTION__);
983
    qxl_spice_reset_memslots(d);
984
    memset(&d->guest_slots, 0, sizeof(d->guest_slots));
985
}
986

    
987
static void qxl_reset_surfaces(PCIQXLDevice *d)
988
{
989
    dprint(d, 1, "%s:\n", __FUNCTION__);
990
    d->mode = QXL_MODE_UNDEFINED;
991
    qxl_spice_destroy_surfaces(d, QXL_SYNC);
992
}
993

    
994
/* called from spice server thread context only */
995
void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id)
996
{
997
    uint64_t phys   = le64_to_cpu(pqxl);
998
    uint32_t slot   = (phys >> (64 -  8)) & 0xff;
999
    uint64_t offset = phys & 0xffffffffffff;
1000

    
1001
    switch (group_id) {
1002
    case MEMSLOT_GROUP_HOST:
1003
        return (void*)offset;
1004
    case MEMSLOT_GROUP_GUEST:
1005
        PANIC_ON(slot > NUM_MEMSLOTS);
1006
        PANIC_ON(!qxl->guest_slots[slot].active);
1007
        PANIC_ON(offset < qxl->guest_slots[slot].delta);
1008
        offset -= qxl->guest_slots[slot].delta;
1009
        PANIC_ON(offset > qxl->guest_slots[slot].size)
1010
        return qxl->guest_slots[slot].ptr + offset;
1011
    default:
1012
        PANIC_ON(1);
1013
    }
1014
}
1015

    
1016
static void qxl_create_guest_primary_complete(PCIQXLDevice *qxl)
1017
{
1018
    /* for local rendering */
1019
    qxl_render_resize(qxl);
1020
}
1021

    
1022
static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm,
1023
                                     qxl_async_io async)
1024
{
1025
    QXLDevSurfaceCreate surface;
1026
    QXLSurfaceCreate *sc = &qxl->guest_primary.surface;
1027

    
1028
    assert(qxl->mode != QXL_MODE_NATIVE);
1029
    qxl_exit_vga_mode(qxl);
1030

    
1031
    dprint(qxl, 1, "%s: %dx%d\n", __FUNCTION__,
1032
           le32_to_cpu(sc->width), le32_to_cpu(sc->height));
1033

    
1034
    surface.format     = le32_to_cpu(sc->format);
1035
    surface.height     = le32_to_cpu(sc->height);
1036
    surface.mem        = le64_to_cpu(sc->mem);
1037
    surface.position   = le32_to_cpu(sc->position);
1038
    surface.stride     = le32_to_cpu(sc->stride);
1039
    surface.width      = le32_to_cpu(sc->width);
1040
    surface.type       = le32_to_cpu(sc->type);
1041
    surface.flags      = le32_to_cpu(sc->flags);
1042

    
1043
    surface.mouse_mode = true;
1044
    surface.group_id   = MEMSLOT_GROUP_GUEST;
1045
    if (loadvm) {
1046
        surface.flags |= QXL_SURF_FLAG_KEEP_DATA;
1047
    }
1048

    
1049
    qxl->mode = QXL_MODE_NATIVE;
1050
    qxl->cmdflags = 0;
1051
    qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface, async);
1052

    
1053
    if (async == QXL_SYNC) {
1054
        qxl_create_guest_primary_complete(qxl);
1055
    }
1056
}
1057

    
1058
/* return 1 if surface destoy was initiated (in QXL_ASYNC case) or
1059
 * done (in QXL_SYNC case), 0 otherwise. */
1060
static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async)
1061
{
1062
    if (d->mode == QXL_MODE_UNDEFINED) {
1063
        return 0;
1064
    }
1065

    
1066
    dprint(d, 1, "%s\n", __FUNCTION__);
1067

    
1068
    d->mode = QXL_MODE_UNDEFINED;
1069
    qemu_spice_destroy_primary_surface(&d->ssd, 0, async);
1070
    return 1;
1071
}
1072

    
1073
static void qxl_set_mode(PCIQXLDevice *d, int modenr, int loadvm)
1074
{
1075
    pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1076
    pcibus_t end   = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start;
1077
    QXLMode *mode = d->modes->modes + modenr;
1078
    uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1079
    QXLMemSlot slot = {
1080
        .mem_start = start,
1081
        .mem_end = end
1082
    };
1083
    QXLSurfaceCreate surface = {
1084
        .width      = mode->x_res,
1085
        .height     = mode->y_res,
1086
        .stride     = -mode->x_res * 4,
1087
        .format     = SPICE_SURFACE_FMT_32_xRGB,
1088
        .flags      = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0,
1089
        .mouse_mode = true,
1090
        .mem        = devmem + d->shadow_rom.draw_area_offset,
1091
    };
1092

    
1093
    dprint(d, 1, "%s: mode %d  [ %d x %d @ %d bpp devmem 0x%lx ]\n", __FUNCTION__,
1094
           modenr, mode->x_res, mode->y_res, mode->bits, devmem);
1095
    if (!loadvm) {
1096
        qxl_hard_reset(d, 0);
1097
    }
1098

    
1099
    d->guest_slots[0].slot = slot;
1100
    qxl_add_memslot(d, 0, devmem, QXL_SYNC);
1101

    
1102
    d->guest_primary.surface = surface;
1103
    qxl_create_guest_primary(d, 0, QXL_SYNC);
1104

    
1105
    d->mode = QXL_MODE_COMPAT;
1106
    d->cmdflags = QXL_COMMAND_FLAG_COMPAT;
1107
#ifdef QXL_COMMAND_FLAG_COMPAT_16BPP /* new in spice 0.6.1 */
1108
    if (mode->bits == 16) {
1109
        d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP;
1110
    }
1111
#endif
1112
    d->shadow_rom.mode = cpu_to_le32(modenr);
1113
    d->rom->mode = cpu_to_le32(modenr);
1114
    qxl_rom_set_dirty(d);
1115
}
1116

    
1117
static void ioport_write(void *opaque, target_phys_addr_t addr,
1118
                         uint64_t val, unsigned size)
1119
{
1120
    PCIQXLDevice *d = opaque;
1121
    uint32_t io_port = addr;
1122
    qxl_async_io async = QXL_SYNC;
1123
#if SPICE_INTERFACE_QXL_MINOR >= 1
1124
    uint32_t orig_io_port = io_port;
1125
#endif
1126

    
1127
    switch (io_port) {
1128
    case QXL_IO_RESET:
1129
    case QXL_IO_SET_MODE:
1130
    case QXL_IO_MEMSLOT_ADD:
1131
    case QXL_IO_MEMSLOT_DEL:
1132
    case QXL_IO_CREATE_PRIMARY:
1133
    case QXL_IO_UPDATE_IRQ:
1134
    case QXL_IO_LOG:
1135
#if SPICE_INTERFACE_QXL_MINOR >= 1
1136
    case QXL_IO_MEMSLOT_ADD_ASYNC:
1137
    case QXL_IO_CREATE_PRIMARY_ASYNC:
1138
#endif
1139
        break;
1140
    default:
1141
        if (d->mode != QXL_MODE_VGA) {
1142
            break;
1143
        }
1144
        dprint(d, 1, "%s: unexpected port 0x%x (%s) in vga mode\n",
1145
            __func__, io_port, io_port_to_string(io_port));
1146
#if SPICE_INTERFACE_QXL_MINOR >= 1
1147
        /* be nice to buggy guest drivers */
1148
        if (io_port >= QXL_IO_UPDATE_AREA_ASYNC &&
1149
            io_port <= QXL_IO_DESTROY_ALL_SURFACES_ASYNC) {
1150
            qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1151
        }
1152
#endif
1153
        return;
1154
    }
1155

    
1156
#if SPICE_INTERFACE_QXL_MINOR >= 1
1157
    /* we change the io_port to avoid ifdeffery in the main switch */
1158
    orig_io_port = io_port;
1159
    switch (io_port) {
1160
    case QXL_IO_UPDATE_AREA_ASYNC:
1161
        io_port = QXL_IO_UPDATE_AREA;
1162
        goto async_common;
1163
    case QXL_IO_MEMSLOT_ADD_ASYNC:
1164
        io_port = QXL_IO_MEMSLOT_ADD;
1165
        goto async_common;
1166
    case QXL_IO_CREATE_PRIMARY_ASYNC:
1167
        io_port = QXL_IO_CREATE_PRIMARY;
1168
        goto async_common;
1169
    case QXL_IO_DESTROY_PRIMARY_ASYNC:
1170
        io_port = QXL_IO_DESTROY_PRIMARY;
1171
        goto async_common;
1172
    case QXL_IO_DESTROY_SURFACE_ASYNC:
1173
        io_port = QXL_IO_DESTROY_SURFACE_WAIT;
1174
        goto async_common;
1175
    case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
1176
        io_port = QXL_IO_DESTROY_ALL_SURFACES;
1177
        goto async_common;
1178
    case QXL_IO_FLUSH_SURFACES_ASYNC:
1179
async_common:
1180
        async = QXL_ASYNC;
1181
        qemu_mutex_lock(&d->async_lock);
1182
        if (d->current_async != QXL_UNDEFINED_IO) {
1183
            qxl_guest_bug(d, "%d async started before last (%d) complete",
1184
                io_port, d->current_async);
1185
            qemu_mutex_unlock(&d->async_lock);
1186
            return;
1187
        }
1188
        d->current_async = orig_io_port;
1189
        qemu_mutex_unlock(&d->async_lock);
1190
        dprint(d, 2, "start async %d (%"PRId64")\n", io_port, val);
1191
        break;
1192
    default:
1193
        break;
1194
    }
1195
#endif
1196

    
1197
    switch (io_port) {
1198
    case QXL_IO_UPDATE_AREA:
1199
    {
1200
        QXLRect update = d->ram->update_area;
1201
        qxl_spice_update_area(d, d->ram->update_surface,
1202
                              &update, NULL, 0, 0, async);
1203
        break;
1204
    }
1205
    case QXL_IO_NOTIFY_CMD:
1206
        qemu_spice_wakeup(&d->ssd);
1207
        break;
1208
    case QXL_IO_NOTIFY_CURSOR:
1209
        qemu_spice_wakeup(&d->ssd);
1210
        break;
1211
    case QXL_IO_UPDATE_IRQ:
1212
        qxl_set_irq(d);
1213
        break;
1214
    case QXL_IO_NOTIFY_OOM:
1215
        if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) {
1216
            break;
1217
        }
1218
        pthread_yield();
1219
        if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) {
1220
            break;
1221
        }
1222
        d->oom_running = 1;
1223
        qxl_spice_oom(d);
1224
        d->oom_running = 0;
1225
        break;
1226
    case QXL_IO_SET_MODE:
1227
        dprint(d, 1, "QXL_SET_MODE %d\n", (int)val);
1228
        qxl_set_mode(d, val, 0);
1229
        break;
1230
    case QXL_IO_LOG:
1231
        if (d->guestdebug) {
1232
            fprintf(stderr, "qxl/guest-%d: %ld: %s", d->id,
1233
                    qemu_get_clock_ns(vm_clock), d->ram->log_buf);
1234
        }
1235
        break;
1236
    case QXL_IO_RESET:
1237
        dprint(d, 1, "QXL_IO_RESET\n");
1238
        qxl_hard_reset(d, 0);
1239
        break;
1240
    case QXL_IO_MEMSLOT_ADD:
1241
        if (val >= NUM_MEMSLOTS) {
1242
            qxl_guest_bug(d, "QXL_IO_MEMSLOT_ADD: val out of range");
1243
            break;
1244
        }
1245
        if (d->guest_slots[val].active) {
1246
            qxl_guest_bug(d, "QXL_IO_MEMSLOT_ADD: memory slot already active");
1247
            break;
1248
        }
1249
        d->guest_slots[val].slot = d->ram->mem_slot;
1250
        qxl_add_memslot(d, val, 0, async);
1251
        break;
1252
    case QXL_IO_MEMSLOT_DEL:
1253
        if (val >= NUM_MEMSLOTS) {
1254
            qxl_guest_bug(d, "QXL_IO_MEMSLOT_DEL: val out of range");
1255
            break;
1256
        }
1257
        qxl_del_memslot(d, val);
1258
        break;
1259
    case QXL_IO_CREATE_PRIMARY:
1260
        if (val != 0) {
1261
            qxl_guest_bug(d, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0",
1262
                          async);
1263
            goto cancel_async;
1264
        }
1265
        dprint(d, 1, "QXL_IO_CREATE_PRIMARY async=%d\n", async);
1266
        d->guest_primary.surface = d->ram->create_surface;
1267
        qxl_create_guest_primary(d, 0, async);
1268
        break;
1269
    case QXL_IO_DESTROY_PRIMARY:
1270
        if (val != 0) {
1271
            qxl_guest_bug(d, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0",
1272
                          async);
1273
            goto cancel_async;
1274
        }
1275
        dprint(d, 1, "QXL_IO_DESTROY_PRIMARY (async=%d) (%s)\n", async,
1276
               qxl_mode_to_string(d->mode));
1277
        if (!qxl_destroy_primary(d, async)) {
1278
            dprint(d, 1, "QXL_IO_DESTROY_PRIMARY_ASYNC in %s, ignored\n",
1279
                    qxl_mode_to_string(d->mode));
1280
            goto cancel_async;
1281
        }
1282
        break;
1283
    case QXL_IO_DESTROY_SURFACE_WAIT:
1284
        if (val >= NUM_SURFACES) {
1285
            qxl_guest_bug(d, "QXL_IO_DESTROY_SURFACE (async=%d):"
1286
                             "%d >= NUM_SURFACES", async, val);
1287
            goto cancel_async;
1288
        }
1289
        qxl_spice_destroy_surface_wait(d, val, async);
1290
        break;
1291
#if SPICE_INTERFACE_QXL_MINOR >= 1
1292
    case QXL_IO_FLUSH_RELEASE: {
1293
        QXLReleaseRing *ring = &d->ram->release_ring;
1294
        if (ring->prod - ring->cons + 1 == ring->num_items) {
1295
            fprintf(stderr,
1296
                "ERROR: no flush, full release ring [p%d,%dc]\n",
1297
                ring->prod, ring->cons);
1298
        }
1299
        qxl_push_free_res(d, 1 /* flush */);
1300
        dprint(d, 1, "QXL_IO_FLUSH_RELEASE exit (%s, s#=%d, res#=%d,%p)\n",
1301
            qxl_mode_to_string(d->mode), d->guest_surfaces.count,
1302
            d->num_free_res, d->last_release);
1303
        break;
1304
    }
1305
    case QXL_IO_FLUSH_SURFACES_ASYNC:
1306
        dprint(d, 1, "QXL_IO_FLUSH_SURFACES_ASYNC"
1307
                     " (%"PRId64") (%s, s#=%d, res#=%d)\n",
1308
               val, qxl_mode_to_string(d->mode), d->guest_surfaces.count,
1309
               d->num_free_res);
1310
        qxl_spice_flush_surfaces_async(d);
1311
        break;
1312
#endif
1313
    case QXL_IO_DESTROY_ALL_SURFACES:
1314
        d->mode = QXL_MODE_UNDEFINED;
1315
        qxl_spice_destroy_surfaces(d, async);
1316
        break;
1317
    default:
1318
        fprintf(stderr, "%s: ioport=0x%x, abort()\n", __FUNCTION__, io_port);
1319
        abort();
1320
    }
1321
    return;
1322
cancel_async:
1323
#if SPICE_INTERFACE_QXL_MINOR >= 1
1324
    if (async) {
1325
        qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1326
        qemu_mutex_lock(&d->async_lock);
1327
        d->current_async = QXL_UNDEFINED_IO;
1328
        qemu_mutex_unlock(&d->async_lock);
1329
    }
1330
#else
1331
    return;
1332
#endif
1333
}
1334

    
1335
static uint64_t ioport_read(void *opaque, target_phys_addr_t addr,
1336
                            unsigned size)
1337
{
1338
    PCIQXLDevice *d = opaque;
1339

    
1340
    dprint(d, 1, "%s: unexpected\n", __FUNCTION__);
1341
    return 0xff;
1342
}
1343

    
1344
static const MemoryRegionOps qxl_io_ops = {
1345
    .read = ioport_read,
1346
    .write = ioport_write,
1347
    .valid = {
1348
        .min_access_size = 1,
1349
        .max_access_size = 1,
1350
    },
1351
};
1352

    
1353
static void pipe_read(void *opaque)
1354
{
1355
    PCIQXLDevice *d = opaque;
1356
    char dummy;
1357
    int len;
1358

    
1359
    do {
1360
        len = read(d->pipe[0], &dummy, sizeof(dummy));
1361
    } while (len == sizeof(dummy));
1362
    qxl_set_irq(d);
1363
}
1364

    
1365
/* called from spice server thread context only */
1366
static void qxl_send_events(PCIQXLDevice *d, uint32_t events)
1367
{
1368
    uint32_t old_pending;
1369
    uint32_t le_events = cpu_to_le32(events);
1370

    
1371
    assert(d->ssd.running);
1372
    old_pending = __sync_fetch_and_or(&d->ram->int_pending, le_events);
1373
    if ((old_pending & le_events) == le_events) {
1374
        return;
1375
    }
1376
    if (pthread_self() == d->main) {
1377
        qxl_set_irq(d);
1378
    } else {
1379
        if (write(d->pipe[1], d, 1) != 1) {
1380
            dprint(d, 1, "%s: write to pipe failed\n", __FUNCTION__);
1381
        }
1382
    }
1383
}
1384

    
1385
static void init_pipe_signaling(PCIQXLDevice *d)
1386
{
1387
   if (pipe(d->pipe) < 0) {
1388
       dprint(d, 1, "%s: pipe creation failed\n", __FUNCTION__);
1389
       return;
1390
   }
1391
#ifdef CONFIG_IOTHREAD
1392
   fcntl(d->pipe[0], F_SETFL, O_NONBLOCK);
1393
#else
1394
   fcntl(d->pipe[0], F_SETFL, O_NONBLOCK /* | O_ASYNC */);
1395
#endif
1396
   fcntl(d->pipe[1], F_SETFL, O_NONBLOCK);
1397
   fcntl(d->pipe[0], F_SETOWN, getpid());
1398

    
1399
   d->main = pthread_self();
1400
   qemu_set_fd_handler(d->pipe[0], pipe_read, NULL, d);
1401
}
1402

    
1403
/* graphics console */
1404

    
1405
static void qxl_hw_update(void *opaque)
1406
{
1407
    PCIQXLDevice *qxl = opaque;
1408
    VGACommonState *vga = &qxl->vga;
1409

    
1410
    switch (qxl->mode) {
1411
    case QXL_MODE_VGA:
1412
        vga->update(vga);
1413
        break;
1414
    case QXL_MODE_COMPAT:
1415
    case QXL_MODE_NATIVE:
1416
        qxl_render_update(qxl);
1417
        break;
1418
    default:
1419
        break;
1420
    }
1421
}
1422

    
1423
static void qxl_hw_invalidate(void *opaque)
1424
{
1425
    PCIQXLDevice *qxl = opaque;
1426
    VGACommonState *vga = &qxl->vga;
1427

    
1428
    vga->invalidate(vga);
1429
}
1430

    
1431
static void qxl_hw_screen_dump(void *opaque, const char *filename)
1432
{
1433
    PCIQXLDevice *qxl = opaque;
1434
    VGACommonState *vga = &qxl->vga;
1435

    
1436
    switch (qxl->mode) {
1437
    case QXL_MODE_COMPAT:
1438
    case QXL_MODE_NATIVE:
1439
        qxl_render_update(qxl);
1440
        ppm_save(filename, qxl->ssd.ds->surface);
1441
        break;
1442
    case QXL_MODE_VGA:
1443
        vga->screen_dump(vga, filename);
1444
        break;
1445
    default:
1446
        break;
1447
    }
1448
}
1449

    
1450
static void qxl_hw_text_update(void *opaque, console_ch_t *chardata)
1451
{
1452
    PCIQXLDevice *qxl = opaque;
1453
    VGACommonState *vga = &qxl->vga;
1454

    
1455
    if (qxl->mode == QXL_MODE_VGA) {
1456
        vga->text_update(vga, chardata);
1457
        return;
1458
    }
1459
}
1460

    
1461
static void qxl_vm_change_state_handler(void *opaque, int running, int reason)
1462
{
1463
    PCIQXLDevice *qxl = opaque;
1464
    qemu_spice_vm_change_state_handler(&qxl->ssd, running, reason);
1465

    
1466
    if (!running && qxl->mode == QXL_MODE_NATIVE) {
1467
        /* dirty all vram (which holds surfaces) and devram (primary surface)
1468
         * to make sure they are saved */
1469
        /* FIXME #1: should go out during "live" stage */
1470
        /* FIXME #2: we only need to save the areas which are actually used */
1471
        qxl_set_dirty(&qxl->vram_bar, 0, qxl->vram_size);
1472
        qxl_set_dirty(&qxl->vga.vram, qxl->shadow_rom.draw_area_offset,
1473
                      qxl->shadow_rom.surface0_area_size);
1474
    }
1475
}
1476

    
1477
/* display change listener */
1478

    
1479
static void display_update(struct DisplayState *ds, int x, int y, int w, int h)
1480
{
1481
    if (qxl0->mode == QXL_MODE_VGA) {
1482
        qemu_spice_display_update(&qxl0->ssd, x, y, w, h);
1483
    }
1484
}
1485

    
1486
static void display_resize(struct DisplayState *ds)
1487
{
1488
    if (qxl0->mode == QXL_MODE_VGA) {
1489
        qemu_spice_display_resize(&qxl0->ssd);
1490
    }
1491
}
1492

    
1493
static void display_refresh(struct DisplayState *ds)
1494
{
1495
    if (qxl0->mode == QXL_MODE_VGA) {
1496
        qemu_spice_display_refresh(&qxl0->ssd);
1497
    }
1498
}
1499

    
1500
static DisplayChangeListener display_listener = {
1501
    .dpy_update  = display_update,
1502
    .dpy_resize  = display_resize,
1503
    .dpy_refresh = display_refresh,
1504
};
1505

    
1506
static int qxl_init_common(PCIQXLDevice *qxl)
1507
{
1508
    uint8_t* config = qxl->pci.config;
1509
    uint32_t pci_device_rev;
1510
    uint32_t io_size;
1511

    
1512
    qxl->mode = QXL_MODE_UNDEFINED;
1513
    qxl->generation = 1;
1514
    qxl->num_memslots = NUM_MEMSLOTS;
1515
    qxl->num_surfaces = NUM_SURFACES;
1516
    qemu_mutex_init(&qxl->track_lock);
1517
    qemu_mutex_init(&qxl->async_lock);
1518
    qxl->current_async = QXL_UNDEFINED_IO;
1519

    
1520
    switch (qxl->revision) {
1521
    case 1: /* spice 0.4 -- qxl-1 */
1522
        pci_device_rev = QXL_REVISION_STABLE_V04;
1523
        break;
1524
    case 2: /* spice 0.6 -- qxl-2 */
1525
        pci_device_rev = QXL_REVISION_STABLE_V06;
1526
        break;
1527
#if SPICE_INTERFACE_QXL_MINOR >= 1
1528
    case 3: /* qxl-3 */
1529
#endif
1530
    default:
1531
        pci_device_rev = QXL_DEFAULT_REVISION;
1532
        break;
1533
    }
1534

    
1535
    pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev);
1536
    pci_set_byte(&config[PCI_INTERRUPT_PIN], 1);
1537

    
1538
    qxl->rom_size = qxl_rom_size();
1539
    memory_region_init_ram(&qxl->rom_bar, &qxl->pci.qdev, "qxl.vrom",
1540
                           qxl->rom_size);
1541
    init_qxl_rom(qxl);
1542
    init_qxl_ram(qxl);
1543

    
1544
    if (qxl->vram_size < 16 * 1024 * 1024) {
1545
        qxl->vram_size = 16 * 1024 * 1024;
1546
    }
1547
    if (qxl->revision == 1) {
1548
        qxl->vram_size = 4096;
1549
    }
1550
    qxl->vram_size = msb_mask(qxl->vram_size * 2 - 1);
1551
    memory_region_init_ram(&qxl->vram_bar, &qxl->pci.qdev, "qxl.vram",
1552
                           qxl->vram_size);
1553

    
1554
    io_size = msb_mask(QXL_IO_RANGE_SIZE * 2 - 1);
1555
    if (qxl->revision == 1) {
1556
        io_size = 8;
1557
    }
1558

    
1559
    memory_region_init_io(&qxl->io_bar, &qxl_io_ops, qxl,
1560
                          "qxl-ioports", io_size);
1561
    if (qxl->id == 0) {
1562
        vga_dirty_log_start(&qxl->vga);
1563
    }
1564

    
1565

    
1566
    pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX,
1567
                     PCI_BASE_ADDRESS_SPACE_IO, &qxl->io_bar);
1568

    
1569
    pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX,
1570
                     PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->rom_bar);
1571

    
1572
    pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX,
1573
                     PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vga.vram);
1574

    
1575
    pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX,
1576
                     PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vram_bar);
1577

    
1578
    qxl->ssd.qxl.base.sif = &qxl_interface.base;
1579
    qxl->ssd.qxl.id = qxl->id;
1580
    qemu_spice_add_interface(&qxl->ssd.qxl.base);
1581
    qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl);
1582

    
1583
    init_pipe_signaling(qxl);
1584
    qxl_reset_state(qxl);
1585

    
1586
    return 0;
1587
}
1588

    
1589
static int qxl_init_primary(PCIDevice *dev)
1590
{
1591
    PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev);
1592
    VGACommonState *vga = &qxl->vga;
1593
    ram_addr_t ram_size = msb_mask(qxl->vga.vram_size * 2 - 1);
1594

    
1595
    qxl->id = 0;
1596

    
1597
    if (ram_size < 32 * 1024 * 1024) {
1598
        ram_size = 32 * 1024 * 1024;
1599
    }
1600
    vga_common_init(vga, ram_size);
1601
    vga_init(vga);
1602
    register_ioport_write(0x3c0, 16, 1, qxl_vga_ioport_write, vga);
1603
    register_ioport_write(0x3b4,  2, 1, qxl_vga_ioport_write, vga);
1604
    register_ioport_write(0x3d4,  2, 1, qxl_vga_ioport_write, vga);
1605
    register_ioport_write(0x3ba,  1, 1, qxl_vga_ioport_write, vga);
1606
    register_ioport_write(0x3da,  1, 1, qxl_vga_ioport_write, vga);
1607

    
1608
    vga->ds = graphic_console_init(qxl_hw_update, qxl_hw_invalidate,
1609
                                   qxl_hw_screen_dump, qxl_hw_text_update, qxl);
1610
    qemu_spice_display_init_common(&qxl->ssd, vga->ds);
1611

    
1612
    qxl0 = qxl;
1613
    register_displaychangelistener(vga->ds, &display_listener);
1614

    
1615
    return qxl_init_common(qxl);
1616
}
1617

    
1618
static int qxl_init_secondary(PCIDevice *dev)
1619
{
1620
    static int device_id = 1;
1621
    PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev);
1622
    ram_addr_t ram_size = msb_mask(qxl->vga.vram_size * 2 - 1);
1623

    
1624
    qxl->id = device_id++;
1625

    
1626
    if (ram_size < 16 * 1024 * 1024) {
1627
        ram_size = 16 * 1024 * 1024;
1628
    }
1629
    qxl->vga.vram_size = ram_size;
1630
    memory_region_init_ram(&qxl->vga.vram, &qxl->pci.qdev, "qxl.vgavram",
1631
                           qxl->vga.vram_size);
1632
    qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram);
1633

    
1634
    return qxl_init_common(qxl);
1635
}
1636

    
1637
static void qxl_pre_save(void *opaque)
1638
{
1639
    PCIQXLDevice* d = opaque;
1640
    uint8_t *ram_start = d->vga.vram_ptr;
1641

    
1642
    dprint(d, 1, "%s:\n", __FUNCTION__);
1643
    if (d->last_release == NULL) {
1644
        d->last_release_offset = 0;
1645
    } else {
1646
        d->last_release_offset = (uint8_t *)d->last_release - ram_start;
1647
    }
1648
    assert(d->last_release_offset < d->vga.vram_size);
1649
}
1650

    
1651
static int qxl_pre_load(void *opaque)
1652
{
1653
    PCIQXLDevice* d = opaque;
1654

    
1655
    dprint(d, 1, "%s: start\n", __FUNCTION__);
1656
    qxl_hard_reset(d, 1);
1657
    qxl_exit_vga_mode(d);
1658
    dprint(d, 1, "%s: done\n", __FUNCTION__);
1659
    return 0;
1660
}
1661

    
1662
static int qxl_post_load(void *opaque, int version)
1663
{
1664
    PCIQXLDevice* d = opaque;
1665
    uint8_t *ram_start = d->vga.vram_ptr;
1666
    QXLCommandExt *cmds;
1667
    int in, out, i, newmode;
1668

    
1669
    dprint(d, 1, "%s: start\n", __FUNCTION__);
1670

    
1671
    assert(d->last_release_offset < d->vga.vram_size);
1672
    if (d->last_release_offset == 0) {
1673
        d->last_release = NULL;
1674
    } else {
1675
        d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset);
1676
    }
1677

    
1678
    d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset);
1679

    
1680
    dprint(d, 1, "%s: restore mode (%s)\n", __FUNCTION__,
1681
        qxl_mode_to_string(d->mode));
1682
    newmode = d->mode;
1683
    d->mode = QXL_MODE_UNDEFINED;
1684
    switch (newmode) {
1685
    case QXL_MODE_UNDEFINED:
1686
        break;
1687
    case QXL_MODE_VGA:
1688
        qxl_enter_vga_mode(d);
1689
        break;
1690
    case QXL_MODE_NATIVE:
1691
        for (i = 0; i < NUM_MEMSLOTS; i++) {
1692
            if (!d->guest_slots[i].active) {
1693
                continue;
1694
            }
1695
            qxl_add_memslot(d, i, 0, QXL_SYNC);
1696
        }
1697
        qxl_create_guest_primary(d, 1, QXL_SYNC);
1698

    
1699
        /* replay surface-create and cursor-set commands */
1700
        cmds = g_malloc0(sizeof(QXLCommandExt) * (NUM_SURFACES + 1));
1701
        for (in = 0, out = 0; in < NUM_SURFACES; in++) {
1702
            if (d->guest_surfaces.cmds[in] == 0) {
1703
                continue;
1704
            }
1705
            cmds[out].cmd.data = d->guest_surfaces.cmds[in];
1706
            cmds[out].cmd.type = QXL_CMD_SURFACE;
1707
            cmds[out].group_id = MEMSLOT_GROUP_GUEST;
1708
            out++;
1709
        }
1710
        cmds[out].cmd.data = d->guest_cursor;
1711
        cmds[out].cmd.type = QXL_CMD_CURSOR;
1712
        cmds[out].group_id = MEMSLOT_GROUP_GUEST;
1713
        out++;
1714
        qxl_spice_loadvm_commands(d, cmds, out);
1715
        g_free(cmds);
1716

    
1717
        break;
1718
    case QXL_MODE_COMPAT:
1719
        qxl_set_mode(d, d->shadow_rom.mode, 1);
1720
        break;
1721
    }
1722
    dprint(d, 1, "%s: done\n", __FUNCTION__);
1723

    
1724
    return 0;
1725
}
1726

    
1727
#define QXL_SAVE_VERSION 21
1728

    
1729
static VMStateDescription qxl_memslot = {
1730
    .name               = "qxl-memslot",
1731
    .version_id         = QXL_SAVE_VERSION,
1732
    .minimum_version_id = QXL_SAVE_VERSION,
1733
    .fields = (VMStateField[]) {
1734
        VMSTATE_UINT64(slot.mem_start, struct guest_slots),
1735
        VMSTATE_UINT64(slot.mem_end,   struct guest_slots),
1736
        VMSTATE_UINT32(active,         struct guest_slots),
1737
        VMSTATE_END_OF_LIST()
1738
    }
1739
};
1740

    
1741
static VMStateDescription qxl_surface = {
1742
    .name               = "qxl-surface",
1743
    .version_id         = QXL_SAVE_VERSION,
1744
    .minimum_version_id = QXL_SAVE_VERSION,
1745
    .fields = (VMStateField[]) {
1746
        VMSTATE_UINT32(width,      QXLSurfaceCreate),
1747
        VMSTATE_UINT32(height,     QXLSurfaceCreate),
1748
        VMSTATE_INT32(stride,      QXLSurfaceCreate),
1749
        VMSTATE_UINT32(format,     QXLSurfaceCreate),
1750
        VMSTATE_UINT32(position,   QXLSurfaceCreate),
1751
        VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate),
1752
        VMSTATE_UINT32(flags,      QXLSurfaceCreate),
1753
        VMSTATE_UINT32(type,       QXLSurfaceCreate),
1754
        VMSTATE_UINT64(mem,        QXLSurfaceCreate),
1755
        VMSTATE_END_OF_LIST()
1756
    }
1757
};
1758

    
1759
static VMStateDescription qxl_vmstate = {
1760
    .name               = "qxl",
1761
    .version_id         = QXL_SAVE_VERSION,
1762
    .minimum_version_id = QXL_SAVE_VERSION,
1763
    .pre_save           = qxl_pre_save,
1764
    .pre_load           = qxl_pre_load,
1765
    .post_load          = qxl_post_load,
1766
    .fields = (VMStateField []) {
1767
        VMSTATE_PCI_DEVICE(pci, PCIQXLDevice),
1768
        VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState),
1769
        VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice),
1770
        VMSTATE_UINT32(num_free_res, PCIQXLDevice),
1771
        VMSTATE_UINT32(last_release_offset, PCIQXLDevice),
1772
        VMSTATE_UINT32(mode, PCIQXLDevice),
1773
        VMSTATE_UINT32(ssd.unique, PCIQXLDevice),
1774
        VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice),
1775
        VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0,
1776
                             qxl_memslot, struct guest_slots),
1777
        VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0,
1778
                       qxl_surface, QXLSurfaceCreate),
1779
        VMSTATE_INT32_EQUAL(num_surfaces, PCIQXLDevice),
1780
        VMSTATE_ARRAY(guest_surfaces.cmds, PCIQXLDevice, NUM_SURFACES, 0,
1781
                      vmstate_info_uint64, uint64_t),
1782
        VMSTATE_UINT64(guest_cursor, PCIQXLDevice),
1783
        VMSTATE_END_OF_LIST()
1784
    },
1785
};
1786

    
1787
static PCIDeviceInfo qxl_info_primary = {
1788
    .qdev.name    = "qxl-vga",
1789
    .qdev.desc    = "Spice QXL GPU (primary, vga compatible)",
1790
    .qdev.size    = sizeof(PCIQXLDevice),
1791
    .qdev.reset   = qxl_reset_handler,
1792
    .qdev.vmsd    = &qxl_vmstate,
1793
    .no_hotplug   = 1,
1794
    .init         = qxl_init_primary,
1795
    .romfile      = "vgabios-qxl.bin",
1796
    .vendor_id    = REDHAT_PCI_VENDOR_ID,
1797
    .device_id    = QXL_DEVICE_ID_STABLE,
1798
    .class_id     = PCI_CLASS_DISPLAY_VGA,
1799
    .qdev.props = (Property[]) {
1800
        DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size,
1801
                           64 * 1024 * 1024),
1802
        DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram_size,
1803
                           64 * 1024 * 1024),
1804
        DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision,
1805
                           QXL_DEFAULT_REVISION),
1806
        DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0),
1807
        DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0),
1808
        DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0),
1809
        DEFINE_PROP_END_OF_LIST(),
1810
    }
1811
};
1812

    
1813
static PCIDeviceInfo qxl_info_secondary = {
1814
    .qdev.name    = "qxl",
1815
    .qdev.desc    = "Spice QXL GPU (secondary)",
1816
    .qdev.size    = sizeof(PCIQXLDevice),
1817
    .qdev.reset   = qxl_reset_handler,
1818
    .qdev.vmsd    = &qxl_vmstate,
1819
    .init         = qxl_init_secondary,
1820
    .vendor_id    = REDHAT_PCI_VENDOR_ID,
1821
    .device_id    = QXL_DEVICE_ID_STABLE,
1822
    .class_id     = PCI_CLASS_DISPLAY_OTHER,
1823
    .qdev.props = (Property[]) {
1824
        DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size,
1825
                           64 * 1024 * 1024),
1826
        DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram_size,
1827
                           64 * 1024 * 1024),
1828
        DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision,
1829
                           QXL_DEFAULT_REVISION),
1830
        DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0),
1831
        DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0),
1832
        DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0),
1833
        DEFINE_PROP_END_OF_LIST(),
1834
    }
1835
};
1836

    
1837
static void qxl_register(void)
1838
{
1839
    pci_qdev_register(&qxl_info_primary);
1840
    pci_qdev_register(&qxl_info_secondary);
1841
}
1842

    
1843
device_init(qxl_register);