Revision 72c7b06c hw/ide.c
| b/hw/ide.c | ||
|---|---|---|
| 2844 | 2844 |
} |
| 2845 | 2845 |
} |
| 2846 | 2846 |
|
| 2847 |
static void ide_dma_cancel(BMDMAState *bm) |
|
| 2848 |
{
|
|
| 2849 |
if (bm->status & BM_STATUS_DMAING) {
|
|
| 2850 |
bm->status &= ~BM_STATUS_DMAING; |
|
| 2851 |
/* cancel DMA request */ |
|
| 2852 |
bm->ide_if = NULL; |
|
| 2853 |
bm->dma_cb = NULL; |
|
| 2854 |
if (bm->aiocb) {
|
|
| 2855 |
#ifdef DEBUG_AIO |
|
| 2856 |
printf("aio_cancel\n");
|
|
| 2857 |
#endif |
|
| 2858 |
bdrv_aio_cancel(bm->aiocb); |
|
| 2859 |
bm->aiocb = NULL; |
|
| 2860 |
} |
|
| 2861 |
} |
|
| 2862 |
} |
|
| 2863 |
|
|
| 2847 | 2864 |
static void bmdma_cmd_writeb(void *opaque, uint32_t addr, uint32_t val) |
| 2848 | 2865 |
{
|
| 2849 | 2866 |
BMDMAState *bm = opaque; |
| ... | ... | |
| 2852 | 2869 |
#endif |
| 2853 | 2870 |
if (!(val & BM_CMD_START)) {
|
| 2854 | 2871 |
/* XXX: do it better */ |
| 2855 |
if (bm->status & BM_STATUS_DMAING) {
|
|
| 2856 |
bm->status &= ~BM_STATUS_DMAING; |
|
| 2857 |
/* cancel DMA request */ |
|
| 2858 |
bm->ide_if = NULL; |
|
| 2859 |
bm->dma_cb = NULL; |
|
| 2860 |
if (bm->aiocb) {
|
|
| 2861 |
#ifdef DEBUG_AIO |
|
| 2862 |
printf("aio_cancel\n");
|
|
| 2863 |
#endif |
|
| 2864 |
bdrv_aio_cancel(bm->aiocb); |
|
| 2865 |
bm->aiocb = NULL; |
|
| 2866 |
} |
|
| 2867 |
} |
|
| 2872 |
ide_dma_cancel(bm); |
|
| 2868 | 2873 |
bm->cmd = val & 0x09; |
| 2869 | 2874 |
} else {
|
| 2870 | 2875 |
if (!(bm->status & BM_STATUS_DMAING)) {
|
| ... | ... | |
| 3188 | 3193 |
return 0; |
| 3189 | 3194 |
} |
| 3190 | 3195 |
|
| 3191 |
static void piix3_reset(PCIIDEState *d)
|
|
| 3196 |
static void piix3_reset(void *opaque)
|
|
| 3192 | 3197 |
{
|
| 3198 |
PCIIDEState *d = opaque; |
|
| 3193 | 3199 |
uint8_t *pci_conf = d->dev.config; |
| 3200 |
int i; |
|
| 3201 |
|
|
| 3202 |
for (i = 0; i < 2; i++) |
|
| 3203 |
ide_dma_cancel(&d->bmdma[i]); |
|
| 3194 | 3204 |
|
| 3195 | 3205 |
pci_conf[0x04] = 0x00; |
| 3196 | 3206 |
pci_conf[0x05] = 0x00; |
| ... | ... | |
| 3224 | 3234 |
pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage |
| 3225 | 3235 |
pci_conf[0x0e] = 0x00; // header_type |
| 3226 | 3236 |
|
| 3237 |
qemu_register_reset(piix3_reset, d); |
|
| 3227 | 3238 |
piix3_reset(d); |
| 3228 | 3239 |
|
| 3229 | 3240 |
pci_register_io_region((PCIDevice *)d, 4, 0x10, |
| ... | ... | |
| 3262 | 3273 |
pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage |
| 3263 | 3274 |
pci_conf[0x0e] = 0x00; // header_type |
| 3264 | 3275 |
|
| 3276 |
qemu_register_reset(piix3_reset, d); |
|
| 3265 | 3277 |
piix3_reset(d); |
| 3266 | 3278 |
|
| 3267 | 3279 |
pci_register_io_region((PCIDevice *)d, 4, 0x10, |
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