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root / target-sparc @ 72cf2d4f

Name Size
TODO 2.2 kB
cpu.h 18.4 kB
exec.h 977 Bytes
helper.c 45.8 kB
helper.h 4.6 kB
machine.c 6 kB
op_helper.c 102.1 kB
translate.c 187.7 kB

Latest revisions

# Date Author Comment
72cf2d4f 09/12/2009 10:36 am Blue Swirl

Fix sys-queue.h conflict for good

Problem: Our file sys-queue.h is a copy of the BSD file, but there are
some additions and it's not entirely compatible. Because of that, there have
been conflicts with system headers on BSD systems. Some hacks have been
introduced in the commits 15cc9235840a22c289edbe064a9b3c19c5f49896,...

0b5c1ce8 08/24/2009 04:21 pm Nathan Froyd

cleanup cpu-exec.c, part 0/N: consolidate handle_cpu_signal

handle_cpu_signal is very nearly copy-paste code for each target, with a
few minor variations. This patch sets up appropriate defaults for a
generic handle_cpu_signal and provides overrides for particular targets...

4c6aa085 08/22/2009 02:54 pm Blue Swirl

sparc32 remove an unnecessary cpu irq set

Signed-off-by: Artyom Tarasenko <>
Signed-off-by: Blue Swirl <>

c27e2752 08/22/2009 02:46 pm Blue Swirl

Sparc32/64: fix jmpl followed by branch

Fix a case where 'jmpl' instruction followed by a branch instruction was
handled incorrectly.

Signed-off-by: Blue Swirl <>

6b743278 08/18/2009 09:04 pm Blue Swirl

Sparc32/64: Fix user emulator breakage

Signed-off-by: Blue Swirl <>

cfa90513 08/15/2009 07:52 pm Blue Swirl

Fix desynchronization of condition code state when a memory access traps

Signed-off-by: Blue Swirl <>

8194f35a 08/04/2009 11:22 pm Igor Kovalenko

Sparc64: replace tsptr with helper routine

tl and tsptr of members sparc64 cpu state must be changed
simultaneously to keep trap state window in sync with current
trap level. Currently translation of store to tl does not change
tsptr, which leads to corrupt trap state on corresponding...

14ed7adc 07/31/2009 09:48 am Igor Kovalenko

sparc64 flush pending conditional evaluations before exposing cpu state

If translation block is interrupted by e.g. mmu exception
we need to compute conditional flags for inclusion into
saved cpu state. Otherwise after return from trap
conditional instructions would use stale psr/xcc data....

e2542fe2 07/27/2009 10:09 pm Juan Quintela


Signed-off-by: Juan Quintela <>
Signed-off-by: Anthony Liguori <>

f707726e 07/27/2009 08:43 am Igor Kovalenko

sparc64 really implement itlb/dtlb automatic replacement writes

- implement "used" bit in tlb translation entry
- mark tlb entry used if qemu code/data translation succeeds
- fold i/d mmu replacement writes code into replace_tlb_1bit_lru which
adds 1bit lru replacement algorithm; previously code tried to replace...

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