root / tcg / ppc64 / tcg-target.c @ 735ee40d
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/*
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* Tiny Code Generator for QEMU
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*
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* Copyright (c) 2008 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#define TCG_CT_CONST_U32 0x100 |
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static uint8_t *tb_ret_addr;
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#define FAST_PATH
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#if TARGET_PHYS_ADDR_BITS == 32 |
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#define LD_ADDEND LWZ
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#else
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#define LD_ADDEND LD
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#endif
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|
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#if TARGET_LONG_BITS == 32 |
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#define LD_ADDR LWZU
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#define CMP_L 0 |
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#else
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#define LD_ADDR LDU
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#define CMP_L (1<<21) |
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#endif
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|
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static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { |
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"r0",
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"r1",
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"rp",
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"r3",
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"r4",
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"r5",
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"r6",
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"r7",
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"r8",
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"r9",
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"r10",
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"r11",
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"r12",
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"r13",
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"r14",
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"r15",
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"r16",
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"r17",
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"r18",
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"r19",
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"r20",
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"r21",
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"r22",
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"r23",
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"r24",
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"r25",
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"r26",
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"r27",
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"r28",
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"r29",
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"r30",
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"r31"
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}; |
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|
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static const int tcg_target_reg_alloc_order[] = { |
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TCG_REG_R14, |
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TCG_REG_R15, |
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TCG_REG_R16, |
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TCG_REG_R17, |
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TCG_REG_R18, |
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TCG_REG_R19, |
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TCG_REG_R20, |
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TCG_REG_R21, |
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TCG_REG_R22, |
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TCG_REG_R23, |
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TCG_REG_R28, |
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TCG_REG_R29, |
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TCG_REG_R30, |
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TCG_REG_R31, |
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TCG_REG_R3, |
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TCG_REG_R4, |
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TCG_REG_R5, |
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TCG_REG_R6, |
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TCG_REG_R7, |
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TCG_REG_R8, |
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TCG_REG_R9, |
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TCG_REG_R10, |
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TCG_REG_R11, |
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TCG_REG_R12, |
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TCG_REG_R13, |
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TCG_REG_R0, |
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TCG_REG_R1, |
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TCG_REG_R2, |
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TCG_REG_R24, |
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TCG_REG_R25, |
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TCG_REG_R26, |
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TCG_REG_R27 |
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}; |
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|
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static const int tcg_target_call_iarg_regs[] = { |
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TCG_REG_R3, |
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TCG_REG_R4, |
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TCG_REG_R5, |
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TCG_REG_R6, |
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TCG_REG_R7, |
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TCG_REG_R8, |
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TCG_REG_R9, |
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TCG_REG_R10 |
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}; |
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|
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static const int tcg_target_call_oarg_regs[2] = { |
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TCG_REG_R3 |
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}; |
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|
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static const int tcg_target_callee_save_regs[] = { |
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TCG_REG_R14, |
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TCG_REG_R15, |
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TCG_REG_R16, |
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TCG_REG_R17, |
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TCG_REG_R18, |
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TCG_REG_R19, |
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TCG_REG_R20, |
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TCG_REG_R21, |
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TCG_REG_R22, |
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TCG_REG_R23, |
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TCG_REG_R28, |
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TCG_REG_R29, |
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TCG_REG_R30, |
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TCG_REG_R31 |
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}; |
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|
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static uint32_t reloc_pc24_val (void *pc, tcg_target_long target) |
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{
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tcg_target_long disp; |
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|
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disp = target - (tcg_target_long) pc; |
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if ((disp << 38) >> 38 != disp) |
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tcg_abort (); |
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|
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return disp & 0x3fffffc; |
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} |
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|
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static void reloc_pc24 (void *pc, tcg_target_long target) |
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{
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*(uint32_t *) pc = (*(uint32_t *) pc & ~0x3fffffc)
|
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| reloc_pc24_val (pc, target); |
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} |
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static uint16_t reloc_pc14_val (void *pc, tcg_target_long target) |
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{
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tcg_target_long disp; |
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|
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disp = target - (tcg_target_long) pc; |
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if (disp != (int16_t) disp)
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tcg_abort (); |
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|
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return disp & 0xfffc; |
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} |
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|
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static void reloc_pc14 (void *pc, tcg_target_long target) |
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{
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*(uint32_t *) pc = (*(uint32_t *) pc & ~0xfffc)
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| reloc_pc14_val (pc, target); |
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} |
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|
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static void patch_reloc (uint8_t *code_ptr, int type, |
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tcg_target_long value, tcg_target_long addend) |
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{
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value += addend; |
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switch (type) {
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case R_PPC_REL14:
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reloc_pc14 (code_ptr, value); |
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break;
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case R_PPC_REL24:
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reloc_pc24 (code_ptr, value); |
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break;
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default:
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tcg_abort (); |
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} |
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} |
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|
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/* maximum number of register used for input function arguments */
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static int tcg_target_get_call_iarg_regs_count (int flags) |
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{
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return sizeof (tcg_target_call_iarg_regs) / sizeof (tcg_target_call_iarg_regs[0]); |
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} |
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|
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/* parse target specific constraints */
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static int target_parse_constraint (TCGArgConstraint *ct, const char **pct_str) |
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{
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const char *ct_str; |
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|
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ct_str = *pct_str; |
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switch (ct_str[0]) { |
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case 'A': case 'B': case 'C': case 'D': |
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ct->ct |= TCG_CT_REG; |
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tcg_regset_set_reg (ct->u.regs, 3 + ct_str[0] - 'A'); |
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break;
|
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case 'r': |
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ct->ct |= TCG_CT_REG; |
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tcg_regset_set32 (ct->u.regs, 0, 0xffffffff); |
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break;
|
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case 'L': /* qemu_ld constraint */ |
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ct->ct |= TCG_CT_REG; |
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tcg_regset_set32 (ct->u.regs, 0, 0xffffffff); |
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tcg_regset_reset_reg (ct->u.regs, TCG_REG_R3); |
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#ifdef CONFIG_SOFTMMU
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tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4); |
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#endif
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break;
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case 'S': /* qemu_st constraint */ |
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ct->ct |= TCG_CT_REG; |
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tcg_regset_set32 (ct->u.regs, 0, 0xffffffff); |
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tcg_regset_reset_reg (ct->u.regs, TCG_REG_R3); |
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#ifdef CONFIG_SOFTMMU
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tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4); |
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tcg_regset_reset_reg (ct->u.regs, TCG_REG_R5); |
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#endif
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break;
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case 'Z': |
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ct->ct |= TCG_CT_CONST_U32; |
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break;
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default:
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return -1; |
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} |
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ct_str++; |
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*pct_str = ct_str; |
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return 0; |
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} |
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|
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/* test if a constant matches the constraint */
|
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static int tcg_target_const_match (tcg_target_long val, |
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const TCGArgConstraint *arg_ct)
|
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{
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int ct;
|
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|
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ct = arg_ct->ct; |
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if (ct & TCG_CT_CONST)
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return 1; |
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else if ((ct & TCG_CT_CONST_U32) && (val == (uint32_t) val)) |
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return 1; |
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return 0; |
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} |
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|
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#define OPCD(opc) ((opc)<<26) |
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#define XO19(opc) (OPCD(19)|((opc)<<1)) |
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#define XO30(opc) (OPCD(30)|((opc)<<2)) |
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#define XO31(opc) (OPCD(31)|((opc)<<1)) |
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#define XO58(opc) (OPCD(58)|(opc)) |
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#define XO62(opc) (OPCD(62)|(opc)) |
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|
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#define B OPCD( 18) |
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#define BC OPCD( 16) |
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#define LBZ OPCD( 34) |
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#define LHZ OPCD( 40) |
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#define LHA OPCD( 42) |
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#define LWZ OPCD( 32) |
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#define STB OPCD( 38) |
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#define STH OPCD( 44) |
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#define STW OPCD( 36) |
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|
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#define STD XO62( 0) |
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#define STDU XO62( 1) |
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#define STDX XO31(149) |
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|
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#define LD XO58( 0) |
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#define LDX XO31( 21) |
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#define LDU XO58( 1) |
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#define LWA XO58( 2) |
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#define LWAX XO31(341) |
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|
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#define ADDI OPCD( 14) |
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#define ADDIS OPCD( 15) |
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#define ORI OPCD( 24) |
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#define ORIS OPCD( 25) |
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#define XORI OPCD( 26) |
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#define XORIS OPCD( 27) |
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#define ANDI OPCD( 28) |
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#define ANDIS OPCD( 29) |
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#define MULLI OPCD( 7) |
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#define CMPLI OPCD( 10) |
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#define CMPI OPCD( 11) |
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|
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#define LWZU OPCD( 33) |
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#define STWU OPCD( 37) |
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|
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#define RLWINM OPCD( 21) |
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|
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#define RLDICL XO30( 0) |
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#define RLDICR XO30( 1) |
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|
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#define BCLR XO19( 16) |
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#define BCCTR XO19(528) |
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#define CRAND XO19(257) |
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#define CRANDC XO19(129) |
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#define CRNAND XO19(225) |
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#define CROR XO19(449) |
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|
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#define EXTSB XO31(954) |
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#define EXTSH XO31(922) |
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#define EXTSW XO31(986) |
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#define ADD XO31(266) |
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#define ADDE XO31(138) |
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#define ADDC XO31( 10) |
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#define AND XO31( 28) |
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#define SUBF XO31( 40) |
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#define SUBFC XO31( 8) |
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#define SUBFE XO31(136) |
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#define OR XO31(444) |
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#define XOR XO31(316) |
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#define MULLW XO31(235) |
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#define MULHWU XO31( 11) |
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#define DIVW XO31(491) |
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#define DIVWU XO31(459) |
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#define CMP XO31( 0) |
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#define CMPL XO31( 32) |
| 332 |
#define LHBRX XO31(790) |
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#define LWBRX XO31(534) |
| 334 |
#define STHBRX XO31(918) |
| 335 |
#define STWBRX XO31(662) |
| 336 |
#define MFSPR XO31(339) |
| 337 |
#define MTSPR XO31(467) |
| 338 |
#define SRAWI XO31(824) |
| 339 |
#define NEG XO31(104) |
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|
| 341 |
#define MULLD XO31(233) |
| 342 |
#define MULHD XO31( 73) |
| 343 |
#define MULHDU XO31( 9) |
| 344 |
#define DIVD XO31(489) |
| 345 |
#define DIVDU XO31(457) |
| 346 |
|
| 347 |
#define LBZX XO31( 87) |
| 348 |
#define LHZX XO31(276) |
| 349 |
#define LHAX XO31(343) |
| 350 |
#define LWZX XO31( 23) |
| 351 |
#define STBX XO31(215) |
| 352 |
#define STHX XO31(407) |
| 353 |
#define STWX XO31(151) |
| 354 |
|
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#define SPR(a,b) ((((a)<<5)|(b))<<11) |
| 356 |
#define LR SPR(8, 0) |
| 357 |
#define CTR SPR(9, 0) |
| 358 |
|
| 359 |
#define SLW XO31( 24) |
| 360 |
#define SRW XO31(536) |
| 361 |
#define SRAW XO31(792) |
| 362 |
|
| 363 |
#define SLD XO31( 27) |
| 364 |
#define SRD XO31(539) |
| 365 |
#define SRAD XO31(794) |
| 366 |
#define SRADI XO31(413<<1) |
| 367 |
|
| 368 |
#define LMW OPCD( 46) |
| 369 |
#define STMW OPCD( 47) |
| 370 |
|
| 371 |
#define TW XO31( 4) |
| 372 |
#define TRAP (TW | TO (31)) |
| 373 |
|
| 374 |
#define RT(r) ((r)<<21) |
| 375 |
#define RS(r) ((r)<<21) |
| 376 |
#define RA(r) ((r)<<16) |
| 377 |
#define RB(r) ((r)<<11) |
| 378 |
#define TO(t) ((t)<<21) |
| 379 |
#define SH(s) ((s)<<11) |
| 380 |
#define MB(b) ((b)<<6) |
| 381 |
#define ME(e) ((e)<<1) |
| 382 |
#define BO(o) ((o)<<21) |
| 383 |
#define MB64(b) ((b)<<5) |
| 384 |
|
| 385 |
#define LK 1 |
| 386 |
|
| 387 |
#define TAB(t,a,b) (RT(t) | RA(a) | RB(b))
|
| 388 |
#define SAB(s,a,b) (RS(s) | RA(a) | RB(b))
|
| 389 |
|
| 390 |
#define BF(n) ((n)<<23) |
| 391 |
#define BI(n, c) (((c)+((n)*4))<<16) |
| 392 |
#define BT(n, c) (((c)+((n)*4))<<21) |
| 393 |
#define BA(n, c) (((c)+((n)*4))<<16) |
| 394 |
#define BB(n, c) (((c)+((n)*4))<<11) |
| 395 |
|
| 396 |
#define BO_COND_TRUE BO (12) |
| 397 |
#define BO_COND_FALSE BO ( 4) |
| 398 |
#define BO_ALWAYS BO (20) |
| 399 |
|
| 400 |
enum {
|
| 401 |
CR_LT, |
| 402 |
CR_GT, |
| 403 |
CR_EQ, |
| 404 |
CR_SO |
| 405 |
}; |
| 406 |
|
| 407 |
static const uint32_t tcg_to_bc[10] = { |
| 408 |
[TCG_COND_EQ] = BC | BI (7, CR_EQ) | BO_COND_TRUE,
|
| 409 |
[TCG_COND_NE] = BC | BI (7, CR_EQ) | BO_COND_FALSE,
|
| 410 |
[TCG_COND_LT] = BC | BI (7, CR_LT) | BO_COND_TRUE,
|
| 411 |
[TCG_COND_GE] = BC | BI (7, CR_LT) | BO_COND_FALSE,
|
| 412 |
[TCG_COND_LE] = BC | BI (7, CR_GT) | BO_COND_FALSE,
|
| 413 |
[TCG_COND_GT] = BC | BI (7, CR_GT) | BO_COND_TRUE,
|
| 414 |
[TCG_COND_LTU] = BC | BI (7, CR_LT) | BO_COND_TRUE,
|
| 415 |
[TCG_COND_GEU] = BC | BI (7, CR_LT) | BO_COND_FALSE,
|
| 416 |
[TCG_COND_LEU] = BC | BI (7, CR_GT) | BO_COND_FALSE,
|
| 417 |
[TCG_COND_GTU] = BC | BI (7, CR_GT) | BO_COND_TRUE,
|
| 418 |
}; |
| 419 |
|
| 420 |
static void tcg_out_mov (TCGContext *s, int ret, int arg) |
| 421 |
{
|
| 422 |
tcg_out32 (s, OR | SAB (arg, ret, arg)); |
| 423 |
} |
| 424 |
|
| 425 |
static void tcg_out_rld (TCGContext *s, int op, int ra, int rs, int sh, int mb) |
| 426 |
{
|
| 427 |
sh = SH (sh & 0x1f) | (((sh >> 5) & 1) << 1); |
| 428 |
mb = MB64 ((mb >> 5) | ((mb << 1) & 0x3f)); |
| 429 |
tcg_out32 (s, op | RA (ra) | RS (rs) | sh | mb); |
| 430 |
} |
| 431 |
|
| 432 |
static void tcg_out_movi32 (TCGContext *s, int ret, int32_t arg) |
| 433 |
{
|
| 434 |
if (arg == (int16_t) arg)
|
| 435 |
tcg_out32 (s, ADDI | RT (ret) | RA (0) | (arg & 0xffff)); |
| 436 |
else {
|
| 437 |
tcg_out32 (s, ADDIS | RT (ret) | RA (0) | ((arg >> 16) & 0xffff)); |
| 438 |
if (arg & 0xffff) |
| 439 |
tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff));
|
| 440 |
} |
| 441 |
} |
| 442 |
|
| 443 |
static void tcg_out_movi (TCGContext *s, TCGType type, |
| 444 |
int ret, tcg_target_long arg)
|
| 445 |
{
|
| 446 |
int32_t arg32 = arg; |
| 447 |
|
| 448 |
if (type == TCG_TYPE_I32 || arg == arg32) {
|
| 449 |
tcg_out_movi32 (s, ret, arg32); |
| 450 |
} |
| 451 |
else {
|
| 452 |
if ((uint64_t) arg >> 32) { |
| 453 |
uint16_t h16 = arg >> 16;
|
| 454 |
uint16_t l16 = arg; |
| 455 |
|
| 456 |
tcg_out_movi32 (s, ret, arg >> 32);
|
| 457 |
tcg_out_rld (s, RLDICR, ret, ret, 32, 31); |
| 458 |
if (h16) tcg_out32 (s, ORIS | RS (ret) | RA (ret) | h16);
|
| 459 |
if (l16) tcg_out32 (s, ORI | RS (ret) | RA (ret) | l16);
|
| 460 |
} |
| 461 |
else {
|
| 462 |
tcg_out_movi32 (s, ret, arg32); |
| 463 |
if (arg32 < 0) |
| 464 |
tcg_out_rld (s, RLDICL, ret, ret, 0, 32); |
| 465 |
} |
| 466 |
} |
| 467 |
} |
| 468 |
|
| 469 |
static void tcg_out_call (TCGContext *s, tcg_target_long arg, int const_arg) |
| 470 |
{
|
| 471 |
int reg;
|
| 472 |
|
| 473 |
if (const_arg) {
|
| 474 |
reg = 2;
|
| 475 |
tcg_out_movi (s, TCG_TYPE_I64, reg, arg); |
| 476 |
} |
| 477 |
else reg = arg;
|
| 478 |
|
| 479 |
tcg_out32 (s, LD | RT (0) | RA (reg));
|
| 480 |
tcg_out32 (s, MTSPR | RA (0) | CTR);
|
| 481 |
tcg_out32 (s, LD | RT (11) | RA (reg) | 16); |
| 482 |
tcg_out32 (s, LD | RT (2) | RA (reg) | 8); |
| 483 |
tcg_out32 (s, BCCTR | BO_ALWAYS | LK); |
| 484 |
} |
| 485 |
|
| 486 |
static void tcg_out_ldst (TCGContext *s, int ret, int addr, |
| 487 |
int offset, int op1, int op2) |
| 488 |
{
|
| 489 |
if (offset == (int16_t) offset)
|
| 490 |
tcg_out32 (s, op1 | RT (ret) | RA (addr) | (offset & 0xffff));
|
| 491 |
else {
|
| 492 |
tcg_out_movi (s, TCG_TYPE_I64, 0, offset);
|
| 493 |
tcg_out32 (s, op2 | RT (ret) | RA (addr) | RB (0));
|
| 494 |
} |
| 495 |
} |
| 496 |
|
| 497 |
static void tcg_out_b (TCGContext *s, int mask, tcg_target_long target) |
| 498 |
{
|
| 499 |
tcg_target_long disp; |
| 500 |
|
| 501 |
disp = target - (tcg_target_long) s->code_ptr; |
| 502 |
if ((disp << 38) >> 38 == disp) |
| 503 |
tcg_out32 (s, B | (disp & 0x3fffffc) | mask);
|
| 504 |
else {
|
| 505 |
tcg_out_movi (s, TCG_TYPE_I64, 0, (tcg_target_long) target);
|
| 506 |
tcg_out32 (s, MTSPR | RS (0) | CTR);
|
| 507 |
tcg_out32 (s, BCCTR | BO_ALWAYS | mask); |
| 508 |
} |
| 509 |
} |
| 510 |
|
| 511 |
#if defined (CONFIG_SOFTMMU)
|
| 512 |
extern void __ldb_mmu(void); |
| 513 |
extern void __ldw_mmu(void); |
| 514 |
extern void __ldl_mmu(void); |
| 515 |
extern void __ldq_mmu(void); |
| 516 |
|
| 517 |
extern void __stb_mmu(void); |
| 518 |
extern void __stw_mmu(void); |
| 519 |
extern void __stl_mmu(void); |
| 520 |
extern void __stq_mmu(void); |
| 521 |
|
| 522 |
static void *qemu_ld_helpers[4] = { |
| 523 |
__ldb_mmu, |
| 524 |
__ldw_mmu, |
| 525 |
__ldl_mmu, |
| 526 |
__ldq_mmu, |
| 527 |
}; |
| 528 |
|
| 529 |
static void *qemu_st_helpers[4] = { |
| 530 |
__stb_mmu, |
| 531 |
__stw_mmu, |
| 532 |
__stl_mmu, |
| 533 |
__stq_mmu, |
| 534 |
}; |
| 535 |
|
| 536 |
static void tcg_out_tlb_read (TCGContext *s, int r0, int r1, int r2, |
| 537 |
int addr_reg, int s_bits, int offset) |
| 538 |
{
|
| 539 |
#if TARGET_LONG_BITS == 32 |
| 540 |
tcg_out_rld (s, RLDICL, addr_reg, addr_reg, 0, 32); |
| 541 |
|
| 542 |
tcg_out32 (s, (RLWINM |
| 543 |
| RA (r0) |
| 544 |
| RS (addr_reg) |
| 545 |
| SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
|
| 546 |
| MB (32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS))
|
| 547 |
| ME (31 - CPU_TLB_ENTRY_BITS)
|
| 548 |
) |
| 549 |
); |
| 550 |
tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0)); |
| 551 |
tcg_out32 (s, (LWZU | RT (r1) | RA (r0) | offset)); |
| 552 |
tcg_out32 (s, (RLWINM |
| 553 |
| RA (r2) |
| 554 |
| RS (addr_reg) |
| 555 |
| SH (0)
|
| 556 |
| MB ((32 - s_bits) & 31) |
| 557 |
| ME (31 - TARGET_PAGE_BITS)
|
| 558 |
) |
| 559 |
); |
| 560 |
#else
|
| 561 |
tcg_out_rld (s, RLDICL, r0, addr_reg, |
| 562 |
64 - TARGET_PAGE_BITS,
|
| 563 |
64 - CPU_TLB_BITS);
|
| 564 |
tcg_out_rld (s, RLDICR, r0, r0, |
| 565 |
CPU_TLB_ENTRY_BITS, |
| 566 |
63 - CPU_TLB_ENTRY_BITS);
|
| 567 |
|
| 568 |
tcg_out32 (s, ADD | TAB (r0, r0, TCG_AREG0)); |
| 569 |
tcg_out32 (s, LD_ADDR | RT (r1) | RA (r0) | offset); |
| 570 |
|
| 571 |
if (!s_bits) {
|
| 572 |
tcg_out_rld (s, RLDICR, r2, addr_reg, 0, 63 - TARGET_PAGE_BITS); |
| 573 |
} |
| 574 |
else {
|
| 575 |
tcg_out_rld (s, RLDICL, r2, addr_reg, |
| 576 |
64 - TARGET_PAGE_BITS,
|
| 577 |
TARGET_PAGE_BITS - s_bits); |
| 578 |
tcg_out_rld (s, RLDICL, r2, r2, TARGET_PAGE_BITS, 0);
|
| 579 |
} |
| 580 |
#endif
|
| 581 |
} |
| 582 |
#endif
|
| 583 |
|
| 584 |
static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc) |
| 585 |
{
|
| 586 |
int addr_reg, data_reg, r0, r1, mem_index, s_bits, bswap;
|
| 587 |
#ifdef CONFIG_SOFTMMU
|
| 588 |
int r2;
|
| 589 |
void *label1_ptr, *label2_ptr;
|
| 590 |
#endif
|
| 591 |
|
| 592 |
data_reg = *args++; |
| 593 |
addr_reg = *args++; |
| 594 |
mem_index = *args; |
| 595 |
s_bits = opc & 3;
|
| 596 |
|
| 597 |
#ifdef CONFIG_SOFTMMU
|
| 598 |
r0 = 3;
|
| 599 |
r1 = 4;
|
| 600 |
r2 = 0;
|
| 601 |
|
| 602 |
tcg_out_tlb_read (s, r0, r1, r2, addr_reg, s_bits, |
| 603 |
offsetof (CPUState, tlb_table[mem_index][0].addr_read));
|
| 604 |
|
| 605 |
tcg_out32 (s, CMP | BF (7) | RA (r2) | RB (r1) | CMP_L);
|
| 606 |
|
| 607 |
label1_ptr = s->code_ptr; |
| 608 |
#ifdef FAST_PATH
|
| 609 |
tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
|
| 610 |
#endif
|
| 611 |
|
| 612 |
/* slow path */
|
| 613 |
tcg_out_mov (s, 3, addr_reg);
|
| 614 |
tcg_out_movi (s, TCG_TYPE_I64, 4, mem_index);
|
| 615 |
|
| 616 |
tcg_out_call (s, (tcg_target_long) qemu_ld_helpers[s_bits], 1);
|
| 617 |
|
| 618 |
switch (opc) {
|
| 619 |
case 0|4: |
| 620 |
tcg_out32 (s, EXTSB | RA (data_reg) | RS (3));
|
| 621 |
break;
|
| 622 |
case 1|4: |
| 623 |
tcg_out32 (s, EXTSH | RA (data_reg) | RS (3));
|
| 624 |
break;
|
| 625 |
case 2|4: |
| 626 |
tcg_out32 (s, EXTSW | RA (data_reg) | RS (3));
|
| 627 |
break;
|
| 628 |
case 0: |
| 629 |
case 1: |
| 630 |
case 2: |
| 631 |
case 3: |
| 632 |
if (data_reg != 3) |
| 633 |
tcg_out_mov (s, data_reg, 3);
|
| 634 |
break;
|
| 635 |
} |
| 636 |
label2_ptr = s->code_ptr; |
| 637 |
tcg_out32 (s, B); |
| 638 |
|
| 639 |
/* label1: fast path */
|
| 640 |
#ifdef FAST_PATH
|
| 641 |
reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr); |
| 642 |
#endif
|
| 643 |
|
| 644 |
/* r0 now contains &env->tlb_table[mem_index][index].addr_read */
|
| 645 |
tcg_out32 (s, (LD_ADDEND |
| 646 |
| RT (r0) |
| 647 |
| RA (r0) |
| 648 |
| (offsetof (CPUTLBEntry, addend) |
| 649 |
- offsetof (CPUTLBEntry, addr_read)) |
| 650 |
)); |
| 651 |
/* r0 = env->tlb_table[mem_index][index].addend */
|
| 652 |
tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg)); |
| 653 |
/* r0 = env->tlb_table[mem_index][index].addend + addr */
|
| 654 |
|
| 655 |
#else /* !CONFIG_SOFTMMU */ |
| 656 |
#if TARGET_LONG_BITS == 32 |
| 657 |
tcg_out_rld (s, RLDICL, addr_reg, addr_reg, 0, 32); |
| 658 |
#endif
|
| 659 |
r0 = addr_reg; |
| 660 |
r1 = 3;
|
| 661 |
#endif
|
| 662 |
|
| 663 |
#ifdef TARGET_WORDS_BIGENDIAN
|
| 664 |
bswap = 0;
|
| 665 |
#else
|
| 666 |
bswap = 1;
|
| 667 |
#endif
|
| 668 |
switch (opc) {
|
| 669 |
default:
|
| 670 |
case 0: |
| 671 |
tcg_out32 (s, LBZ | RT (data_reg) | RA (r0)); |
| 672 |
break;
|
| 673 |
case 0|4: |
| 674 |
tcg_out32 (s, LBZ | RT (data_reg) | RA (r0)); |
| 675 |
tcg_out32 (s, EXTSB | RA (data_reg) | RS (data_reg)); |
| 676 |
break;
|
| 677 |
case 1: |
| 678 |
if (bswap) tcg_out32 (s, LHBRX | RT (data_reg) | RB (r0));
|
| 679 |
else tcg_out32 (s, LHZ | RT (data_reg) | RA (r0));
|
| 680 |
break;
|
| 681 |
case 1|4: |
| 682 |
if (bswap) {
|
| 683 |
tcg_out32 (s, LHBRX | RT (data_reg) | RB (r0)); |
| 684 |
tcg_out32 (s, EXTSH | RA (data_reg) | RS (data_reg)); |
| 685 |
} |
| 686 |
else tcg_out32 (s, LHA | RT (data_reg) | RA (r0));
|
| 687 |
break;
|
| 688 |
case 2: |
| 689 |
if (bswap) tcg_out32 (s, LWBRX | RT (data_reg) | RB (r0));
|
| 690 |
else tcg_out32 (s, LWZ | RT (data_reg)| RA (r0));
|
| 691 |
break;
|
| 692 |
case 2|4: |
| 693 |
if (bswap) {
|
| 694 |
tcg_out32 (s, LWBRX | RT (data_reg) | RB (r0)); |
| 695 |
tcg_out32 (s, EXTSW | RA (data_reg) | RS (data_reg)); |
| 696 |
} |
| 697 |
else tcg_out32 (s, LWA | RT (data_reg)| RA (r0));
|
| 698 |
break;
|
| 699 |
case 3: |
| 700 |
if (bswap) {
|
| 701 |
tcg_out32 (s, LWBRX | RT (0) | RB (r0));
|
| 702 |
tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
|
| 703 |
tcg_out32 (s, LWBRX | RT (data_reg) | RB (r1)); |
| 704 |
tcg_out_rld (s, RLDICR, data_reg, data_reg, 32, 31); |
| 705 |
tcg_out32 (s, OR | SAB (0, data_reg, data_reg));
|
| 706 |
} |
| 707 |
else tcg_out32 (s, LD | RT (data_reg) | RA (r0));
|
| 708 |
break;
|
| 709 |
} |
| 710 |
|
| 711 |
#ifdef CONFIG_SOFTMMU
|
| 712 |
reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr); |
| 713 |
#endif
|
| 714 |
} |
| 715 |
|
| 716 |
static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc) |
| 717 |
{
|
| 718 |
int addr_reg, r0, r1, data_reg, mem_index, bswap;
|
| 719 |
#ifdef CONFIG_SOFTMMU
|
| 720 |
int r2;
|
| 721 |
void *label1_ptr, *label2_ptr;
|
| 722 |
#endif
|
| 723 |
|
| 724 |
data_reg = *args++; |
| 725 |
addr_reg = *args++; |
| 726 |
mem_index = *args; |
| 727 |
|
| 728 |
#ifdef CONFIG_SOFTMMU
|
| 729 |
r0 = 3;
|
| 730 |
r1 = 4;
|
| 731 |
r2 = 0;
|
| 732 |
|
| 733 |
tcg_out_tlb_read (s, r0, r1, r2, addr_reg, opc, |
| 734 |
offsetof (CPUState, tlb_table[mem_index][0].addr_write));
|
| 735 |
|
| 736 |
tcg_out32 (s, CMP | BF (7) | RA (r2) | RB (r1) | CMP_L);
|
| 737 |
|
| 738 |
label1_ptr = s->code_ptr; |
| 739 |
#ifdef FAST_PATH
|
| 740 |
tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
|
| 741 |
#endif
|
| 742 |
|
| 743 |
/* slow path */
|
| 744 |
tcg_out_mov (s, 3, addr_reg);
|
| 745 |
tcg_out_rld (s, RLDICL, 4, data_reg, 0, 64 - (1 << (3 + opc))); |
| 746 |
tcg_out_movi (s, TCG_TYPE_I64, 5, mem_index);
|
| 747 |
|
| 748 |
tcg_out_call (s, (tcg_target_long) qemu_st_helpers[opc], 1);
|
| 749 |
|
| 750 |
label2_ptr = s->code_ptr; |
| 751 |
tcg_out32 (s, B); |
| 752 |
|
| 753 |
/* label1: fast path */
|
| 754 |
#ifdef FAST_PATH
|
| 755 |
reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr); |
| 756 |
#endif
|
| 757 |
|
| 758 |
tcg_out32 (s, (LD_ADDEND |
| 759 |
| RT (r0) |
| 760 |
| RA (r0) |
| 761 |
| (offsetof (CPUTLBEntry, addend) |
| 762 |
- offsetof (CPUTLBEntry, addr_write)) |
| 763 |
)); |
| 764 |
/* r0 = env->tlb_table[mem_index][index].addend */
|
| 765 |
tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg)); |
| 766 |
/* r0 = env->tlb_table[mem_index][index].addend + addr */
|
| 767 |
|
| 768 |
#else /* !CONFIG_SOFTMMU */ |
| 769 |
#if TARGET_LONG_BITS == 32 |
| 770 |
tcg_out_rld (s, RLDICL, addr_reg, addr_reg, 0, 32); |
| 771 |
#endif
|
| 772 |
r1 = 3;
|
| 773 |
r0 = addr_reg; |
| 774 |
#endif
|
| 775 |
|
| 776 |
#ifdef TARGET_WORDS_BIGENDIAN
|
| 777 |
bswap = 0;
|
| 778 |
#else
|
| 779 |
bswap = 1;
|
| 780 |
#endif
|
| 781 |
switch (opc) {
|
| 782 |
case 0: |
| 783 |
tcg_out32 (s, STB | RS (data_reg) | RA (r0)); |
| 784 |
break;
|
| 785 |
case 1: |
| 786 |
if (bswap) tcg_out32 (s, STHBRX | RS (data_reg) | RA (0) | RB (r0)); |
| 787 |
else tcg_out32 (s, STH | RS (data_reg) | RA (r0));
|
| 788 |
break;
|
| 789 |
case 2: |
| 790 |
if (bswap) tcg_out32 (s, STWBRX | RS (data_reg) | RA (0) | RB (r0)); |
| 791 |
else tcg_out32 (s, STW | RS (data_reg) | RA (r0));
|
| 792 |
break;
|
| 793 |
case 3: |
| 794 |
if (bswap) {
|
| 795 |
tcg_out32 (s, STWBRX | RS (data_reg) | RA (0) | RB (r0));
|
| 796 |
tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
|
| 797 |
tcg_out_rld (s, RLDICL, 0, data_reg, 32, 0); |
| 798 |
tcg_out32 (s, STWBRX | RS (0) | RA (0) | RB (r1)); |
| 799 |
} |
| 800 |
else tcg_out32 (s, STD | RS (data_reg) | RA (r0));
|
| 801 |
break;
|
| 802 |
} |
| 803 |
|
| 804 |
#ifdef CONFIG_SOFTMMU
|
| 805 |
reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr); |
| 806 |
#endif
|
| 807 |
} |
| 808 |
|
| 809 |
void tcg_target_qemu_prologue (TCGContext *s)
|
| 810 |
{
|
| 811 |
int i, frame_size;
|
| 812 |
uint64_t addr; |
| 813 |
|
| 814 |
frame_size = 0
|
| 815 |
+ 8 /* back chain */ |
| 816 |
+ 8 /* CR */ |
| 817 |
+ 8 /* LR */ |
| 818 |
+ 8 /* compiler doubleword */ |
| 819 |
+ 8 /* link editor doubleword */ |
| 820 |
+ 8 /* TOC save area */ |
| 821 |
+ TCG_STATIC_CALL_ARGS_SIZE |
| 822 |
+ ARRAY_SIZE (tcg_target_callee_save_regs) * 8
|
| 823 |
; |
| 824 |
frame_size = (frame_size + 15) & ~15; |
| 825 |
|
| 826 |
/* First emit adhoc function descriptor */
|
| 827 |
addr = (uint64_t) s->code_ptr + 24;
|
| 828 |
tcg_out32 (s, addr >> 32); tcg_out32 (s, addr); /* entry point */ |
| 829 |
s->code_ptr += 16; /* skip TOC and environment pointer */ |
| 830 |
|
| 831 |
/* Prologue */
|
| 832 |
tcg_out32 (s, MFSPR | RT (0) | LR);
|
| 833 |
tcg_out32 (s, STDU | RS (1) | RA (1) | (-frame_size & 0xffff)); |
| 834 |
for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i) |
| 835 |
tcg_out32 (s, (STD |
| 836 |
| RS (tcg_target_callee_save_regs[i]) |
| 837 |
| RA (1)
|
| 838 |
| (i * 8 + 48 + TCG_STATIC_CALL_ARGS_SIZE) |
| 839 |
) |
| 840 |
); |
| 841 |
tcg_out32 (s, STD | RS (0) | RA (1) | (frame_size + 16)); |
| 842 |
|
| 843 |
tcg_out32 (s, MTSPR | RS (3) | CTR);
|
| 844 |
tcg_out32 (s, BCCTR | BO_ALWAYS); |
| 845 |
|
| 846 |
/* Epilogue */
|
| 847 |
tb_ret_addr = s->code_ptr; |
| 848 |
|
| 849 |
for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i) |
| 850 |
tcg_out32 (s, (LD |
| 851 |
| RT (tcg_target_callee_save_regs[i]) |
| 852 |
| RA (1)
|
| 853 |
| (i * 8 + 48 + TCG_STATIC_CALL_ARGS_SIZE) |
| 854 |
) |
| 855 |
); |
| 856 |
tcg_out32 (s, LD | RT (0) | RA (1) | (frame_size + 16)); |
| 857 |
tcg_out32 (s, MTSPR | RS (0) | LR);
|
| 858 |
tcg_out32 (s, ADDI | RT (1) | RA (1) | frame_size); |
| 859 |
tcg_out32 (s, BCLR | BO_ALWAYS); |
| 860 |
} |
| 861 |
|
| 862 |
static void tcg_out_ld (TCGContext *s, TCGType type, int ret, int arg1, |
| 863 |
tcg_target_long arg2) |
| 864 |
{
|
| 865 |
if (type == TCG_TYPE_I32)
|
| 866 |
tcg_out_ldst (s, ret, arg1, arg2, LWZ, LWZX); |
| 867 |
else
|
| 868 |
tcg_out_ldst (s, ret, arg1, arg2, LD, LDX); |
| 869 |
} |
| 870 |
|
| 871 |
static void tcg_out_st (TCGContext *s, TCGType type, int arg, int arg1, |
| 872 |
tcg_target_long arg2) |
| 873 |
{
|
| 874 |
if (type == TCG_TYPE_I32)
|
| 875 |
tcg_out_ldst (s, arg, arg1, arg2, STW, STWX); |
| 876 |
else
|
| 877 |
tcg_out_ldst (s, arg, arg1, arg2, STD, STDX); |
| 878 |
} |
| 879 |
|
| 880 |
static void ppc_addi32 (TCGContext *s, int rt, int ra, tcg_target_long si) |
| 881 |
{
|
| 882 |
if (!si && rt == ra)
|
| 883 |
return;
|
| 884 |
|
| 885 |
if (si == (int16_t) si)
|
| 886 |
tcg_out32 (s, ADDI | RT (rt) | RA (ra) | (si & 0xffff));
|
| 887 |
else {
|
| 888 |
uint16_t h = ((si >> 16) & 0xffff) + ((uint16_t) si >> 15); |
| 889 |
tcg_out32 (s, ADDIS | RT (rt) | RA (ra) | h); |
| 890 |
tcg_out32 (s, ADDI | RT (rt) | RA (rt) | (si & 0xffff));
|
| 891 |
} |
| 892 |
} |
| 893 |
|
| 894 |
static void ppc_addi64 (TCGContext *s, int rt, int ra, tcg_target_long si) |
| 895 |
{
|
| 896 |
/* XXX: suboptimal */
|
| 897 |
if (si == (int16_t) si
|
| 898 |
|| (((uint64_t) si >> 31) == 0) && (si & 0x8000) == 0) |
| 899 |
ppc_addi32 (s, rt, ra, si); |
| 900 |
else {
|
| 901 |
tcg_out_movi (s, TCG_TYPE_I64, 0, si);
|
| 902 |
tcg_out32 (s, ADD | RT (rt) | RA (ra)); |
| 903 |
} |
| 904 |
} |
| 905 |
|
| 906 |
static void tcg_out_addi (TCGContext *s, int reg, tcg_target_long val) |
| 907 |
{
|
| 908 |
ppc_addi64 (s, reg, reg, val); |
| 909 |
} |
| 910 |
|
| 911 |
static void tcg_out_cmp (TCGContext *s, int cond, TCGArg arg1, TCGArg arg2, |
| 912 |
int const_arg2, int cr, int arch64) |
| 913 |
{
|
| 914 |
int imm;
|
| 915 |
uint32_t op; |
| 916 |
|
| 917 |
switch (cond) {
|
| 918 |
case TCG_COND_EQ:
|
| 919 |
case TCG_COND_NE:
|
| 920 |
if (const_arg2) {
|
| 921 |
if ((int16_t) arg2 == arg2) {
|
| 922 |
op = CMPI; |
| 923 |
imm = 1;
|
| 924 |
break;
|
| 925 |
} |
| 926 |
else if ((uint16_t) arg2 == arg2) { |
| 927 |
op = CMPLI; |
| 928 |
imm = 1;
|
| 929 |
break;
|
| 930 |
} |
| 931 |
} |
| 932 |
op = CMPL; |
| 933 |
imm = 0;
|
| 934 |
break;
|
| 935 |
|
| 936 |
case TCG_COND_LT:
|
| 937 |
case TCG_COND_GE:
|
| 938 |
case TCG_COND_LE:
|
| 939 |
case TCG_COND_GT:
|
| 940 |
if (const_arg2) {
|
| 941 |
if ((int16_t) arg2 == arg2) {
|
| 942 |
op = CMPI; |
| 943 |
imm = 1;
|
| 944 |
break;
|
| 945 |
} |
| 946 |
} |
| 947 |
op = CMP; |
| 948 |
imm = 0;
|
| 949 |
break;
|
| 950 |
|
| 951 |
case TCG_COND_LTU:
|
| 952 |
case TCG_COND_GEU:
|
| 953 |
case TCG_COND_LEU:
|
| 954 |
case TCG_COND_GTU:
|
| 955 |
if (const_arg2) {
|
| 956 |
if ((uint16_t) arg2 == arg2) {
|
| 957 |
op = CMPLI; |
| 958 |
imm = 1;
|
| 959 |
break;
|
| 960 |
} |
| 961 |
} |
| 962 |
op = CMPL; |
| 963 |
imm = 0;
|
| 964 |
break;
|
| 965 |
|
| 966 |
default:
|
| 967 |
tcg_abort (); |
| 968 |
} |
| 969 |
op |= BF (cr) | (arch64 << 21);
|
| 970 |
|
| 971 |
if (imm)
|
| 972 |
tcg_out32 (s, op | RA (arg1) | (arg2 & 0xffff));
|
| 973 |
else {
|
| 974 |
if (const_arg2) {
|
| 975 |
tcg_out_movi (s, TCG_TYPE_I64, 0, arg2);
|
| 976 |
tcg_out32 (s, op | RA (arg1) | RB (0));
|
| 977 |
} |
| 978 |
else
|
| 979 |
tcg_out32 (s, op | RA (arg1) | RB (arg2)); |
| 980 |
} |
| 981 |
|
| 982 |
} |
| 983 |
|
| 984 |
static void tcg_out_bc (TCGContext *s, int bc, int label_index) |
| 985 |
{
|
| 986 |
TCGLabel *l = &s->labels[label_index]; |
| 987 |
|
| 988 |
if (l->has_value)
|
| 989 |
tcg_out32 (s, bc | reloc_pc14_val (s->code_ptr, l->u.value)); |
| 990 |
else {
|
| 991 |
uint16_t val = *(uint16_t *) &s->code_ptr[2];
|
| 992 |
|
| 993 |
/* Thanks to Andrzej Zaborowski */
|
| 994 |
tcg_out32 (s, bc | (val & 0xfffc));
|
| 995 |
tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL14, label_index, 0); |
| 996 |
} |
| 997 |
} |
| 998 |
|
| 999 |
static void tcg_out_brcond (TCGContext *s, int cond, |
| 1000 |
TCGArg arg1, TCGArg arg2, int const_arg2,
|
| 1001 |
int label_index, int arch64) |
| 1002 |
{
|
| 1003 |
tcg_out_cmp (s, cond, arg1, arg2, const_arg2, 7, arch64);
|
| 1004 |
tcg_out_bc (s, tcg_to_bc[cond], label_index); |
| 1005 |
} |
| 1006 |
|
| 1007 |
void ppc_tb_set_jmp_target (unsigned long jmp_addr, unsigned long addr) |
| 1008 |
{
|
| 1009 |
TCGContext s; |
| 1010 |
unsigned long patch_size; |
| 1011 |
|
| 1012 |
s.code_ptr = (uint8_t *) jmp_addr; |
| 1013 |
tcg_out_b (&s, 0, addr);
|
| 1014 |
patch_size = s.code_ptr - (uint8_t *) jmp_addr; |
| 1015 |
flush_icache_range (jmp_addr, jmp_addr + patch_size); |
| 1016 |
} |
| 1017 |
|
| 1018 |
static void tcg_out_op (TCGContext *s, int opc, const TCGArg *args, |
| 1019 |
const int *const_args) |
| 1020 |
{
|
| 1021 |
int c;
|
| 1022 |
|
| 1023 |
switch (opc) {
|
| 1024 |
case INDEX_op_exit_tb:
|
| 1025 |
tcg_out_movi (s, TCG_TYPE_I64, TCG_REG_R3, args[0]);
|
| 1026 |
tcg_out_b (s, 0, (tcg_target_long) tb_ret_addr);
|
| 1027 |
break;
|
| 1028 |
case INDEX_op_goto_tb:
|
| 1029 |
if (s->tb_jmp_offset) {
|
| 1030 |
/* direct jump method */
|
| 1031 |
|
| 1032 |
s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
|
| 1033 |
s->code_ptr += 28;
|
| 1034 |
} |
| 1035 |
else {
|
| 1036 |
tcg_abort (); |
| 1037 |
} |
| 1038 |
s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
|
| 1039 |
break;
|
| 1040 |
case INDEX_op_br:
|
| 1041 |
{
|
| 1042 |
TCGLabel *l = &s->labels[args[0]];
|
| 1043 |
|
| 1044 |
if (l->has_value) {
|
| 1045 |
tcg_out_b (s, 0, l->u.value);
|
| 1046 |
} |
| 1047 |
else {
|
| 1048 |
uint32_t val = *(uint32_t *) s->code_ptr; |
| 1049 |
|
| 1050 |
/* Thanks to Andrzej Zaborowski */
|
| 1051 |
tcg_out32 (s, B | (val & 0x3fffffc));
|
| 1052 |
tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL24, args[0], 0); |
| 1053 |
} |
| 1054 |
} |
| 1055 |
break;
|
| 1056 |
case INDEX_op_call:
|
| 1057 |
tcg_out_call (s, args[0], const_args[0]); |
| 1058 |
break;
|
| 1059 |
case INDEX_op_jmp:
|
| 1060 |
if (const_args[0]) { |
| 1061 |
tcg_out_b (s, 0, args[0]); |
| 1062 |
} |
| 1063 |
else {
|
| 1064 |
tcg_out32 (s, MTSPR | RS (args[0]) | CTR);
|
| 1065 |
tcg_out32 (s, BCCTR | BO_ALWAYS); |
| 1066 |
} |
| 1067 |
break;
|
| 1068 |
case INDEX_op_movi_i32:
|
| 1069 |
tcg_out_movi (s, TCG_TYPE_I32, args[0], args[1]); |
| 1070 |
break;
|
| 1071 |
case INDEX_op_movi_i64:
|
| 1072 |
tcg_out_movi (s, TCG_TYPE_I64, args[0], args[1]); |
| 1073 |
break;
|
| 1074 |
case INDEX_op_ld8u_i32:
|
| 1075 |
case INDEX_op_ld8u_i64:
|
| 1076 |
tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX); |
| 1077 |
break;
|
| 1078 |
case INDEX_op_ld8s_i32:
|
| 1079 |
case INDEX_op_ld8s_i64:
|
| 1080 |
tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX); |
| 1081 |
tcg_out32 (s, EXTSB | RS (args[0]) | RA (args[0])); |
| 1082 |
break;
|
| 1083 |
case INDEX_op_ld16u_i32:
|
| 1084 |
case INDEX_op_ld16u_i64:
|
| 1085 |
tcg_out_ldst (s, args[0], args[1], args[2], LHZ, LHZX); |
| 1086 |
break;
|
| 1087 |
case INDEX_op_ld16s_i32:
|
| 1088 |
case INDEX_op_ld16s_i64:
|
| 1089 |
tcg_out_ldst (s, args[0], args[1], args[2], LHA, LHAX); |
| 1090 |
break;
|
| 1091 |
case INDEX_op_ld_i32:
|
| 1092 |
case INDEX_op_ld32u_i64:
|
| 1093 |
tcg_out_ldst (s, args[0], args[1], args[2], LWZ, LWZX); |
| 1094 |
break;
|
| 1095 |
case INDEX_op_ld32s_i64:
|
| 1096 |
tcg_out_ldst (s, args[0], args[1], args[2], LWA, LWAX); |
| 1097 |
break;
|
| 1098 |
case INDEX_op_ld_i64:
|
| 1099 |
tcg_out_ldst (s, args[0], args[1], args[2], LD, LDX); |
| 1100 |
break;
|
| 1101 |
case INDEX_op_st8_i32:
|
| 1102 |
case INDEX_op_st8_i64:
|
| 1103 |
tcg_out_ldst (s, args[0], args[1], args[2], STB, STBX); |
| 1104 |
break;
|
| 1105 |
case INDEX_op_st16_i32:
|
| 1106 |
case INDEX_op_st16_i64:
|
| 1107 |
tcg_out_ldst (s, args[0], args[1], args[2], STH, STHX); |
| 1108 |
break;
|
| 1109 |
case INDEX_op_st_i32:
|
| 1110 |
case INDEX_op_st32_i64:
|
| 1111 |
tcg_out_ldst (s, args[0], args[1], args[2], STW, STWX); |
| 1112 |
break;
|
| 1113 |
case INDEX_op_st_i64:
|
| 1114 |
tcg_out_ldst (s, args[0], args[1], args[2], STD, STDX); |
| 1115 |
break;
|
| 1116 |
|
| 1117 |
case INDEX_op_add_i32:
|
| 1118 |
if (const_args[2]) |
| 1119 |
ppc_addi32 (s, args[0], args[1], args[2]); |
| 1120 |
else
|
| 1121 |
tcg_out32 (s, ADD | TAB (args[0], args[1], args[2])); |
| 1122 |
break;
|
| 1123 |
case INDEX_op_sub_i32:
|
| 1124 |
if (const_args[2]) |
| 1125 |
ppc_addi32 (s, args[0], args[1], -args[2]); |
| 1126 |
else
|
| 1127 |
tcg_out32 (s, SUBF | TAB (args[0], args[2], args[1])); |
| 1128 |
break;
|
| 1129 |
|
| 1130 |
case INDEX_op_and_i64:
|
| 1131 |
case INDEX_op_and_i32:
|
| 1132 |
if (const_args[2]) { |
| 1133 |
if ((args[2] & 0xffff) == args[2]) |
| 1134 |
tcg_out32 (s, ANDI | RS (args[1]) | RA (args[0]) | args[2]); |
| 1135 |
else if ((args[2] & 0xffff0000) == args[2]) |
| 1136 |
tcg_out32 (s, ANDIS | RS (args[1]) | RA (args[0]) |
| 1137 |
| ((args[2] >> 16) & 0xffff)); |
| 1138 |
else {
|
| 1139 |
tcg_out_movi (s, (opc == INDEX_op_and_i32 |
| 1140 |
? TCG_TYPE_I32 |
| 1141 |
: TCG_TYPE_I64), |
| 1142 |
0, args[2]); |
| 1143 |
tcg_out32 (s, AND | SAB (args[1], args[0], 0)); |
| 1144 |
} |
| 1145 |
} |
| 1146 |
else
|
| 1147 |
tcg_out32 (s, AND | SAB (args[1], args[0], args[2])); |
| 1148 |
break;
|
| 1149 |
case INDEX_op_or_i64:
|
| 1150 |
case INDEX_op_or_i32:
|
| 1151 |
if (const_args[2]) { |
| 1152 |
if (args[2] & 0xffff) { |
| 1153 |
tcg_out32 (s, ORI | RS (args[1]) | RA (args[0]) |
| 1154 |
| (args[2] & 0xffff)); |
| 1155 |
if (args[2] >> 16) |
| 1156 |
tcg_out32 (s, ORIS | RS (args[0]) | RA (args[0]) |
| 1157 |
| ((args[2] >> 16) & 0xffff)); |
| 1158 |
} |
| 1159 |
else {
|
| 1160 |
tcg_out32 (s, ORIS | RS (args[1]) | RA (args[0]) |
| 1161 |
| ((args[2] >> 16) & 0xffff)); |
| 1162 |
} |
| 1163 |
} |
| 1164 |
else
|
| 1165 |
tcg_out32 (s, OR | SAB (args[1], args[0], args[2])); |
| 1166 |
break;
|
| 1167 |
case INDEX_op_xor_i64:
|
| 1168 |
case INDEX_op_xor_i32:
|
| 1169 |
if (const_args[2]) { |
| 1170 |
if ((args[2] & 0xffff) == args[2]) |
| 1171 |
tcg_out32 (s, XORI | RS (args[1]) | RA (args[0]) |
| 1172 |
| (args[2] & 0xffff)); |
| 1173 |
else if ((args[2] & 0xffff0000) == args[2]) |
| 1174 |
tcg_out32 (s, XORIS | RS (args[1]) | RA (args[0]) |
| 1175 |
| ((args[2] >> 16) & 0xffff)); |
| 1176 |
else {
|
| 1177 |
tcg_out_movi (s, (opc == INDEX_op_and_i32 |
| 1178 |
? TCG_TYPE_I32 |
| 1179 |
: TCG_TYPE_I64), |
| 1180 |
0, args[2]); |
| 1181 |
tcg_out32 (s, XOR | SAB (args[1], args[0], 0)); |
| 1182 |
} |
| 1183 |
} |
| 1184 |
else
|
| 1185 |
tcg_out32 (s, XOR | SAB (args[1], args[0], args[2])); |
| 1186 |
break;
|
| 1187 |
|
| 1188 |
case INDEX_op_mul_i32:
|
| 1189 |
if (const_args[2]) { |
| 1190 |
if (args[2] == (int16_t) args[2]) |
| 1191 |
tcg_out32 (s, MULLI | RT (args[0]) | RA (args[1]) |
| 1192 |
| (args[2] & 0xffff)); |
| 1193 |
else {
|
| 1194 |
tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]); |
| 1195 |
tcg_out32 (s, MULLW | TAB (args[0], args[1], 0)); |
| 1196 |
} |
| 1197 |
} |
| 1198 |
else
|
| 1199 |
tcg_out32 (s, MULLW | TAB (args[0], args[1], args[2])); |
| 1200 |
break;
|
| 1201 |
|
| 1202 |
case INDEX_op_div_i32:
|
| 1203 |
tcg_out32 (s, DIVW | TAB (args[0], args[1], args[2])); |
| 1204 |
break;
|
| 1205 |
|
| 1206 |
case INDEX_op_divu_i32:
|
| 1207 |
tcg_out32 (s, DIVWU | TAB (args[0], args[1], args[2])); |
| 1208 |
break;
|
| 1209 |
|
| 1210 |
case INDEX_op_rem_i32:
|
| 1211 |
tcg_out32 (s, DIVW | TAB (0, args[1], args[2])); |
| 1212 |
tcg_out32 (s, MULLW | TAB (0, 0, args[2])); |
| 1213 |
tcg_out32 (s, SUBF | TAB (args[0], 0, args[1])); |
| 1214 |
break;
|
| 1215 |
|
| 1216 |
case INDEX_op_remu_i32:
|
| 1217 |
tcg_out32 (s, DIVWU | TAB (0, args[1], args[2])); |
| 1218 |
tcg_out32 (s, MULLW | TAB (0, 0, args[2])); |
| 1219 |
tcg_out32 (s, SUBF | TAB (args[0], 0, args[1])); |
| 1220 |
break;
|
| 1221 |
|
| 1222 |
case INDEX_op_shl_i32:
|
| 1223 |
if (const_args[2]) { |
| 1224 |
tcg_out32 (s, (RLWINM |
| 1225 |
| RA (args[0])
|
| 1226 |
| RS (args[1])
|
| 1227 |
| SH (args[2])
|
| 1228 |
| MB (0)
|
| 1229 |
| ME (31 - args[2]) |
| 1230 |
) |
| 1231 |
); |
| 1232 |
} |
| 1233 |
else
|
| 1234 |
tcg_out32 (s, SLW | SAB (args[1], args[0], args[2])); |
| 1235 |
break;
|
| 1236 |
case INDEX_op_shr_i32:
|
| 1237 |
if (const_args[2]) { |
| 1238 |
tcg_out32 (s, (RLWINM |
| 1239 |
| RA (args[0])
|
| 1240 |
| RS (args[1])
|
| 1241 |
| SH (32 - args[2]) |
| 1242 |
| MB (args[2])
|
| 1243 |
| ME (31)
|
| 1244 |
) |
| 1245 |
); |
| 1246 |
} |
| 1247 |
else
|
| 1248 |
tcg_out32 (s, SRW | SAB (args[1], args[0], args[2])); |
| 1249 |
break;
|
| 1250 |
case INDEX_op_sar_i32:
|
| 1251 |
if (const_args[2]) |
| 1252 |
tcg_out32 (s, SRAWI | RS (args[1]) | RA (args[0]) | SH (args[2])); |
| 1253 |
else
|
| 1254 |
tcg_out32 (s, SRAW | SAB (args[1], args[0], args[2])); |
| 1255 |
break;
|
| 1256 |
|
| 1257 |
case INDEX_op_brcond_i32:
|
| 1258 |
tcg_out_brcond (s, args[2], args[0], args[1], const_args[1], args[3], 0); |
| 1259 |
break;
|
| 1260 |
|
| 1261 |
case INDEX_op_brcond_i64:
|
| 1262 |
tcg_out_brcond (s, args[2], args[0], args[1], const_args[1], args[3], 1); |
| 1263 |
break;
|
| 1264 |
|
| 1265 |
case INDEX_op_neg_i32:
|
| 1266 |
case INDEX_op_neg_i64:
|
| 1267 |
tcg_out32 (s, NEG | RT (args[0]) | RA (args[1])); |
| 1268 |
break;
|
| 1269 |
|
| 1270 |
case INDEX_op_add_i64:
|
| 1271 |
if (const_args[2]) |
| 1272 |
ppc_addi64 (s, args[0], args[1], args[2]); |
| 1273 |
else
|
| 1274 |
tcg_out32 (s, ADD | TAB (args[0], args[1], args[2])); |
| 1275 |
break;
|
| 1276 |
case INDEX_op_sub_i64:
|
| 1277 |
if (const_args[2]) |
| 1278 |
ppc_addi64 (s, args[0], args[1], -args[2]); |
| 1279 |
else
|
| 1280 |
tcg_out32 (s, SUBF | TAB (args[0], args[2], args[1])); |
| 1281 |
break;
|
| 1282 |
|
| 1283 |
case INDEX_op_shl_i64:
|
| 1284 |
if (const_args[2]) |
| 1285 |
tcg_out_rld (s, RLDICR, args[0], args[1], args[2], 63 - args[2]); |
| 1286 |
else
|
| 1287 |
tcg_out32 (s, SLD | SAB (args[1], args[0], args[2])); |
| 1288 |
break;
|
| 1289 |
case INDEX_op_shr_i64:
|
| 1290 |
if (const_args[2]) |
| 1291 |
tcg_out_rld (s, RLDICL, args[0], args[1], 64 - args[2], args[2]); |
| 1292 |
else
|
| 1293 |
tcg_out32 (s, SRD | SAB (args[1], args[0], args[2])); |
| 1294 |
break;
|
| 1295 |
case INDEX_op_sar_i64:
|
| 1296 |
if (const_args[2]) { |
| 1297 |
int sh = SH (args[2] & 0x1f) | (((args[2] >> 5) & 1) << 1); |
| 1298 |
tcg_out32 (s, SRADI | RA (args[0]) | RS (args[1]) | sh); |
| 1299 |
} |
| 1300 |
else
|
| 1301 |
tcg_out32 (s, SRAD | SAB (args[1], args[0], args[2])); |
| 1302 |
break;
|
| 1303 |
|
| 1304 |
case INDEX_op_mul_i64:
|
| 1305 |
tcg_out32 (s, MULLD | TAB (args[0], args[1], args[2])); |
| 1306 |
break;
|
| 1307 |
case INDEX_op_div_i64:
|
| 1308 |
tcg_out32 (s, DIVD | TAB (args[0], args[1], args[2])); |
| 1309 |
break;
|
| 1310 |
case INDEX_op_divu_i64:
|
| 1311 |
tcg_out32 (s, DIVDU | TAB (args[0], args[1], args[2])); |
| 1312 |
break;
|
| 1313 |
case INDEX_op_rem_i64:
|
| 1314 |
tcg_out32 (s, DIVD | TAB (0, args[1], args[2])); |
| 1315 |
tcg_out32 (s, MULLD | TAB (0, 0, args[2])); |
| 1316 |
tcg_out32 (s, SUBF | TAB (args[0], 0, args[1])); |
| 1317 |
break;
|
| 1318 |
case INDEX_op_remu_i64:
|
| 1319 |
tcg_out32 (s, DIVDU | TAB (0, args[1], args[2])); |
| 1320 |
tcg_out32 (s, MULLD | TAB (0, 0, args[2])); |
| 1321 |
tcg_out32 (s, SUBF | TAB (args[0], 0, args[1])); |
| 1322 |
break;
|
| 1323 |
|
| 1324 |
case INDEX_op_qemu_ld8u:
|
| 1325 |
tcg_out_qemu_ld (s, args, 0);
|
| 1326 |
break;
|
| 1327 |
case INDEX_op_qemu_ld8s:
|
| 1328 |
tcg_out_qemu_ld (s, args, 0 | 4); |
| 1329 |
break;
|
| 1330 |
case INDEX_op_qemu_ld16u:
|
| 1331 |
tcg_out_qemu_ld (s, args, 1);
|
| 1332 |
break;
|
| 1333 |
case INDEX_op_qemu_ld16s:
|
| 1334 |
tcg_out_qemu_ld (s, args, 1 | 4); |
| 1335 |
break;
|
| 1336 |
case INDEX_op_qemu_ld32u:
|
| 1337 |
tcg_out_qemu_ld (s, args, 2);
|
| 1338 |
break;
|
| 1339 |
case INDEX_op_qemu_ld32s:
|
| 1340 |
tcg_out_qemu_ld (s, args, 2 | 4); |
| 1341 |
break;
|
| 1342 |
case INDEX_op_qemu_ld64:
|
| 1343 |
tcg_out_qemu_ld (s, args, 3);
|
| 1344 |
break;
|
| 1345 |
case INDEX_op_qemu_st8:
|
| 1346 |
tcg_out_qemu_st (s, args, 0);
|
| 1347 |
break;
|
| 1348 |
case INDEX_op_qemu_st16:
|
| 1349 |
tcg_out_qemu_st (s, args, 1);
|
| 1350 |
break;
|
| 1351 |
case INDEX_op_qemu_st32:
|
| 1352 |
tcg_out_qemu_st (s, args, 2);
|
| 1353 |
break;
|
| 1354 |
case INDEX_op_qemu_st64:
|
| 1355 |
tcg_out_qemu_st (s, args, 3);
|
| 1356 |
break;
|
| 1357 |
|
| 1358 |
case INDEX_op_ext8s_i32:
|
| 1359 |
case INDEX_op_ext8s_i64:
|
| 1360 |
c = EXTSB; |
| 1361 |
goto gen_ext;
|
| 1362 |
case INDEX_op_ext16s_i32:
|
| 1363 |
case INDEX_op_ext16s_i64:
|
| 1364 |
c = EXTSH; |
| 1365 |
goto gen_ext;
|
| 1366 |
case INDEX_op_ext32s_i64:
|
| 1367 |
c = EXTSW; |
| 1368 |
goto gen_ext;
|
| 1369 |
gen_ext:
|
| 1370 |
tcg_out32 (s, c | RS (args[1]) | RA (args[0])); |
| 1371 |
break;
|
| 1372 |
|
| 1373 |
default:
|
| 1374 |
tcg_dump_ops (s, stderr); |
| 1375 |
tcg_abort (); |
| 1376 |
} |
| 1377 |
} |
| 1378 |
|
| 1379 |
static const TCGTargetOpDef ppc_op_defs[] = { |
| 1380 |
{ INDEX_op_exit_tb, { } },
|
| 1381 |
{ INDEX_op_goto_tb, { } },
|
| 1382 |
{ INDEX_op_call, { "ri" } },
|
| 1383 |
{ INDEX_op_jmp, { "ri" } },
|
| 1384 |
{ INDEX_op_br, { } },
|
| 1385 |
|
| 1386 |
{ INDEX_op_mov_i32, { "r", "r" } },
|
| 1387 |
{ INDEX_op_mov_i64, { "r", "r" } },
|
| 1388 |
{ INDEX_op_movi_i32, { "r" } },
|
| 1389 |
{ INDEX_op_movi_i64, { "r" } },
|
| 1390 |
|
| 1391 |
{ INDEX_op_ld8u_i32, { "r", "r" } },
|
| 1392 |
{ INDEX_op_ld8s_i32, { "r", "r" } },
|
| 1393 |
{ INDEX_op_ld16u_i32, { "r", "r" } },
|
| 1394 |
{ INDEX_op_ld16s_i32, { "r", "r" } },
|
| 1395 |
{ INDEX_op_ld_i32, { "r", "r" } },
|
| 1396 |
{ INDEX_op_ld_i64, { "r", "r" } },
|
| 1397 |
{ INDEX_op_st8_i32, { "r", "r" } },
|
| 1398 |
{ INDEX_op_st8_i64, { "r", "r" } },
|
| 1399 |
{ INDEX_op_st16_i32, { "r", "r" } },
|
| 1400 |
{ INDEX_op_st16_i64, { "r", "r" } },
|
| 1401 |
{ INDEX_op_st_i32, { "r", "r" } },
|
| 1402 |
{ INDEX_op_st_i64, { "r", "r" } },
|
| 1403 |
{ INDEX_op_st32_i64, { "r", "r" } },
|
| 1404 |
|
| 1405 |
{ INDEX_op_ld8u_i64, { "r", "r" } },
|
| 1406 |
{ INDEX_op_ld8s_i64, { "r", "r" } },
|
| 1407 |
{ INDEX_op_ld16u_i64, { "r", "r" } },
|
| 1408 |
{ INDEX_op_ld16s_i64, { "r", "r" } },
|
| 1409 |
{ INDEX_op_ld32u_i64, { "r", "r" } },
|
| 1410 |
{ INDEX_op_ld32s_i64, { "r", "r" } },
|
| 1411 |
{ INDEX_op_ld_i64, { "r", "r" } },
|
| 1412 |
|
| 1413 |
{ INDEX_op_add_i32, { "r", "r", "ri" } },
|
| 1414 |
{ INDEX_op_mul_i32, { "r", "r", "ri" } },
|
| 1415 |
{ INDEX_op_div_i32, { "r", "r", "r" } },
|
| 1416 |
{ INDEX_op_divu_i32, { "r", "r", "r" } },
|
| 1417 |
{ INDEX_op_rem_i32, { "r", "r", "r" } },
|
| 1418 |
{ INDEX_op_remu_i32, { "r", "r", "r" } },
|
| 1419 |
{ INDEX_op_sub_i32, { "r", "r", "ri" } },
|
| 1420 |
{ INDEX_op_and_i32, { "r", "r", "ri" } },
|
| 1421 |
{ INDEX_op_or_i32, { "r", "r", "ri" } },
|
| 1422 |
{ INDEX_op_xor_i32, { "r", "r", "ri" } },
|
| 1423 |
|
| 1424 |
{ INDEX_op_shl_i32, { "r", "r", "ri" } },
|
| 1425 |
{ INDEX_op_shr_i32, { "r", "r", "ri" } },
|
| 1426 |
{ INDEX_op_sar_i32, { "r", "r", "ri" } },
|
| 1427 |
|
| 1428 |
{ INDEX_op_brcond_i32, { "r", "ri" } },
|
| 1429 |
{ INDEX_op_brcond_i64, { "r", "ri" } },
|
| 1430 |
|
| 1431 |
{ INDEX_op_neg_i32, { "r", "r" } },
|
| 1432 |
|
| 1433 |
{ INDEX_op_add_i64, { "r", "r", "ri" } },
|
| 1434 |
{ INDEX_op_sub_i64, { "r", "r", "ri" } },
|
| 1435 |
{ INDEX_op_and_i64, { "r", "r", "rZ" } },
|
| 1436 |
{ INDEX_op_or_i64, { "r", "r", "rZ" } },
|
| 1437 |
{ INDEX_op_xor_i64, { "r", "r", "rZ" } },
|
| 1438 |
|
| 1439 |
{ INDEX_op_shl_i64, { "r", "r", "ri" } },
|
| 1440 |
{ INDEX_op_shr_i64, { "r", "r", "ri" } },
|
| 1441 |
{ INDEX_op_sar_i64, { "r", "r", "ri" } },
|
| 1442 |
|
| 1443 |
{ INDEX_op_mul_i64, { "r", "r", "r" } },
|
| 1444 |
{ INDEX_op_div_i64, { "r", "r", "r" } },
|
| 1445 |
{ INDEX_op_divu_i64, { "r", "r", "r" } },
|
| 1446 |
{ INDEX_op_rem_i64, { "r", "r", "r" } },
|
| 1447 |
{ INDEX_op_remu_i64, { "r", "r", "r" } },
|
| 1448 |
|
| 1449 |
{ INDEX_op_neg_i64, { "r", "r" } },
|
| 1450 |
|
| 1451 |
{ INDEX_op_qemu_ld8u, { "r", "L" } },
|
| 1452 |
{ INDEX_op_qemu_ld8s, { "r", "L" } },
|
| 1453 |
{ INDEX_op_qemu_ld16u, { "r", "L" } },
|
| 1454 |
{ INDEX_op_qemu_ld16s, { "r", "L" } },
|
| 1455 |
{ INDEX_op_qemu_ld32u, { "r", "L" } },
|
| 1456 |
{ INDEX_op_qemu_ld32s, { "r", "L" } },
|
| 1457 |
{ INDEX_op_qemu_ld64, { "r", "L" } },
|
| 1458 |
|
| 1459 |
{ INDEX_op_qemu_st8, { "S", "S" } },
|
| 1460 |
{ INDEX_op_qemu_st16, { "S", "S" } },
|
| 1461 |
{ INDEX_op_qemu_st32, { "S", "S" } },
|
| 1462 |
{ INDEX_op_qemu_st64, { "S", "S", "S" } },
|
| 1463 |
|
| 1464 |
{ INDEX_op_ext8s_i32, { "r", "r" } },
|
| 1465 |
{ INDEX_op_ext16s_i32, { "r", "r" } },
|
| 1466 |
{ INDEX_op_ext8s_i64, { "r", "r" } },
|
| 1467 |
{ INDEX_op_ext16s_i64, { "r", "r" } },
|
| 1468 |
{ INDEX_op_ext32s_i64, { "r", "r" } },
|
| 1469 |
|
| 1470 |
{ -1 },
|
| 1471 |
}; |
| 1472 |
|
| 1473 |
void tcg_target_init (TCGContext *s)
|
| 1474 |
{
|
| 1475 |
tcg_regset_set32 (tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff); |
| 1476 |
tcg_regset_set32 (tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff); |
| 1477 |
tcg_regset_set32 (tcg_target_call_clobber_regs, 0,
|
| 1478 |
(1 << TCG_REG_R0) |
|
| 1479 |
(1 << TCG_REG_R3) |
|
| 1480 |
(1 << TCG_REG_R4) |
|
| 1481 |
(1 << TCG_REG_R5) |
|
| 1482 |
(1 << TCG_REG_R6) |
|
| 1483 |
(1 << TCG_REG_R7) |
|
| 1484 |
(1 << TCG_REG_R8) |
|
| 1485 |
(1 << TCG_REG_R9) |
|
| 1486 |
(1 << TCG_REG_R10) |
|
| 1487 |
(1 << TCG_REG_R11) |
|
| 1488 |
(1 << TCG_REG_R12)
|
| 1489 |
); |
| 1490 |
|
| 1491 |
tcg_regset_clear (s->reserved_regs); |
| 1492 |
tcg_regset_set_reg (s->reserved_regs, TCG_REG_R0); |
| 1493 |
tcg_regset_set_reg (s->reserved_regs, TCG_REG_R1); |
| 1494 |
tcg_regset_set_reg (s->reserved_regs, TCG_REG_R2); |
| 1495 |
tcg_regset_set_reg (s->reserved_regs, TCG_REG_R13); |
| 1496 |
|
| 1497 |
tcg_add_target_add_op_defs (ppc_op_defs); |
| 1498 |
} |