root / hw / pflash_cfi02.c @ 737e150e
History | View | Annotate | Download (23.8 kB)
1 |
/*
|
---|---|
2 |
* CFI parallel flash with AMD command set emulation
|
3 |
*
|
4 |
* Copyright (c) 2005 Jocelyn Mayer
|
5 |
*
|
6 |
* This library is free software; you can redistribute it and/or
|
7 |
* modify it under the terms of the GNU Lesser General Public
|
8 |
* License as published by the Free Software Foundation; either
|
9 |
* version 2 of the License, or (at your option) any later version.
|
10 |
*
|
11 |
* This library is distributed in the hope that it will be useful,
|
12 |
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
13 |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
14 |
* Lesser General Public License for more details.
|
15 |
*
|
16 |
* You should have received a copy of the GNU Lesser General Public
|
17 |
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
|
18 |
*/
|
19 |
|
20 |
/*
|
21 |
* For now, this code can emulate flashes of 1, 2 or 4 bytes width.
|
22 |
* Supported commands/modes are:
|
23 |
* - flash read
|
24 |
* - flash write
|
25 |
* - flash ID read
|
26 |
* - sector erase
|
27 |
* - chip erase
|
28 |
* - unlock bypass command
|
29 |
* - CFI queries
|
30 |
*
|
31 |
* It does not support flash interleaving.
|
32 |
* It does not implement boot blocs with reduced size
|
33 |
* It does not implement software data protection as found in many real chips
|
34 |
* It does not implement erase suspend/resume commands
|
35 |
* It does not implement multiple sectors erase
|
36 |
*/
|
37 |
|
38 |
#include "hw.h" |
39 |
#include "flash.h" |
40 |
#include "qemu-timer.h" |
41 |
#include "block/block.h" |
42 |
#include "exec-memory.h" |
43 |
#include "host-utils.h" |
44 |
#include "sysbus.h" |
45 |
|
46 |
//#define PFLASH_DEBUG
|
47 |
#ifdef PFLASH_DEBUG
|
48 |
#define DPRINTF(fmt, ...) \
|
49 |
do { \
|
50 |
printf("PFLASH: " fmt , ## __VA_ARGS__); \ |
51 |
} while (0) |
52 |
#else
|
53 |
#define DPRINTF(fmt, ...) do { } while (0) |
54 |
#endif
|
55 |
|
56 |
#define PFLASH_LAZY_ROMD_THRESHOLD 42 |
57 |
|
58 |
struct pflash_t {
|
59 |
SysBusDevice busdev; |
60 |
BlockDriverState *bs; |
61 |
uint32_t sector_len; |
62 |
uint32_t nb_blocs; |
63 |
uint32_t chip_len; |
64 |
uint8_t mappings; |
65 |
uint8_t width; |
66 |
uint8_t be; |
67 |
int wcycle; /* if 0, the flash is read normally */ |
68 |
int bypass;
|
69 |
int ro;
|
70 |
uint8_t cmd; |
71 |
uint8_t status; |
72 |
/* FIXME: implement array device properties */
|
73 |
uint16_t ident0; |
74 |
uint16_t ident1; |
75 |
uint16_t ident2; |
76 |
uint16_t ident3; |
77 |
uint16_t unlock_addr0; |
78 |
uint16_t unlock_addr1; |
79 |
uint8_t cfi_len; |
80 |
uint8_t cfi_table[0x52];
|
81 |
QEMUTimer *timer; |
82 |
/* The device replicates the flash memory across its memory space. Emulate
|
83 |
* that by having a container (.mem) filled with an array of aliases
|
84 |
* (.mem_mappings) pointing to the flash memory (.orig_mem).
|
85 |
*/
|
86 |
MemoryRegion mem; |
87 |
MemoryRegion *mem_mappings; /* array; one per mapping */
|
88 |
MemoryRegion orig_mem; |
89 |
int rom_mode;
|
90 |
int read_counter; /* used for lazy switch-back to rom mode */ |
91 |
char *name;
|
92 |
void *storage;
|
93 |
}; |
94 |
|
95 |
/*
|
96 |
* Set up replicated mappings of the same region.
|
97 |
*/
|
98 |
static void pflash_setup_mappings(pflash_t *pfl) |
99 |
{ |
100 |
unsigned i;
|
101 |
hwaddr size = memory_region_size(&pfl->orig_mem); |
102 |
|
103 |
memory_region_init(&pfl->mem, "pflash", pfl->mappings * size);
|
104 |
pfl->mem_mappings = g_new(MemoryRegion, pfl->mappings); |
105 |
for (i = 0; i < pfl->mappings; ++i) { |
106 |
memory_region_init_alias(&pfl->mem_mappings[i], "pflash-alias",
|
107 |
&pfl->orig_mem, 0, size);
|
108 |
memory_region_add_subregion(&pfl->mem, i * size, &pfl->mem_mappings[i]); |
109 |
} |
110 |
} |
111 |
|
112 |
static void pflash_register_memory(pflash_t *pfl, int rom_mode) |
113 |
{ |
114 |
memory_region_rom_device_set_readable(&pfl->orig_mem, rom_mode); |
115 |
pfl->rom_mode = rom_mode; |
116 |
} |
117 |
|
118 |
static void pflash_timer (void *opaque) |
119 |
{ |
120 |
pflash_t *pfl = opaque; |
121 |
|
122 |
DPRINTF("%s: command %02x done\n", __func__, pfl->cmd);
|
123 |
/* Reset flash */
|
124 |
pfl->status ^= 0x80;
|
125 |
if (pfl->bypass) {
|
126 |
pfl->wcycle = 2;
|
127 |
} else {
|
128 |
pflash_register_memory(pfl, 1);
|
129 |
pfl->wcycle = 0;
|
130 |
} |
131 |
pfl->cmd = 0;
|
132 |
} |
133 |
|
134 |
static uint32_t pflash_read (pflash_t *pfl, hwaddr offset,
|
135 |
int width, int be) |
136 |
{ |
137 |
hwaddr boff; |
138 |
uint32_t ret; |
139 |
uint8_t *p; |
140 |
|
141 |
DPRINTF("%s: offset " TARGET_FMT_plx "\n", __func__, offset); |
142 |
ret = -1;
|
143 |
/* Lazy reset to ROMD mode after a certain amount of read accesses */
|
144 |
if (!pfl->rom_mode && pfl->wcycle == 0 && |
145 |
++pfl->read_counter > PFLASH_LAZY_ROMD_THRESHOLD) { |
146 |
pflash_register_memory(pfl, 1);
|
147 |
} |
148 |
offset &= pfl->chip_len - 1;
|
149 |
boff = offset & 0xFF;
|
150 |
if (pfl->width == 2) |
151 |
boff = boff >> 1;
|
152 |
else if (pfl->width == 4) |
153 |
boff = boff >> 2;
|
154 |
switch (pfl->cmd) {
|
155 |
default:
|
156 |
/* This should never happen : reset state & treat it as a read*/
|
157 |
DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd);
|
158 |
pfl->wcycle = 0;
|
159 |
pfl->cmd = 0;
|
160 |
case 0x80: |
161 |
/* We accept reads during second unlock sequence... */
|
162 |
case 0x00: |
163 |
flash_read:
|
164 |
/* Flash area read */
|
165 |
p = pfl->storage; |
166 |
switch (width) {
|
167 |
case 1: |
168 |
ret = p[offset]; |
169 |
// DPRINTF("%s: data offset %08x %02x\n", __func__, offset, ret);
|
170 |
break;
|
171 |
case 2: |
172 |
if (be) {
|
173 |
ret = p[offset] << 8;
|
174 |
ret |= p[offset + 1];
|
175 |
} else {
|
176 |
ret = p[offset]; |
177 |
ret |= p[offset + 1] << 8; |
178 |
} |
179 |
// DPRINTF("%s: data offset %08x %04x\n", __func__, offset, ret);
|
180 |
break;
|
181 |
case 4: |
182 |
if (be) {
|
183 |
ret = p[offset] << 24;
|
184 |
ret |= p[offset + 1] << 16; |
185 |
ret |= p[offset + 2] << 8; |
186 |
ret |= p[offset + 3];
|
187 |
} else {
|
188 |
ret = p[offset]; |
189 |
ret |= p[offset + 1] << 8; |
190 |
ret |= p[offset + 2] << 16; |
191 |
ret |= p[offset + 3] << 24; |
192 |
} |
193 |
// DPRINTF("%s: data offset %08x %08x\n", __func__, offset, ret);
|
194 |
break;
|
195 |
} |
196 |
break;
|
197 |
case 0x90: |
198 |
/* flash ID read */
|
199 |
switch (boff) {
|
200 |
case 0x00: |
201 |
case 0x01: |
202 |
ret = boff & 0x01 ? pfl->ident1 : pfl->ident0;
|
203 |
break;
|
204 |
case 0x02: |
205 |
ret = 0x00; /* Pretend all sectors are unprotected */ |
206 |
break;
|
207 |
case 0x0E: |
208 |
case 0x0F: |
209 |
ret = boff & 0x01 ? pfl->ident3 : pfl->ident2;
|
210 |
if (ret == (uint8_t)-1) { |
211 |
goto flash_read;
|
212 |
} |
213 |
break;
|
214 |
default:
|
215 |
goto flash_read;
|
216 |
} |
217 |
DPRINTF("%s: ID " TARGET_FMT_plx " %x\n", __func__, boff, ret); |
218 |
break;
|
219 |
case 0xA0: |
220 |
case 0x10: |
221 |
case 0x30: |
222 |
/* Status register read */
|
223 |
ret = pfl->status; |
224 |
DPRINTF("%s: status %x\n", __func__, ret);
|
225 |
/* Toggle bit 6 */
|
226 |
pfl->status ^= 0x40;
|
227 |
break;
|
228 |
case 0x98: |
229 |
/* CFI query mode */
|
230 |
if (boff > pfl->cfi_len)
|
231 |
ret = 0;
|
232 |
else
|
233 |
ret = pfl->cfi_table[boff]; |
234 |
break;
|
235 |
} |
236 |
|
237 |
return ret;
|
238 |
} |
239 |
|
240 |
/* update flash content on disk */
|
241 |
static void pflash_update(pflash_t *pfl, int offset, |
242 |
int size)
|
243 |
{ |
244 |
int offset_end;
|
245 |
if (pfl->bs) {
|
246 |
offset_end = offset + size; |
247 |
/* round to sectors */
|
248 |
offset = offset >> 9;
|
249 |
offset_end = (offset_end + 511) >> 9; |
250 |
bdrv_write(pfl->bs, offset, pfl->storage + (offset << 9),
|
251 |
offset_end - offset); |
252 |
} |
253 |
} |
254 |
|
255 |
static void pflash_write (pflash_t *pfl, hwaddr offset, |
256 |
uint32_t value, int width, int be) |
257 |
{ |
258 |
hwaddr boff; |
259 |
uint8_t *p; |
260 |
uint8_t cmd; |
261 |
|
262 |
cmd = value; |
263 |
if (pfl->cmd != 0xA0 && cmd == 0xF0) { |
264 |
#if 0
|
265 |
DPRINTF("%s: flash reset asked (%02x %02x)\n",
|
266 |
__func__, pfl->cmd, cmd);
|
267 |
#endif
|
268 |
goto reset_flash;
|
269 |
} |
270 |
DPRINTF("%s: offset " TARGET_FMT_plx " %08x %d %d\n", __func__, |
271 |
offset, value, width, pfl->wcycle); |
272 |
offset &= pfl->chip_len - 1;
|
273 |
|
274 |
DPRINTF("%s: offset " TARGET_FMT_plx " %08x %d\n", __func__, |
275 |
offset, value, width); |
276 |
boff = offset & (pfl->sector_len - 1);
|
277 |
if (pfl->width == 2) |
278 |
boff = boff >> 1;
|
279 |
else if (pfl->width == 4) |
280 |
boff = boff >> 2;
|
281 |
switch (pfl->wcycle) {
|
282 |
case 0: |
283 |
/* Set the device in I/O access mode if required */
|
284 |
if (pfl->rom_mode)
|
285 |
pflash_register_memory(pfl, 0);
|
286 |
pfl->read_counter = 0;
|
287 |
/* We're in read mode */
|
288 |
check_unlock0:
|
289 |
if (boff == 0x55 && cmd == 0x98) { |
290 |
enter_CFI_mode:
|
291 |
/* Enter CFI query mode */
|
292 |
pfl->wcycle = 7;
|
293 |
pfl->cmd = 0x98;
|
294 |
return;
|
295 |
} |
296 |
if (boff != pfl->unlock_addr0 || cmd != 0xAA) { |
297 |
DPRINTF("%s: unlock0 failed " TARGET_FMT_plx " %02x %04x\n", |
298 |
__func__, boff, cmd, pfl->unlock_addr0); |
299 |
goto reset_flash;
|
300 |
} |
301 |
DPRINTF("%s: unlock sequence started\n", __func__);
|
302 |
break;
|
303 |
case 1: |
304 |
/* We started an unlock sequence */
|
305 |
check_unlock1:
|
306 |
if (boff != pfl->unlock_addr1 || cmd != 0x55) { |
307 |
DPRINTF("%s: unlock1 failed " TARGET_FMT_plx " %02x\n", __func__, |
308 |
boff, cmd); |
309 |
goto reset_flash;
|
310 |
} |
311 |
DPRINTF("%s: unlock sequence done\n", __func__);
|
312 |
break;
|
313 |
case 2: |
314 |
/* We finished an unlock sequence */
|
315 |
if (!pfl->bypass && boff != pfl->unlock_addr0) {
|
316 |
DPRINTF("%s: command failed " TARGET_FMT_plx " %02x\n", __func__, |
317 |
boff, cmd); |
318 |
goto reset_flash;
|
319 |
} |
320 |
switch (cmd) {
|
321 |
case 0x20: |
322 |
pfl->bypass = 1;
|
323 |
goto do_bypass;
|
324 |
case 0x80: |
325 |
case 0x90: |
326 |
case 0xA0: |
327 |
pfl->cmd = cmd; |
328 |
DPRINTF("%s: starting command %02x\n", __func__, cmd);
|
329 |
break;
|
330 |
default:
|
331 |
DPRINTF("%s: unknown command %02x\n", __func__, cmd);
|
332 |
goto reset_flash;
|
333 |
} |
334 |
break;
|
335 |
case 3: |
336 |
switch (pfl->cmd) {
|
337 |
case 0x80: |
338 |
/* We need another unlock sequence */
|
339 |
goto check_unlock0;
|
340 |
case 0xA0: |
341 |
DPRINTF("%s: write data offset " TARGET_FMT_plx " %08x %d\n", |
342 |
__func__, offset, value, width); |
343 |
p = pfl->storage; |
344 |
if (!pfl->ro) {
|
345 |
switch (width) {
|
346 |
case 1: |
347 |
p[offset] &= value; |
348 |
pflash_update(pfl, offset, 1);
|
349 |
break;
|
350 |
case 2: |
351 |
if (be) {
|
352 |
p[offset] &= value >> 8;
|
353 |
p[offset + 1] &= value;
|
354 |
} else {
|
355 |
p[offset] &= value; |
356 |
p[offset + 1] &= value >> 8; |
357 |
} |
358 |
pflash_update(pfl, offset, 2);
|
359 |
break;
|
360 |
case 4: |
361 |
if (be) {
|
362 |
p[offset] &= value >> 24;
|
363 |
p[offset + 1] &= value >> 16; |
364 |
p[offset + 2] &= value >> 8; |
365 |
p[offset + 3] &= value;
|
366 |
} else {
|
367 |
p[offset] &= value; |
368 |
p[offset + 1] &= value >> 8; |
369 |
p[offset + 2] &= value >> 16; |
370 |
p[offset + 3] &= value >> 24; |
371 |
} |
372 |
pflash_update(pfl, offset, 4);
|
373 |
break;
|
374 |
} |
375 |
} |
376 |
pfl->status = 0x00 | ~(value & 0x80); |
377 |
/* Let's pretend write is immediate */
|
378 |
if (pfl->bypass)
|
379 |
goto do_bypass;
|
380 |
goto reset_flash;
|
381 |
case 0x90: |
382 |
if (pfl->bypass && cmd == 0x00) { |
383 |
/* Unlock bypass reset */
|
384 |
goto reset_flash;
|
385 |
} |
386 |
/* We can enter CFI query mode from autoselect mode */
|
387 |
if (boff == 0x55 && cmd == 0x98) |
388 |
goto enter_CFI_mode;
|
389 |
/* No break here */
|
390 |
default:
|
391 |
DPRINTF("%s: invalid write for command %02x\n",
|
392 |
__func__, pfl->cmd); |
393 |
goto reset_flash;
|
394 |
} |
395 |
case 4: |
396 |
switch (pfl->cmd) {
|
397 |
case 0xA0: |
398 |
/* Ignore writes while flash data write is occurring */
|
399 |
/* As we suppose write is immediate, this should never happen */
|
400 |
return;
|
401 |
case 0x80: |
402 |
goto check_unlock1;
|
403 |
default:
|
404 |
/* Should never happen */
|
405 |
DPRINTF("%s: invalid command state %02x (wc 4)\n",
|
406 |
__func__, pfl->cmd); |
407 |
goto reset_flash;
|
408 |
} |
409 |
break;
|
410 |
case 5: |
411 |
switch (cmd) {
|
412 |
case 0x10: |
413 |
if (boff != pfl->unlock_addr0) {
|
414 |
DPRINTF("%s: chip erase: invalid address " TARGET_FMT_plx "\n", |
415 |
__func__, offset); |
416 |
goto reset_flash;
|
417 |
} |
418 |
/* Chip erase */
|
419 |
DPRINTF("%s: start chip erase\n", __func__);
|
420 |
if (!pfl->ro) {
|
421 |
memset(pfl->storage, 0xFF, pfl->chip_len);
|
422 |
pflash_update(pfl, 0, pfl->chip_len);
|
423 |
} |
424 |
pfl->status = 0x00;
|
425 |
/* Let's wait 5 seconds before chip erase is done */
|
426 |
qemu_mod_timer(pfl->timer, |
427 |
qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() * 5));
|
428 |
break;
|
429 |
case 0x30: |
430 |
/* Sector erase */
|
431 |
p = pfl->storage; |
432 |
offset &= ~(pfl->sector_len - 1);
|
433 |
DPRINTF("%s: start sector erase at " TARGET_FMT_plx "\n", __func__, |
434 |
offset); |
435 |
if (!pfl->ro) {
|
436 |
memset(p + offset, 0xFF, pfl->sector_len);
|
437 |
pflash_update(pfl, offset, pfl->sector_len); |
438 |
} |
439 |
pfl->status = 0x00;
|
440 |
/* Let's wait 1/2 second before sector erase is done */
|
441 |
qemu_mod_timer(pfl->timer, |
442 |
qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() / 2));
|
443 |
break;
|
444 |
default:
|
445 |
DPRINTF("%s: invalid command %02x (wc 5)\n", __func__, cmd);
|
446 |
goto reset_flash;
|
447 |
} |
448 |
pfl->cmd = cmd; |
449 |
break;
|
450 |
case 6: |
451 |
switch (pfl->cmd) {
|
452 |
case 0x10: |
453 |
/* Ignore writes during chip erase */
|
454 |
return;
|
455 |
case 0x30: |
456 |
/* Ignore writes during sector erase */
|
457 |
return;
|
458 |
default:
|
459 |
/* Should never happen */
|
460 |
DPRINTF("%s: invalid command state %02x (wc 6)\n",
|
461 |
__func__, pfl->cmd); |
462 |
goto reset_flash;
|
463 |
} |
464 |
break;
|
465 |
case 7: /* Special value for CFI queries */ |
466 |
DPRINTF("%s: invalid write in CFI query mode\n", __func__);
|
467 |
goto reset_flash;
|
468 |
default:
|
469 |
/* Should never happen */
|
470 |
DPRINTF("%s: invalid write state (wc 7)\n", __func__);
|
471 |
goto reset_flash;
|
472 |
} |
473 |
pfl->wcycle++; |
474 |
|
475 |
return;
|
476 |
|
477 |
/* Reset flash */
|
478 |
reset_flash:
|
479 |
pfl->bypass = 0;
|
480 |
pfl->wcycle = 0;
|
481 |
pfl->cmd = 0;
|
482 |
return;
|
483 |
|
484 |
do_bypass:
|
485 |
pfl->wcycle = 2;
|
486 |
pfl->cmd = 0;
|
487 |
} |
488 |
|
489 |
|
490 |
static uint32_t pflash_readb_be(void *opaque, hwaddr addr) |
491 |
{ |
492 |
return pflash_read(opaque, addr, 1, 1); |
493 |
} |
494 |
|
495 |
static uint32_t pflash_readb_le(void *opaque, hwaddr addr) |
496 |
{ |
497 |
return pflash_read(opaque, addr, 1, 0); |
498 |
} |
499 |
|
500 |
static uint32_t pflash_readw_be(void *opaque, hwaddr addr) |
501 |
{ |
502 |
pflash_t *pfl = opaque; |
503 |
|
504 |
return pflash_read(pfl, addr, 2, 1); |
505 |
} |
506 |
|
507 |
static uint32_t pflash_readw_le(void *opaque, hwaddr addr) |
508 |
{ |
509 |
pflash_t *pfl = opaque; |
510 |
|
511 |
return pflash_read(pfl, addr, 2, 0); |
512 |
} |
513 |
|
514 |
static uint32_t pflash_readl_be(void *opaque, hwaddr addr) |
515 |
{ |
516 |
pflash_t *pfl = opaque; |
517 |
|
518 |
return pflash_read(pfl, addr, 4, 1); |
519 |
} |
520 |
|
521 |
static uint32_t pflash_readl_le(void *opaque, hwaddr addr) |
522 |
{ |
523 |
pflash_t *pfl = opaque; |
524 |
|
525 |
return pflash_read(pfl, addr, 4, 0); |
526 |
} |
527 |
|
528 |
static void pflash_writeb_be(void *opaque, hwaddr addr, |
529 |
uint32_t value) |
530 |
{ |
531 |
pflash_write(opaque, addr, value, 1, 1); |
532 |
} |
533 |
|
534 |
static void pflash_writeb_le(void *opaque, hwaddr addr, |
535 |
uint32_t value) |
536 |
{ |
537 |
pflash_write(opaque, addr, value, 1, 0); |
538 |
} |
539 |
|
540 |
static void pflash_writew_be(void *opaque, hwaddr addr, |
541 |
uint32_t value) |
542 |
{ |
543 |
pflash_t *pfl = opaque; |
544 |
|
545 |
pflash_write(pfl, addr, value, 2, 1); |
546 |
} |
547 |
|
548 |
static void pflash_writew_le(void *opaque, hwaddr addr, |
549 |
uint32_t value) |
550 |
{ |
551 |
pflash_t *pfl = opaque; |
552 |
|
553 |
pflash_write(pfl, addr, value, 2, 0); |
554 |
} |
555 |
|
556 |
static void pflash_writel_be(void *opaque, hwaddr addr, |
557 |
uint32_t value) |
558 |
{ |
559 |
pflash_t *pfl = opaque; |
560 |
|
561 |
pflash_write(pfl, addr, value, 4, 1); |
562 |
} |
563 |
|
564 |
static void pflash_writel_le(void *opaque, hwaddr addr, |
565 |
uint32_t value) |
566 |
{ |
567 |
pflash_t *pfl = opaque; |
568 |
|
569 |
pflash_write(pfl, addr, value, 4, 0); |
570 |
} |
571 |
|
572 |
static const MemoryRegionOps pflash_cfi02_ops_be = { |
573 |
.old_mmio = { |
574 |
.read = { pflash_readb_be, pflash_readw_be, pflash_readl_be, }, |
575 |
.write = { pflash_writeb_be, pflash_writew_be, pflash_writel_be, }, |
576 |
}, |
577 |
.endianness = DEVICE_NATIVE_ENDIAN, |
578 |
}; |
579 |
|
580 |
static const MemoryRegionOps pflash_cfi02_ops_le = { |
581 |
.old_mmio = { |
582 |
.read = { pflash_readb_le, pflash_readw_le, pflash_readl_le, }, |
583 |
.write = { pflash_writeb_le, pflash_writew_le, pflash_writel_le, }, |
584 |
}, |
585 |
.endianness = DEVICE_NATIVE_ENDIAN, |
586 |
}; |
587 |
|
588 |
static int pflash_cfi02_init(SysBusDevice *dev) |
589 |
{ |
590 |
pflash_t *pfl = FROM_SYSBUS(typeof(*pfl), dev); |
591 |
uint32_t chip_len; |
592 |
int ret;
|
593 |
|
594 |
chip_len = pfl->sector_len * pfl->nb_blocs; |
595 |
/* XXX: to be fixed */
|
596 |
#if 0
|
597 |
if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) &&
|
598 |
total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024))
|
599 |
return NULL;
|
600 |
#endif
|
601 |
|
602 |
memory_region_init_rom_device(&pfl->orig_mem, pfl->be ? |
603 |
&pflash_cfi02_ops_be : &pflash_cfi02_ops_le, |
604 |
pfl, pfl->name, chip_len); |
605 |
vmstate_register_ram(&pfl->orig_mem, DEVICE(pfl)); |
606 |
pfl->storage = memory_region_get_ram_ptr(&pfl->orig_mem); |
607 |
pfl->chip_len = chip_len; |
608 |
if (pfl->bs) {
|
609 |
/* read the initial flash content */
|
610 |
ret = bdrv_read(pfl->bs, 0, pfl->storage, chip_len >> 9); |
611 |
if (ret < 0) { |
612 |
g_free(pfl); |
613 |
return 1; |
614 |
} |
615 |
} |
616 |
|
617 |
pflash_setup_mappings(pfl); |
618 |
pfl->rom_mode = 1;
|
619 |
sysbus_init_mmio(dev, &pfl->mem); |
620 |
|
621 |
if (pfl->bs) {
|
622 |
pfl->ro = bdrv_is_read_only(pfl->bs); |
623 |
} else {
|
624 |
pfl->ro = 0;
|
625 |
} |
626 |
|
627 |
pfl->timer = qemu_new_timer_ns(vm_clock, pflash_timer, pfl); |
628 |
pfl->wcycle = 0;
|
629 |
pfl->cmd = 0;
|
630 |
pfl->status = 0;
|
631 |
/* Hardcoded CFI table (mostly from SG29 Spansion flash) */
|
632 |
pfl->cfi_len = 0x52;
|
633 |
/* Standard "QRY" string */
|
634 |
pfl->cfi_table[0x10] = 'Q'; |
635 |
pfl->cfi_table[0x11] = 'R'; |
636 |
pfl->cfi_table[0x12] = 'Y'; |
637 |
/* Command set (AMD/Fujitsu) */
|
638 |
pfl->cfi_table[0x13] = 0x02; |
639 |
pfl->cfi_table[0x14] = 0x00; |
640 |
/* Primary extended table address */
|
641 |
pfl->cfi_table[0x15] = 0x31; |
642 |
pfl->cfi_table[0x16] = 0x00; |
643 |
/* Alternate command set (none) */
|
644 |
pfl->cfi_table[0x17] = 0x00; |
645 |
pfl->cfi_table[0x18] = 0x00; |
646 |
/* Alternate extended table (none) */
|
647 |
pfl->cfi_table[0x19] = 0x00; |
648 |
pfl->cfi_table[0x1A] = 0x00; |
649 |
/* Vcc min */
|
650 |
pfl->cfi_table[0x1B] = 0x27; |
651 |
/* Vcc max */
|
652 |
pfl->cfi_table[0x1C] = 0x36; |
653 |
/* Vpp min (no Vpp pin) */
|
654 |
pfl->cfi_table[0x1D] = 0x00; |
655 |
/* Vpp max (no Vpp pin) */
|
656 |
pfl->cfi_table[0x1E] = 0x00; |
657 |
/* Reserved */
|
658 |
pfl->cfi_table[0x1F] = 0x07; |
659 |
/* Timeout for min size buffer write (NA) */
|
660 |
pfl->cfi_table[0x20] = 0x00; |
661 |
/* Typical timeout for block erase (512 ms) */
|
662 |
pfl->cfi_table[0x21] = 0x09; |
663 |
/* Typical timeout for full chip erase (4096 ms) */
|
664 |
pfl->cfi_table[0x22] = 0x0C; |
665 |
/* Reserved */
|
666 |
pfl->cfi_table[0x23] = 0x01; |
667 |
/* Max timeout for buffer write (NA) */
|
668 |
pfl->cfi_table[0x24] = 0x00; |
669 |
/* Max timeout for block erase */
|
670 |
pfl->cfi_table[0x25] = 0x0A; |
671 |
/* Max timeout for chip erase */
|
672 |
pfl->cfi_table[0x26] = 0x0D; |
673 |
/* Device size */
|
674 |
pfl->cfi_table[0x27] = ctz32(chip_len);
|
675 |
/* Flash device interface (8 & 16 bits) */
|
676 |
pfl->cfi_table[0x28] = 0x02; |
677 |
pfl->cfi_table[0x29] = 0x00; |
678 |
/* Max number of bytes in multi-bytes write */
|
679 |
/* XXX: disable buffered write as it's not supported */
|
680 |
// pfl->cfi_table[0x2A] = 0x05;
|
681 |
pfl->cfi_table[0x2A] = 0x00; |
682 |
pfl->cfi_table[0x2B] = 0x00; |
683 |
/* Number of erase block regions (uniform) */
|
684 |
pfl->cfi_table[0x2C] = 0x01; |
685 |
/* Erase block region 1 */
|
686 |
pfl->cfi_table[0x2D] = pfl->nb_blocs - 1; |
687 |
pfl->cfi_table[0x2E] = (pfl->nb_blocs - 1) >> 8; |
688 |
pfl->cfi_table[0x2F] = pfl->sector_len >> 8; |
689 |
pfl->cfi_table[0x30] = pfl->sector_len >> 16; |
690 |
|
691 |
/* Extended */
|
692 |
pfl->cfi_table[0x31] = 'P'; |
693 |
pfl->cfi_table[0x32] = 'R'; |
694 |
pfl->cfi_table[0x33] = 'I'; |
695 |
|
696 |
pfl->cfi_table[0x34] = '1'; |
697 |
pfl->cfi_table[0x35] = '0'; |
698 |
|
699 |
pfl->cfi_table[0x36] = 0x00; |
700 |
pfl->cfi_table[0x37] = 0x00; |
701 |
pfl->cfi_table[0x38] = 0x00; |
702 |
pfl->cfi_table[0x39] = 0x00; |
703 |
|
704 |
pfl->cfi_table[0x3a] = 0x00; |
705 |
|
706 |
pfl->cfi_table[0x3b] = 0x00; |
707 |
pfl->cfi_table[0x3c] = 0x00; |
708 |
|
709 |
return 0; |
710 |
} |
711 |
|
712 |
static Property pflash_cfi02_properties[] = {
|
713 |
DEFINE_PROP_DRIVE("drive", struct pflash_t, bs), |
714 |
DEFINE_PROP_UINT32("num-blocks", struct pflash_t, nb_blocs, 0), |
715 |
DEFINE_PROP_UINT32("sector-length", struct pflash_t, sector_len, 0), |
716 |
DEFINE_PROP_UINT8("width", struct pflash_t, width, 0), |
717 |
DEFINE_PROP_UINT8("mappings", struct pflash_t, mappings, 0), |
718 |
DEFINE_PROP_UINT8("big-endian", struct pflash_t, be, 0), |
719 |
DEFINE_PROP_UINT16("id0", struct pflash_t, ident0, 0), |
720 |
DEFINE_PROP_UINT16("id1", struct pflash_t, ident1, 0), |
721 |
DEFINE_PROP_UINT16("id2", struct pflash_t, ident2, 0), |
722 |
DEFINE_PROP_UINT16("id3", struct pflash_t, ident3, 0), |
723 |
DEFINE_PROP_UINT16("unlock-addr0", struct pflash_t, unlock_addr0, 0), |
724 |
DEFINE_PROP_UINT16("unlock-addr1", struct pflash_t, unlock_addr1, 0), |
725 |
DEFINE_PROP_STRING("name", struct pflash_t, name), |
726 |
DEFINE_PROP_END_OF_LIST(), |
727 |
}; |
728 |
|
729 |
static void pflash_cfi02_class_init(ObjectClass *klass, void *data) |
730 |
{ |
731 |
DeviceClass *dc = DEVICE_CLASS(klass); |
732 |
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
733 |
|
734 |
k->init = pflash_cfi02_init; |
735 |
dc->props = pflash_cfi02_properties; |
736 |
} |
737 |
|
738 |
static const TypeInfo pflash_cfi02_info = { |
739 |
.name = "cfi.pflash02",
|
740 |
.parent = TYPE_SYS_BUS_DEVICE, |
741 |
.instance_size = sizeof(struct pflash_t), |
742 |
.class_init = pflash_cfi02_class_init, |
743 |
}; |
744 |
|
745 |
static void pflash_cfi02_register_types(void) |
746 |
{ |
747 |
type_register_static(&pflash_cfi02_info); |
748 |
} |
749 |
|
750 |
type_init(pflash_cfi02_register_types) |
751 |
|
752 |
pflash_t *pflash_cfi02_register(hwaddr base, |
753 |
DeviceState *qdev, const char *name, |
754 |
hwaddr size, |
755 |
BlockDriverState *bs, uint32_t sector_len, |
756 |
int nb_blocs, int nb_mappings, int width, |
757 |
uint16_t id0, uint16_t id1, |
758 |
uint16_t id2, uint16_t id3, |
759 |
uint16_t unlock_addr0, uint16_t unlock_addr1, |
760 |
int be)
|
761 |
{ |
762 |
DeviceState *dev = qdev_create(NULL, "cfi.pflash02"); |
763 |
SysBusDevice *busdev = sysbus_from_qdev(dev); |
764 |
pflash_t *pfl = (pflash_t *)object_dynamic_cast(OBJECT(dev), |
765 |
"cfi.pflash02");
|
766 |
|
767 |
if (bs && qdev_prop_set_drive(dev, "drive", bs)) { |
768 |
abort(); |
769 |
} |
770 |
qdev_prop_set_uint32(dev, "num-blocks", nb_blocs);
|
771 |
qdev_prop_set_uint32(dev, "sector-length", sector_len);
|
772 |
qdev_prop_set_uint8(dev, "width", width);
|
773 |
qdev_prop_set_uint8(dev, "mappings", nb_mappings);
|
774 |
qdev_prop_set_uint8(dev, "big-endian", !!be);
|
775 |
qdev_prop_set_uint16(dev, "id0", id0);
|
776 |
qdev_prop_set_uint16(dev, "id1", id1);
|
777 |
qdev_prop_set_uint16(dev, "id2", id2);
|
778 |
qdev_prop_set_uint16(dev, "id3", id3);
|
779 |
qdev_prop_set_uint16(dev, "unlock-addr0", unlock_addr0);
|
780 |
qdev_prop_set_uint16(dev, "unlock-addr1", unlock_addr1);
|
781 |
qdev_prop_set_string(dev, "name", name);
|
782 |
qdev_init_nofail(dev); |
783 |
|
784 |
sysbus_mmio_map(busdev, 0, base);
|
785 |
return pfl;
|
786 |
} |