Revision 7385ac0b target-mips/translate.c
| b/target-mips/translate.c | ||
|---|---|---|
| 749 | 749 |
generate_exception(ctx, EXCP_RI); |
| 750 | 750 |
} |
| 751 | 751 |
|
| 752 |
static always_inline void check_cp1_3d(CPUState *env, DisasContext *ctx) |
|
| 753 |
{
|
|
| 754 |
if (unlikely(!(env->fpu->fcr0 & (1 << FCR0_3D)))) |
|
| 755 |
generate_exception(ctx, EXCP_RI); |
|
| 756 |
} |
|
| 757 |
|
|
| 758 | 752 |
/* |
| 759 | 753 |
* Verify if floating point register is valid; an operation is not defined |
| 760 | 754 |
* if bit 0 of any register specification is set and the FR bit in the |
| ... | ... | |
| 780 | 774 |
generate_exception(ctx, EXCP_RI); |
| 781 | 775 |
} |
| 782 | 776 |
|
| 783 |
/* This code generates a "reserved instruction" exception if the |
|
| 784 |
CPU is not MIPS MT capable. */ |
|
| 785 |
static always_inline void check_mips_mt(CPUState *env, DisasContext *ctx) |
|
| 786 |
{
|
|
| 787 |
if (unlikely(!(env->CP0_Config3 & (1 << CP0C3_MT)))) |
|
| 788 |
generate_exception(ctx, EXCP_RI); |
|
| 789 |
} |
|
| 790 |
|
|
| 791 | 777 |
/* This code generates a "reserved instruction" exception if 64-bit |
| 792 | 778 |
instructions are not enabled. */ |
| 793 | 779 |
static always_inline void check_mips_64(DisasContext *ctx) |
| ... | ... | |
| 1971 | 1957 |
rn = "Index"; |
| 1972 | 1958 |
break; |
| 1973 | 1959 |
case 1: |
| 1974 |
check_mips_mt(env, ctx);
|
|
| 1960 |
check_insn(env, ctx, ASE_MT);
|
|
| 1975 | 1961 |
gen_op_mfc0_mvpcontrol(); |
| 1976 | 1962 |
rn = "MVPControl"; |
| 1977 | 1963 |
break; |
| 1978 | 1964 |
case 2: |
| 1979 |
check_mips_mt(env, ctx);
|
|
| 1965 |
check_insn(env, ctx, ASE_MT);
|
|
| 1980 | 1966 |
gen_op_mfc0_mvpconf0(); |
| 1981 | 1967 |
rn = "MVPConf0"; |
| 1982 | 1968 |
break; |
| 1983 | 1969 |
case 3: |
| 1984 |
check_mips_mt(env, ctx);
|
|
| 1970 |
check_insn(env, ctx, ASE_MT);
|
|
| 1985 | 1971 |
gen_op_mfc0_mvpconf1(); |
| 1986 | 1972 |
rn = "MVPConf1"; |
| 1987 | 1973 |
break; |
| ... | ... | |
| 1996 | 1982 |
rn = "Random"; |
| 1997 | 1983 |
break; |
| 1998 | 1984 |
case 1: |
| 1999 |
check_mips_mt(env, ctx);
|
|
| 1985 |
check_insn(env, ctx, ASE_MT);
|
|
| 2000 | 1986 |
gen_op_mfc0_vpecontrol(); |
| 2001 | 1987 |
rn = "VPEControl"; |
| 2002 | 1988 |
break; |
| 2003 | 1989 |
case 2: |
| 2004 |
check_mips_mt(env, ctx);
|
|
| 1990 |
check_insn(env, ctx, ASE_MT);
|
|
| 2005 | 1991 |
gen_op_mfc0_vpeconf0(); |
| 2006 | 1992 |
rn = "VPEConf0"; |
| 2007 | 1993 |
break; |
| 2008 | 1994 |
case 3: |
| 2009 |
check_mips_mt(env, ctx);
|
|
| 1995 |
check_insn(env, ctx, ASE_MT);
|
|
| 2010 | 1996 |
gen_op_mfc0_vpeconf1(); |
| 2011 | 1997 |
rn = "VPEConf1"; |
| 2012 | 1998 |
break; |
| 2013 | 1999 |
case 4: |
| 2014 |
check_mips_mt(env, ctx);
|
|
| 2000 |
check_insn(env, ctx, ASE_MT);
|
|
| 2015 | 2001 |
gen_op_mfc0_yqmask(); |
| 2016 | 2002 |
rn = "YQMask"; |
| 2017 | 2003 |
break; |
| 2018 | 2004 |
case 5: |
| 2019 |
check_mips_mt(env, ctx);
|
|
| 2005 |
check_insn(env, ctx, ASE_MT);
|
|
| 2020 | 2006 |
gen_op_mfc0_vpeschedule(); |
| 2021 | 2007 |
rn = "VPESchedule"; |
| 2022 | 2008 |
break; |
| 2023 | 2009 |
case 6: |
| 2024 |
check_mips_mt(env, ctx);
|
|
| 2010 |
check_insn(env, ctx, ASE_MT);
|
|
| 2025 | 2011 |
gen_op_mfc0_vpeschefback(); |
| 2026 | 2012 |
rn = "VPEScheFBack"; |
| 2027 | 2013 |
break; |
| 2028 | 2014 |
case 7: |
| 2029 |
check_mips_mt(env, ctx);
|
|
| 2015 |
check_insn(env, ctx, ASE_MT);
|
|
| 2030 | 2016 |
gen_op_mfc0_vpeopt(); |
| 2031 | 2017 |
rn = "VPEOpt"; |
| 2032 | 2018 |
break; |
| ... | ... | |
| 2041 | 2027 |
rn = "EntryLo0"; |
| 2042 | 2028 |
break; |
| 2043 | 2029 |
case 1: |
| 2044 |
check_mips_mt(env, ctx);
|
|
| 2030 |
check_insn(env, ctx, ASE_MT);
|
|
| 2045 | 2031 |
gen_op_mfc0_tcstatus(); |
| 2046 | 2032 |
rn = "TCStatus"; |
| 2047 | 2033 |
break; |
| 2048 | 2034 |
case 2: |
| 2049 |
check_mips_mt(env, ctx);
|
|
| 2035 |
check_insn(env, ctx, ASE_MT);
|
|
| 2050 | 2036 |
gen_op_mfc0_tcbind(); |
| 2051 | 2037 |
rn = "TCBind"; |
| 2052 | 2038 |
break; |
| 2053 | 2039 |
case 3: |
| 2054 |
check_mips_mt(env, ctx);
|
|
| 2040 |
check_insn(env, ctx, ASE_MT);
|
|
| 2055 | 2041 |
gen_op_mfc0_tcrestart(); |
| 2056 | 2042 |
rn = "TCRestart"; |
| 2057 | 2043 |
break; |
| 2058 | 2044 |
case 4: |
| 2059 |
check_mips_mt(env, ctx);
|
|
| 2045 |
check_insn(env, ctx, ASE_MT);
|
|
| 2060 | 2046 |
gen_op_mfc0_tchalt(); |
| 2061 | 2047 |
rn = "TCHalt"; |
| 2062 | 2048 |
break; |
| 2063 | 2049 |
case 5: |
| 2064 |
check_mips_mt(env, ctx);
|
|
| 2050 |
check_insn(env, ctx, ASE_MT);
|
|
| 2065 | 2051 |
gen_op_mfc0_tccontext(); |
| 2066 | 2052 |
rn = "TCContext"; |
| 2067 | 2053 |
break; |
| 2068 | 2054 |
case 6: |
| 2069 |
check_mips_mt(env, ctx);
|
|
| 2055 |
check_insn(env, ctx, ASE_MT);
|
|
| 2070 | 2056 |
gen_op_mfc0_tcschedule(); |
| 2071 | 2057 |
rn = "TCSchedule"; |
| 2072 | 2058 |
break; |
| 2073 | 2059 |
case 7: |
| 2074 |
check_mips_mt(env, ctx);
|
|
| 2060 |
check_insn(env, ctx, ASE_MT);
|
|
| 2075 | 2061 |
gen_op_mfc0_tcschefback(); |
| 2076 | 2062 |
rn = "TCScheFBack"; |
| 2077 | 2063 |
break; |
| ... | ... | |
| 2539 | 2525 |
rn = "Index"; |
| 2540 | 2526 |
break; |
| 2541 | 2527 |
case 1: |
| 2542 |
check_mips_mt(env, ctx);
|
|
| 2528 |
check_insn(env, ctx, ASE_MT);
|
|
| 2543 | 2529 |
gen_op_mtc0_mvpcontrol(); |
| 2544 | 2530 |
rn = "MVPControl"; |
| 2545 | 2531 |
break; |
| 2546 | 2532 |
case 2: |
| 2547 |
check_mips_mt(env, ctx);
|
|
| 2533 |
check_insn(env, ctx, ASE_MT);
|
|
| 2548 | 2534 |
/* ignored */ |
| 2549 | 2535 |
rn = "MVPConf0"; |
| 2550 | 2536 |
break; |
| 2551 | 2537 |
case 3: |
| 2552 |
check_mips_mt(env, ctx);
|
|
| 2538 |
check_insn(env, ctx, ASE_MT);
|
|
| 2553 | 2539 |
/* ignored */ |
| 2554 | 2540 |
rn = "MVPConf1"; |
| 2555 | 2541 |
break; |
| ... | ... | |
| 2564 | 2550 |
rn = "Random"; |
| 2565 | 2551 |
break; |
| 2566 | 2552 |
case 1: |
| 2567 |
check_mips_mt(env, ctx);
|
|
| 2553 |
check_insn(env, ctx, ASE_MT);
|
|
| 2568 | 2554 |
gen_op_mtc0_vpecontrol(); |
| 2569 | 2555 |
rn = "VPEControl"; |
| 2570 | 2556 |
break; |
| 2571 | 2557 |
case 2: |
| 2572 |
check_mips_mt(env, ctx);
|
|
| 2558 |
check_insn(env, ctx, ASE_MT);
|
|
| 2573 | 2559 |
gen_op_mtc0_vpeconf0(); |
| 2574 | 2560 |
rn = "VPEConf0"; |
| 2575 | 2561 |
break; |
| 2576 | 2562 |
case 3: |
| 2577 |
check_mips_mt(env, ctx);
|
|
| 2563 |
check_insn(env, ctx, ASE_MT);
|
|
| 2578 | 2564 |
gen_op_mtc0_vpeconf1(); |
| 2579 | 2565 |
rn = "VPEConf1"; |
| 2580 | 2566 |
break; |
| 2581 | 2567 |
case 4: |
| 2582 |
check_mips_mt(env, ctx);
|
|
| 2568 |
check_insn(env, ctx, ASE_MT);
|
|
| 2583 | 2569 |
gen_op_mtc0_yqmask(); |
| 2584 | 2570 |
rn = "YQMask"; |
| 2585 | 2571 |
break; |
| 2586 | 2572 |
case 5: |
| 2587 |
check_mips_mt(env, ctx);
|
|
| 2573 |
check_insn(env, ctx, ASE_MT);
|
|
| 2588 | 2574 |
gen_op_mtc0_vpeschedule(); |
| 2589 | 2575 |
rn = "VPESchedule"; |
| 2590 | 2576 |
break; |
| 2591 | 2577 |
case 6: |
| 2592 |
check_mips_mt(env, ctx);
|
|
| 2578 |
check_insn(env, ctx, ASE_MT);
|
|
| 2593 | 2579 |
gen_op_mtc0_vpeschefback(); |
| 2594 | 2580 |
rn = "VPEScheFBack"; |
| 2595 | 2581 |
break; |
| 2596 | 2582 |
case 7: |
| 2597 |
check_mips_mt(env, ctx);
|
|
| 2583 |
check_insn(env, ctx, ASE_MT);
|
|
| 2598 | 2584 |
gen_op_mtc0_vpeopt(); |
| 2599 | 2585 |
rn = "VPEOpt"; |
| 2600 | 2586 |
break; |
| ... | ... | |
| 2609 | 2595 |
rn = "EntryLo0"; |
| 2610 | 2596 |
break; |
| 2611 | 2597 |
case 1: |
| 2612 |
check_mips_mt(env, ctx);
|
|
| 2598 |
check_insn(env, ctx, ASE_MT);
|
|
| 2613 | 2599 |
gen_op_mtc0_tcstatus(); |
| 2614 | 2600 |
rn = "TCStatus"; |
| 2615 | 2601 |
break; |
| 2616 | 2602 |
case 2: |
| 2617 |
check_mips_mt(env, ctx);
|
|
| 2603 |
check_insn(env, ctx, ASE_MT);
|
|
| 2618 | 2604 |
gen_op_mtc0_tcbind(); |
| 2619 | 2605 |
rn = "TCBind"; |
| 2620 | 2606 |
break; |
| 2621 | 2607 |
case 3: |
| 2622 |
check_mips_mt(env, ctx);
|
|
| 2608 |
check_insn(env, ctx, ASE_MT);
|
|
| 2623 | 2609 |
gen_op_mtc0_tcrestart(); |
| 2624 | 2610 |
rn = "TCRestart"; |
| 2625 | 2611 |
break; |
| 2626 | 2612 |
case 4: |
| 2627 |
check_mips_mt(env, ctx);
|
|
| 2613 |
check_insn(env, ctx, ASE_MT);
|
|
| 2628 | 2614 |
gen_op_mtc0_tchalt(); |
| 2629 | 2615 |
rn = "TCHalt"; |
| 2630 | 2616 |
break; |
| 2631 | 2617 |
case 5: |
| 2632 |
check_mips_mt(env, ctx);
|
|
| 2618 |
check_insn(env, ctx, ASE_MT);
|
|
| 2633 | 2619 |
gen_op_mtc0_tccontext(); |
| 2634 | 2620 |
rn = "TCContext"; |
| 2635 | 2621 |
break; |
| 2636 | 2622 |
case 6: |
| 2637 |
check_mips_mt(env, ctx);
|
|
| 2623 |
check_insn(env, ctx, ASE_MT);
|
|
| 2638 | 2624 |
gen_op_mtc0_tcschedule(); |
| 2639 | 2625 |
rn = "TCSchedule"; |
| 2640 | 2626 |
break; |
| 2641 | 2627 |
case 7: |
| 2642 |
check_mips_mt(env, ctx);
|
|
| 2628 |
check_insn(env, ctx, ASE_MT);
|
|
| 2643 | 2629 |
gen_op_mtc0_tcschefback(); |
| 2644 | 2630 |
rn = "TCScheFBack"; |
| 2645 | 2631 |
break; |
| ... | ... | |
| 3139 | 3125 |
rn = "Index"; |
| 3140 | 3126 |
break; |
| 3141 | 3127 |
case 1: |
| 3142 |
check_mips_mt(env, ctx);
|
|
| 3128 |
check_insn(env, ctx, ASE_MT);
|
|
| 3143 | 3129 |
gen_op_mfc0_mvpcontrol(); |
| 3144 | 3130 |
rn = "MVPControl"; |
| 3145 | 3131 |
break; |
| 3146 | 3132 |
case 2: |
| 3147 |
check_mips_mt(env, ctx);
|
|
| 3133 |
check_insn(env, ctx, ASE_MT);
|
|
| 3148 | 3134 |
gen_op_mfc0_mvpconf0(); |
| 3149 | 3135 |
rn = "MVPConf0"; |
| 3150 | 3136 |
break; |
| 3151 | 3137 |
case 3: |
| 3152 |
check_mips_mt(env, ctx);
|
|
| 3138 |
check_insn(env, ctx, ASE_MT);
|
|
| 3153 | 3139 |
gen_op_mfc0_mvpconf1(); |
| 3154 | 3140 |
rn = "MVPConf1"; |
| 3155 | 3141 |
break; |
| ... | ... | |
| 3164 | 3150 |
rn = "Random"; |
| 3165 | 3151 |
break; |
| 3166 | 3152 |
case 1: |
| 3167 |
check_mips_mt(env, ctx);
|
|
| 3153 |
check_insn(env, ctx, ASE_MT);
|
|
| 3168 | 3154 |
gen_op_mfc0_vpecontrol(); |
| 3169 | 3155 |
rn = "VPEControl"; |
| 3170 | 3156 |
break; |
| 3171 | 3157 |
case 2: |
| 3172 |
check_mips_mt(env, ctx);
|
|
| 3158 |
check_insn(env, ctx, ASE_MT);
|
|
| 3173 | 3159 |
gen_op_mfc0_vpeconf0(); |
| 3174 | 3160 |
rn = "VPEConf0"; |
| 3175 | 3161 |
break; |
| 3176 | 3162 |
case 3: |
| 3177 |
check_mips_mt(env, ctx);
|
|
| 3163 |
check_insn(env, ctx, ASE_MT);
|
|
| 3178 | 3164 |
gen_op_mfc0_vpeconf1(); |
| 3179 | 3165 |
rn = "VPEConf1"; |
| 3180 | 3166 |
break; |
| 3181 | 3167 |
case 4: |
| 3182 |
check_mips_mt(env, ctx);
|
|
| 3168 |
check_insn(env, ctx, ASE_MT);
|
|
| 3183 | 3169 |
gen_op_dmfc0_yqmask(); |
| 3184 | 3170 |
rn = "YQMask"; |
| 3185 | 3171 |
break; |
| 3186 | 3172 |
case 5: |
| 3187 |
check_mips_mt(env, ctx);
|
|
| 3173 |
check_insn(env, ctx, ASE_MT);
|
|
| 3188 | 3174 |
gen_op_dmfc0_vpeschedule(); |
| 3189 | 3175 |
rn = "VPESchedule"; |
| 3190 | 3176 |
break; |
| 3191 | 3177 |
case 6: |
| 3192 |
check_mips_mt(env, ctx);
|
|
| 3178 |
check_insn(env, ctx, ASE_MT);
|
|
| 3193 | 3179 |
gen_op_dmfc0_vpeschefback(); |
| 3194 | 3180 |
rn = "VPEScheFBack"; |
| 3195 | 3181 |
break; |
| 3196 | 3182 |
case 7: |
| 3197 |
check_mips_mt(env, ctx);
|
|
| 3183 |
check_insn(env, ctx, ASE_MT);
|
|
| 3198 | 3184 |
gen_op_mfc0_vpeopt(); |
| 3199 | 3185 |
rn = "VPEOpt"; |
| 3200 | 3186 |
break; |
| ... | ... | |
| 3209 | 3195 |
rn = "EntryLo0"; |
| 3210 | 3196 |
break; |
| 3211 | 3197 |
case 1: |
| 3212 |
check_mips_mt(env, ctx);
|
|
| 3198 |
check_insn(env, ctx, ASE_MT);
|
|
| 3213 | 3199 |
gen_op_mfc0_tcstatus(); |
| 3214 | 3200 |
rn = "TCStatus"; |
| 3215 | 3201 |
break; |
| 3216 | 3202 |
case 2: |
| 3217 |
check_mips_mt(env, ctx);
|
|
| 3203 |
check_insn(env, ctx, ASE_MT);
|
|
| 3218 | 3204 |
gen_op_mfc0_tcbind(); |
| 3219 | 3205 |
rn = "TCBind"; |
| 3220 | 3206 |
break; |
| 3221 | 3207 |
case 3: |
| 3222 |
check_mips_mt(env, ctx);
|
|
| 3208 |
check_insn(env, ctx, ASE_MT);
|
|
| 3223 | 3209 |
gen_op_dmfc0_tcrestart(); |
| 3224 | 3210 |
rn = "TCRestart"; |
| 3225 | 3211 |
break; |
| 3226 | 3212 |
case 4: |
| 3227 |
check_mips_mt(env, ctx);
|
|
| 3213 |
check_insn(env, ctx, ASE_MT);
|
|
| 3228 | 3214 |
gen_op_dmfc0_tchalt(); |
| 3229 | 3215 |
rn = "TCHalt"; |
| 3230 | 3216 |
break; |
| 3231 | 3217 |
case 5: |
| 3232 |
check_mips_mt(env, ctx);
|
|
| 3218 |
check_insn(env, ctx, ASE_MT);
|
|
| 3233 | 3219 |
gen_op_dmfc0_tccontext(); |
| 3234 | 3220 |
rn = "TCContext"; |
| 3235 | 3221 |
break; |
| 3236 | 3222 |
case 6: |
| 3237 |
check_mips_mt(env, ctx);
|
|
| 3223 |
check_insn(env, ctx, ASE_MT);
|
|
| 3238 | 3224 |
gen_op_dmfc0_tcschedule(); |
| 3239 | 3225 |
rn = "TCSchedule"; |
| 3240 | 3226 |
break; |
| 3241 | 3227 |
case 7: |
| 3242 |
check_mips_mt(env, ctx);
|
|
| 3228 |
check_insn(env, ctx, ASE_MT);
|
|
| 3243 | 3229 |
gen_op_dmfc0_tcschefback(); |
| 3244 | 3230 |
rn = "TCScheFBack"; |
| 3245 | 3231 |
break; |
| ... | ... | |
| 3696 | 3682 |
rn = "Index"; |
| 3697 | 3683 |
break; |
| 3698 | 3684 |
case 1: |
| 3699 |
check_mips_mt(env, ctx);
|
|
| 3685 |
check_insn(env, ctx, ASE_MT);
|
|
| 3700 | 3686 |
gen_op_mtc0_mvpcontrol(); |
| 3701 | 3687 |
rn = "MVPControl"; |
| 3702 | 3688 |
break; |
| 3703 | 3689 |
case 2: |
| 3704 |
check_mips_mt(env, ctx);
|
|
| 3690 |
check_insn(env, ctx, ASE_MT);
|
|
| 3705 | 3691 |
/* ignored */ |
| 3706 | 3692 |
rn = "MVPConf0"; |
| 3707 | 3693 |
break; |
| 3708 | 3694 |
case 3: |
| 3709 |
check_mips_mt(env, ctx);
|
|
| 3695 |
check_insn(env, ctx, ASE_MT);
|
|
| 3710 | 3696 |
/* ignored */ |
| 3711 | 3697 |
rn = "MVPConf1"; |
| 3712 | 3698 |
break; |
| ... | ... | |
| 3721 | 3707 |
rn = "Random"; |
| 3722 | 3708 |
break; |
| 3723 | 3709 |
case 1: |
| 3724 |
check_mips_mt(env, ctx);
|
|
| 3710 |
check_insn(env, ctx, ASE_MT);
|
|
| 3725 | 3711 |
gen_op_mtc0_vpecontrol(); |
| 3726 | 3712 |
rn = "VPEControl"; |
| 3727 | 3713 |
break; |
| 3728 | 3714 |
case 2: |
| 3729 |
check_mips_mt(env, ctx);
|
|
| 3715 |
check_insn(env, ctx, ASE_MT);
|
|
| 3730 | 3716 |
gen_op_mtc0_vpeconf0(); |
| 3731 | 3717 |
rn = "VPEConf0"; |
| 3732 | 3718 |
break; |
| 3733 | 3719 |
case 3: |
| 3734 |
check_mips_mt(env, ctx);
|
|
| 3720 |
check_insn(env, ctx, ASE_MT);
|
|
| 3735 | 3721 |
gen_op_mtc0_vpeconf1(); |
| 3736 | 3722 |
rn = "VPEConf1"; |
| 3737 | 3723 |
break; |
| 3738 | 3724 |
case 4: |
| 3739 |
check_mips_mt(env, ctx);
|
|
| 3725 |
check_insn(env, ctx, ASE_MT);
|
|
| 3740 | 3726 |
gen_op_mtc0_yqmask(); |
| 3741 | 3727 |
rn = "YQMask"; |
| 3742 | 3728 |
break; |
| 3743 | 3729 |
case 5: |
| 3744 |
check_mips_mt(env, ctx);
|
|
| 3730 |
check_insn(env, ctx, ASE_MT);
|
|
| 3745 | 3731 |
gen_op_mtc0_vpeschedule(); |
| 3746 | 3732 |
rn = "VPESchedule"; |
| 3747 | 3733 |
break; |
| 3748 | 3734 |
case 6: |
| 3749 |
check_mips_mt(env, ctx);
|
|
| 3735 |
check_insn(env, ctx, ASE_MT);
|
|
| 3750 | 3736 |
gen_op_mtc0_vpeschefback(); |
| 3751 | 3737 |
rn = "VPEScheFBack"; |
| 3752 | 3738 |
break; |
| 3753 | 3739 |
case 7: |
| 3754 |
check_mips_mt(env, ctx);
|
|
| 3740 |
check_insn(env, ctx, ASE_MT);
|
|
| 3755 | 3741 |
gen_op_mtc0_vpeopt(); |
| 3756 | 3742 |
rn = "VPEOpt"; |
| 3757 | 3743 |
break; |
| ... | ... | |
| 3766 | 3752 |
rn = "EntryLo0"; |
| 3767 | 3753 |
break; |
| 3768 | 3754 |
case 1: |
| 3769 |
check_mips_mt(env, ctx);
|
|
| 3755 |
check_insn(env, ctx, ASE_MT);
|
|
| 3770 | 3756 |
gen_op_mtc0_tcstatus(); |
| 3771 | 3757 |
rn = "TCStatus"; |
| 3772 | 3758 |
break; |
| 3773 | 3759 |
case 2: |
| 3774 |
check_mips_mt(env, ctx);
|
|
| 3760 |
check_insn(env, ctx, ASE_MT);
|
|
| 3775 | 3761 |
gen_op_mtc0_tcbind(); |
| 3776 | 3762 |
rn = "TCBind"; |
| 3777 | 3763 |
break; |
| 3778 | 3764 |
case 3: |
| 3779 |
check_mips_mt(env, ctx);
|
|
| 3765 |
check_insn(env, ctx, ASE_MT);
|
|
| 3780 | 3766 |
gen_op_mtc0_tcrestart(); |
| 3781 | 3767 |
rn = "TCRestart"; |
| 3782 | 3768 |
break; |
| 3783 | 3769 |
case 4: |
| 3784 |
check_mips_mt(env, ctx);
|
|
| 3770 |
check_insn(env, ctx, ASE_MT);
|
|
| 3785 | 3771 |
gen_op_mtc0_tchalt(); |
| 3786 | 3772 |
rn = "TCHalt"; |
| 3787 | 3773 |
break; |
| 3788 | 3774 |
case 5: |
| 3789 |
check_mips_mt(env, ctx);
|
|
| 3775 |
check_insn(env, ctx, ASE_MT);
|
|
| 3790 | 3776 |
gen_op_mtc0_tccontext(); |
| 3791 | 3777 |
rn = "TCContext"; |
| 3792 | 3778 |
break; |
| 3793 | 3779 |
case 6: |
| 3794 |
check_mips_mt(env, ctx);
|
|
| 3780 |
check_insn(env, ctx, ASE_MT);
|
|
| 3795 | 3781 |
gen_op_mtc0_tcschedule(); |
| 3796 | 3782 |
rn = "TCSchedule"; |
| 3797 | 3783 |
break; |
| 3798 | 3784 |
case 7: |
| 3799 |
check_mips_mt(env, ctx);
|
|
| 3785 |
check_insn(env, ctx, ASE_MT);
|
|
| 3800 | 3786 |
gen_op_mtc0_tcschefback(); |
| 3801 | 3787 |
rn = "TCScheFBack"; |
| 3802 | 3788 |
break; |
| ... | ... | |
| 4636 | 4622 |
break; |
| 4637 | 4623 |
#endif |
| 4638 | 4624 |
case OPC_MFTR: |
| 4639 |
check_mips_mt(env, ctx);
|
|
| 4625 |
check_insn(env, ctx, ASE_MT);
|
|
| 4640 | 4626 |
if (rd == 0) {
|
| 4641 | 4627 |
/* Treat as NOP. */ |
| 4642 | 4628 |
return; |
| ... | ... | |
| 4647 | 4633 |
opn = "mftr"; |
| 4648 | 4634 |
break; |
| 4649 | 4635 |
case OPC_MTTR: |
| 4650 |
check_mips_mt(env, ctx);
|
|
| 4636 |
check_insn(env, ctx, ASE_MT);
|
|
| 4651 | 4637 |
GEN_LOAD_REG_TN(T0, rt); |
| 4652 | 4638 |
gen_mttr(env, ctx, rd, (ctx->opcode >> 5) & 1, |
| 4653 | 4639 |
ctx->opcode & 0x7, (ctx->opcode >> 4) & 1); |
| ... | ... | |
| 5893 | 5879 |
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64) |
| 5894 | 5880 |
|
| 5895 | 5881 |
/* MDMX extension to MIPS64 */ |
| 5896 |
/* MIPS-3D extension to MIPS64 */ |
|
| 5897 | 5882 |
|
| 5898 | 5883 |
#endif |
| 5899 | 5884 |
|
| ... | ... | |
| 6133 | 6118 |
GEN_STORE_TN_REG(rt, T0); |
| 6134 | 6119 |
break; |
| 6135 | 6120 |
case OPC_FORK: |
| 6136 |
check_mips_mt(env, ctx);
|
|
| 6121 |
check_insn(env, ctx, ASE_MT);
|
|
| 6137 | 6122 |
GEN_LOAD_REG_TN(T0, rt); |
| 6138 | 6123 |
GEN_LOAD_REG_TN(T1, rs); |
| 6139 | 6124 |
gen_op_fork(); |
| 6140 | 6125 |
break; |
| 6141 | 6126 |
case OPC_YIELD: |
| 6142 |
check_mips_mt(env, ctx);
|
|
| 6127 |
check_insn(env, ctx, ASE_MT);
|
|
| 6143 | 6128 |
GEN_LOAD_REG_TN(T0, rs); |
| 6144 | 6129 |
gen_op_yield(); |
| 6145 | 6130 |
GEN_STORE_TN_REG(rd, T0); |
| ... | ... | |
| 6219 | 6204 |
op2 = MASK_MFMC0(ctx->opcode); |
| 6220 | 6205 |
switch (op2) {
|
| 6221 | 6206 |
case OPC_DMT: |
| 6222 |
check_mips_mt(env, ctx);
|
|
| 6207 |
check_insn(env, ctx, ASE_MT);
|
|
| 6223 | 6208 |
gen_op_dmt(); |
| 6224 | 6209 |
break; |
| 6225 | 6210 |
case OPC_EMT: |
| 6226 |
check_mips_mt(env, ctx);
|
|
| 6211 |
check_insn(env, ctx, ASE_MT);
|
|
| 6227 | 6212 |
gen_op_emt(); |
| 6228 | 6213 |
break; |
| 6229 | 6214 |
case OPC_DVPE: |
| 6230 |
check_mips_mt(env, ctx);
|
|
| 6215 |
check_insn(env, ctx, ASE_MT);
|
|
| 6231 | 6216 |
gen_op_dvpe(); |
| 6232 | 6217 |
break; |
| 6233 | 6218 |
case OPC_EVPE: |
| 6234 |
check_mips_mt(env, ctx);
|
|
| 6219 |
check_insn(env, ctx, ASE_MT);
|
|
| 6235 | 6220 |
gen_op_evpe(); |
| 6236 | 6221 |
break; |
| 6237 | 6222 |
case OPC_DI: |
| ... | ... | |
| 6336 | 6321 |
#endif |
| 6337 | 6322 |
case OPC_BC1ANY2: |
| 6338 | 6323 |
case OPC_BC1ANY4: |
| 6339 |
check_cp1_3d(env, ctx);
|
|
| 6324 |
check_insn(env, ctx, ASE_MIPS3D);
|
|
| 6340 | 6325 |
/* fall through */ |
| 6341 | 6326 |
case OPC_BC1: |
| 6342 | 6327 |
gen_compute_branch1(env, ctx, MASK_BC1(ctx->opcode), |
Also available in: Unified diff