Revision 7385ac0b target-mips/translate_init.c

b/target-mips/translate_init.c
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        .CP0_SRSConf4_rw_bitmask = 0x3fffffff,
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        .CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) |
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                    (0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13),
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        .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP,
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        .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
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    },
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#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
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    {

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