root / target-ppc / kvm.c @ 73aaec4a
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1 | d76d1650 | aurel32 | /*
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2 | d76d1650 | aurel32 | * PowerPC implementation of KVM hooks
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3 | d76d1650 | aurel32 | *
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4 | d76d1650 | aurel32 | * Copyright IBM Corp. 2007
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5 | d76d1650 | aurel32 | *
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6 | d76d1650 | aurel32 | * Authors:
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7 | d76d1650 | aurel32 | * Jerone Young <jyoung5@us.ibm.com>
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8 | d76d1650 | aurel32 | * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
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9 | d76d1650 | aurel32 | * Hollis Blanchard <hollisb@us.ibm.com>
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10 | d76d1650 | aurel32 | *
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11 | d76d1650 | aurel32 | * This work is licensed under the terms of the GNU GPL, version 2 or later.
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12 | d76d1650 | aurel32 | * See the COPYING file in the top-level directory.
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13 | d76d1650 | aurel32 | *
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14 | d76d1650 | aurel32 | */
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15 | d76d1650 | aurel32 | |
16 | d76d1650 | aurel32 | #include <sys/types.h> |
17 | d76d1650 | aurel32 | #include <sys/ioctl.h> |
18 | d76d1650 | aurel32 | #include <sys/mman.h> |
19 | d76d1650 | aurel32 | |
20 | d76d1650 | aurel32 | #include <linux/kvm.h> |
21 | d76d1650 | aurel32 | |
22 | d76d1650 | aurel32 | #include "qemu-common.h" |
23 | d76d1650 | aurel32 | #include "qemu-timer.h" |
24 | d76d1650 | aurel32 | #include "sysemu.h" |
25 | d76d1650 | aurel32 | #include "kvm.h" |
26 | d76d1650 | aurel32 | #include "kvm_ppc.h" |
27 | d76d1650 | aurel32 | #include "cpu.h" |
28 | d76d1650 | aurel32 | #include "device_tree.h" |
29 | d76d1650 | aurel32 | |
30 | d76d1650 | aurel32 | //#define DEBUG_KVM
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31 | d76d1650 | aurel32 | |
32 | d76d1650 | aurel32 | #ifdef DEBUG_KVM
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33 | d76d1650 | aurel32 | #define dprintf(fmt, ...) \
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34 | d76d1650 | aurel32 | do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0) |
35 | d76d1650 | aurel32 | #else
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36 | d76d1650 | aurel32 | #define dprintf(fmt, ...) \
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37 | d76d1650 | aurel32 | do { } while (0) |
38 | d76d1650 | aurel32 | #endif
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39 | d76d1650 | aurel32 | |
40 | fc87e185 | Alexander Graf | static int cap_interrupt_unset = false; |
41 | fc87e185 | Alexander Graf | static int cap_interrupt_level = false; |
42 | fc87e185 | Alexander Graf | |
43 | c821c2bd | Alexander Graf | /* XXX We have a race condition where we actually have a level triggered
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44 | c821c2bd | Alexander Graf | * interrupt, but the infrastructure can't expose that yet, so the guest
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45 | c821c2bd | Alexander Graf | * takes but ignores it, goes to sleep and never gets notified that there's
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46 | c821c2bd | Alexander Graf | * still an interrupt pending.
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47 | c6a94ba5 | Alexander Graf | *
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48 | c821c2bd | Alexander Graf | * As a quick workaround, let's just wake up again 20 ms after we injected
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49 | c821c2bd | Alexander Graf | * an interrupt. That way we can assure that we're always reinjecting
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50 | c821c2bd | Alexander Graf | * interrupts in case the guest swallowed them.
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51 | c6a94ba5 | Alexander Graf | */
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52 | c6a94ba5 | Alexander Graf | static QEMUTimer *idle_timer;
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53 | c6a94ba5 | Alexander Graf | |
54 | c821c2bd | Alexander Graf | static void kvm_kick_env(void *env) |
55 | c6a94ba5 | Alexander Graf | { |
56 | c821c2bd | Alexander Graf | qemu_cpu_kick(env); |
57 | c6a94ba5 | Alexander Graf | } |
58 | c6a94ba5 | Alexander Graf | |
59 | d76d1650 | aurel32 | int kvm_arch_init(KVMState *s, int smp_cpus) |
60 | d76d1650 | aurel32 | { |
61 | fc87e185 | Alexander Graf | #ifdef KVM_CAP_PPC_UNSET_IRQ
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62 | fc87e185 | Alexander Graf | cap_interrupt_unset = kvm_check_extension(s, KVM_CAP_PPC_UNSET_IRQ); |
63 | fc87e185 | Alexander Graf | #endif
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64 | fc87e185 | Alexander Graf | #ifdef KVM_CAP_PPC_IRQ_LEVEL
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65 | fc87e185 | Alexander Graf | cap_interrupt_level = kvm_check_extension(s, KVM_CAP_PPC_IRQ_LEVEL); |
66 | fc87e185 | Alexander Graf | #endif
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67 | fc87e185 | Alexander Graf | |
68 | fc87e185 | Alexander Graf | if (!cap_interrupt_level) {
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69 | fc87e185 | Alexander Graf | fprintf(stderr, "KVM: Couldn't find level irq capability. Expect the "
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70 | fc87e185 | Alexander Graf | "VM to stall at times!\n");
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71 | fc87e185 | Alexander Graf | } |
72 | fc87e185 | Alexander Graf | |
73 | d76d1650 | aurel32 | return 0; |
74 | d76d1650 | aurel32 | } |
75 | d76d1650 | aurel32 | |
76 | d76d1650 | aurel32 | int kvm_arch_init_vcpu(CPUState *cenv)
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77 | d76d1650 | aurel32 | { |
78 | 861bbc80 | Alexander Graf | int ret = 0; |
79 | 861bbc80 | Alexander Graf | struct kvm_sregs sregs;
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80 | 861bbc80 | Alexander Graf | |
81 | 861bbc80 | Alexander Graf | sregs.pvr = cenv->spr[SPR_PVR]; |
82 | 861bbc80 | Alexander Graf | ret = kvm_vcpu_ioctl(cenv, KVM_SET_SREGS, &sregs); |
83 | 861bbc80 | Alexander Graf | |
84 | c821c2bd | Alexander Graf | idle_timer = qemu_new_timer(vm_clock, kvm_kick_env, cenv); |
85 | c821c2bd | Alexander Graf | |
86 | 861bbc80 | Alexander Graf | return ret;
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87 | d76d1650 | aurel32 | } |
88 | d76d1650 | aurel32 | |
89 | caa5af0f | Jan Kiszka | void kvm_arch_reset_vcpu(CPUState *env)
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90 | caa5af0f | Jan Kiszka | { |
91 | caa5af0f | Jan Kiszka | } |
92 | caa5af0f | Jan Kiszka | |
93 | ea375f9a | Jan Kiszka | int kvm_arch_put_registers(CPUState *env, int level) |
94 | d76d1650 | aurel32 | { |
95 | d76d1650 | aurel32 | struct kvm_regs regs;
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96 | d76d1650 | aurel32 | int ret;
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97 | d76d1650 | aurel32 | int i;
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98 | d76d1650 | aurel32 | |
99 | d76d1650 | aurel32 | ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, ®s); |
100 | d76d1650 | aurel32 | if (ret < 0) |
101 | d76d1650 | aurel32 | return ret;
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102 | d76d1650 | aurel32 | |
103 | d76d1650 | aurel32 | regs.ctr = env->ctr; |
104 | d76d1650 | aurel32 | regs.lr = env->lr; |
105 | d76d1650 | aurel32 | regs.xer = env->xer; |
106 | d76d1650 | aurel32 | regs.msr = env->msr; |
107 | d76d1650 | aurel32 | regs.pc = env->nip; |
108 | d76d1650 | aurel32 | |
109 | d76d1650 | aurel32 | regs.srr0 = env->spr[SPR_SRR0]; |
110 | d76d1650 | aurel32 | regs.srr1 = env->spr[SPR_SRR1]; |
111 | d76d1650 | aurel32 | |
112 | d76d1650 | aurel32 | regs.sprg0 = env->spr[SPR_SPRG0]; |
113 | d76d1650 | aurel32 | regs.sprg1 = env->spr[SPR_SPRG1]; |
114 | d76d1650 | aurel32 | regs.sprg2 = env->spr[SPR_SPRG2]; |
115 | d76d1650 | aurel32 | regs.sprg3 = env->spr[SPR_SPRG3]; |
116 | d76d1650 | aurel32 | regs.sprg4 = env->spr[SPR_SPRG4]; |
117 | d76d1650 | aurel32 | regs.sprg5 = env->spr[SPR_SPRG5]; |
118 | d76d1650 | aurel32 | regs.sprg6 = env->spr[SPR_SPRG6]; |
119 | d76d1650 | aurel32 | regs.sprg7 = env->spr[SPR_SPRG7]; |
120 | d76d1650 | aurel32 | |
121 | d76d1650 | aurel32 | for (i = 0;i < 32; i++) |
122 | d76d1650 | aurel32 | regs.gpr[i] = env->gpr[i]; |
123 | d76d1650 | aurel32 | |
124 | d76d1650 | aurel32 | ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, ®s); |
125 | d76d1650 | aurel32 | if (ret < 0) |
126 | d76d1650 | aurel32 | return ret;
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127 | d76d1650 | aurel32 | |
128 | d76d1650 | aurel32 | return ret;
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129 | d76d1650 | aurel32 | } |
130 | d76d1650 | aurel32 | |
131 | d76d1650 | aurel32 | int kvm_arch_get_registers(CPUState *env)
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132 | d76d1650 | aurel32 | { |
133 | d76d1650 | aurel32 | struct kvm_regs regs;
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134 | ba5e5090 | Alexander Graf | struct kvm_sregs sregs;
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135 | 138b38b6 | Alexander Graf | int i, ret;
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136 | d76d1650 | aurel32 | |
137 | d76d1650 | aurel32 | ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, ®s); |
138 | d76d1650 | aurel32 | if (ret < 0) |
139 | d76d1650 | aurel32 | return ret;
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140 | d76d1650 | aurel32 | |
141 | ba5e5090 | Alexander Graf | ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs); |
142 | ba5e5090 | Alexander Graf | if (ret < 0) |
143 | ba5e5090 | Alexander Graf | return ret;
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144 | ba5e5090 | Alexander Graf | |
145 | d76d1650 | aurel32 | env->ctr = regs.ctr; |
146 | d76d1650 | aurel32 | env->lr = regs.lr; |
147 | d76d1650 | aurel32 | env->xer = regs.xer; |
148 | d76d1650 | aurel32 | env->msr = regs.msr; |
149 | d76d1650 | aurel32 | env->nip = regs.pc; |
150 | d76d1650 | aurel32 | |
151 | d76d1650 | aurel32 | env->spr[SPR_SRR0] = regs.srr0; |
152 | d76d1650 | aurel32 | env->spr[SPR_SRR1] = regs.srr1; |
153 | d76d1650 | aurel32 | |
154 | d76d1650 | aurel32 | env->spr[SPR_SPRG0] = regs.sprg0; |
155 | d76d1650 | aurel32 | env->spr[SPR_SPRG1] = regs.sprg1; |
156 | d76d1650 | aurel32 | env->spr[SPR_SPRG2] = regs.sprg2; |
157 | d76d1650 | aurel32 | env->spr[SPR_SPRG3] = regs.sprg3; |
158 | d76d1650 | aurel32 | env->spr[SPR_SPRG4] = regs.sprg4; |
159 | d76d1650 | aurel32 | env->spr[SPR_SPRG5] = regs.sprg5; |
160 | d76d1650 | aurel32 | env->spr[SPR_SPRG6] = regs.sprg6; |
161 | d76d1650 | aurel32 | env->spr[SPR_SPRG7] = regs.sprg7; |
162 | d76d1650 | aurel32 | |
163 | d76d1650 | aurel32 | for (i = 0;i < 32; i++) |
164 | d76d1650 | aurel32 | env->gpr[i] = regs.gpr[i]; |
165 | d76d1650 | aurel32 | |
166 | ba5e5090 | Alexander Graf | #ifdef KVM_CAP_PPC_SEGSTATE
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167 | ba5e5090 | Alexander Graf | if (kvm_check_extension(env->kvm_state, KVM_CAP_PPC_SEGSTATE)) {
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168 | ba5e5090 | Alexander Graf | env->sdr1 = sregs.u.s.sdr1; |
169 | ba5e5090 | Alexander Graf | |
170 | ba5e5090 | Alexander Graf | /* Sync SLB */
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171 | 82c09f2f | Alexander Graf | #ifdef TARGET_PPC64
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172 | ba5e5090 | Alexander Graf | for (i = 0; i < 64; i++) { |
173 | ba5e5090 | Alexander Graf | ppc_store_slb(env, sregs.u.s.ppc64.slb[i].slbe, |
174 | ba5e5090 | Alexander Graf | sregs.u.s.ppc64.slb[i].slbv); |
175 | ba5e5090 | Alexander Graf | } |
176 | 82c09f2f | Alexander Graf | #endif
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177 | ba5e5090 | Alexander Graf | |
178 | ba5e5090 | Alexander Graf | /* Sync SRs */
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179 | ba5e5090 | Alexander Graf | for (i = 0; i < 16; i++) { |
180 | ba5e5090 | Alexander Graf | env->sr[i] = sregs.u.s.ppc32.sr[i]; |
181 | ba5e5090 | Alexander Graf | } |
182 | ba5e5090 | Alexander Graf | |
183 | ba5e5090 | Alexander Graf | /* Sync BATs */
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184 | ba5e5090 | Alexander Graf | for (i = 0; i < 8; i++) { |
185 | ba5e5090 | Alexander Graf | env->DBAT[0][i] = sregs.u.s.ppc32.dbat[i] & 0xffffffff; |
186 | ba5e5090 | Alexander Graf | env->DBAT[1][i] = sregs.u.s.ppc32.dbat[i] >> 32; |
187 | ba5e5090 | Alexander Graf | env->IBAT[0][i] = sregs.u.s.ppc32.ibat[i] & 0xffffffff; |
188 | ba5e5090 | Alexander Graf | env->IBAT[1][i] = sregs.u.s.ppc32.ibat[i] >> 32; |
189 | ba5e5090 | Alexander Graf | } |
190 | ba5e5090 | Alexander Graf | } |
191 | ba5e5090 | Alexander Graf | #endif
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192 | ba5e5090 | Alexander Graf | |
193 | d76d1650 | aurel32 | return 0; |
194 | d76d1650 | aurel32 | } |
195 | d76d1650 | aurel32 | |
196 | fc87e185 | Alexander Graf | int kvmppc_set_interrupt(CPUState *env, int irq, int level) |
197 | fc87e185 | Alexander Graf | { |
198 | fc87e185 | Alexander Graf | unsigned virq = level ? KVM_INTERRUPT_SET_LEVEL : KVM_INTERRUPT_UNSET;
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199 | fc87e185 | Alexander Graf | |
200 | fc87e185 | Alexander Graf | if (irq != PPC_INTERRUPT_EXT) {
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201 | fc87e185 | Alexander Graf | return 0; |
202 | fc87e185 | Alexander Graf | } |
203 | fc87e185 | Alexander Graf | |
204 | fc87e185 | Alexander Graf | if (!kvm_enabled() || !cap_interrupt_unset || !cap_interrupt_level) {
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205 | fc87e185 | Alexander Graf | return 0; |
206 | fc87e185 | Alexander Graf | } |
207 | fc87e185 | Alexander Graf | |
208 | fc87e185 | Alexander Graf | kvm_vcpu_ioctl(env, KVM_INTERRUPT, &virq); |
209 | fc87e185 | Alexander Graf | |
210 | fc87e185 | Alexander Graf | return 0; |
211 | fc87e185 | Alexander Graf | } |
212 | fc87e185 | Alexander Graf | |
213 | 16415335 | Alexander Graf | #if defined(TARGET_PPCEMB)
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214 | 16415335 | Alexander Graf | #define PPC_INPUT_INT PPC40x_INPUT_INT
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215 | 16415335 | Alexander Graf | #elif defined(TARGET_PPC64)
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216 | 16415335 | Alexander Graf | #define PPC_INPUT_INT PPC970_INPUT_INT
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217 | 16415335 | Alexander Graf | #else
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218 | 16415335 | Alexander Graf | #define PPC_INPUT_INT PPC6xx_INPUT_INT
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219 | 16415335 | Alexander Graf | #endif
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220 | 16415335 | Alexander Graf | |
221 | d76d1650 | aurel32 | int kvm_arch_pre_run(CPUState *env, struct kvm_run *run) |
222 | d76d1650 | aurel32 | { |
223 | d76d1650 | aurel32 | int r;
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224 | d76d1650 | aurel32 | unsigned irq;
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225 | d76d1650 | aurel32 | |
226 | d76d1650 | aurel32 | /* PowerPC Qemu tracks the various core input pins (interrupt, critical
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227 | d76d1650 | aurel32 | * interrupt, reset, etc) in PPC-specific env->irq_input_state. */
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228 | fc87e185 | Alexander Graf | if (!cap_interrupt_level &&
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229 | fc87e185 | Alexander Graf | run->ready_for_interrupt_injection && |
230 | d76d1650 | aurel32 | (env->interrupt_request & CPU_INTERRUPT_HARD) && |
231 | 16415335 | Alexander Graf | (env->irq_input_state & (1<<PPC_INPUT_INT)))
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232 | d76d1650 | aurel32 | { |
233 | d76d1650 | aurel32 | /* For now KVM disregards the 'irq' argument. However, in the
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234 | d76d1650 | aurel32 | * future KVM could cache it in-kernel to avoid a heavyweight exit
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235 | d76d1650 | aurel32 | * when reading the UIC.
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236 | d76d1650 | aurel32 | */
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237 | fc87e185 | Alexander Graf | irq = KVM_INTERRUPT_SET; |
238 | d76d1650 | aurel32 | |
239 | d76d1650 | aurel32 | dprintf("injected interrupt %d\n", irq);
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240 | d76d1650 | aurel32 | r = kvm_vcpu_ioctl(env, KVM_INTERRUPT, &irq); |
241 | d76d1650 | aurel32 | if (r < 0) |
242 | d76d1650 | aurel32 | printf("cpu %d fail inject %x\n", env->cpu_index, irq);
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243 | c821c2bd | Alexander Graf | |
244 | c821c2bd | Alexander Graf | /* Always wake up soon in case the interrupt was level based */
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245 | c821c2bd | Alexander Graf | qemu_mod_timer(idle_timer, qemu_get_clock(vm_clock) + |
246 | c821c2bd | Alexander Graf | (get_ticks_per_sec() / 50));
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247 | d76d1650 | aurel32 | } |
248 | d76d1650 | aurel32 | |
249 | d76d1650 | aurel32 | /* We don't know if there are more interrupts pending after this. However,
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250 | d76d1650 | aurel32 | * the guest will return to userspace in the course of handling this one
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251 | d76d1650 | aurel32 | * anyways, so we will get a chance to deliver the rest. */
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252 | d76d1650 | aurel32 | return 0; |
253 | d76d1650 | aurel32 | } |
254 | d76d1650 | aurel32 | |
255 | d76d1650 | aurel32 | int kvm_arch_post_run(CPUState *env, struct kvm_run *run) |
256 | d76d1650 | aurel32 | { |
257 | d76d1650 | aurel32 | return 0; |
258 | d76d1650 | aurel32 | } |
259 | d76d1650 | aurel32 | |
260 | 0af691d7 | Marcelo Tosatti | int kvm_arch_process_irqchip_events(CPUState *env)
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261 | 0af691d7 | Marcelo Tosatti | { |
262 | 0af691d7 | Marcelo Tosatti | return 0; |
263 | 0af691d7 | Marcelo Tosatti | } |
264 | 0af691d7 | Marcelo Tosatti | |
265 | d76d1650 | aurel32 | static int kvmppc_handle_halt(CPUState *env) |
266 | d76d1650 | aurel32 | { |
267 | d76d1650 | aurel32 | if (!(env->interrupt_request & CPU_INTERRUPT_HARD) && (msr_ee)) {
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268 | d76d1650 | aurel32 | env->halted = 1;
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269 | d76d1650 | aurel32 | env->exception_index = EXCP_HLT; |
270 | d76d1650 | aurel32 | } |
271 | d76d1650 | aurel32 | |
272 | d76d1650 | aurel32 | return 1; |
273 | d76d1650 | aurel32 | } |
274 | d76d1650 | aurel32 | |
275 | d76d1650 | aurel32 | /* map dcr access to existing qemu dcr emulation */
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276 | d76d1650 | aurel32 | static int kvmppc_handle_dcr_read(CPUState *env, uint32_t dcrn, uint32_t *data) |
277 | d76d1650 | aurel32 | { |
278 | d76d1650 | aurel32 | if (ppc_dcr_read(env->dcr_env, dcrn, data) < 0) |
279 | d76d1650 | aurel32 | fprintf(stderr, "Read to unhandled DCR (0x%x)\n", dcrn);
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280 | d76d1650 | aurel32 | |
281 | d76d1650 | aurel32 | return 1; |
282 | d76d1650 | aurel32 | } |
283 | d76d1650 | aurel32 | |
284 | d76d1650 | aurel32 | static int kvmppc_handle_dcr_write(CPUState *env, uint32_t dcrn, uint32_t data) |
285 | d76d1650 | aurel32 | { |
286 | d76d1650 | aurel32 | if (ppc_dcr_write(env->dcr_env, dcrn, data) < 0) |
287 | d76d1650 | aurel32 | fprintf(stderr, "Write to unhandled DCR (0x%x)\n", dcrn);
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288 | d76d1650 | aurel32 | |
289 | d76d1650 | aurel32 | return 1; |
290 | d76d1650 | aurel32 | } |
291 | d76d1650 | aurel32 | |
292 | d76d1650 | aurel32 | int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run) |
293 | d76d1650 | aurel32 | { |
294 | d76d1650 | aurel32 | int ret = 0; |
295 | d76d1650 | aurel32 | |
296 | d76d1650 | aurel32 | switch (run->exit_reason) {
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297 | d76d1650 | aurel32 | case KVM_EXIT_DCR:
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298 | d76d1650 | aurel32 | if (run->dcr.is_write) {
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299 | d76d1650 | aurel32 | dprintf("handle dcr write\n");
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300 | d76d1650 | aurel32 | ret = kvmppc_handle_dcr_write(env, run->dcr.dcrn, run->dcr.data); |
301 | d76d1650 | aurel32 | } else {
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302 | d76d1650 | aurel32 | dprintf("handle dcr read\n");
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303 | d76d1650 | aurel32 | ret = kvmppc_handle_dcr_read(env, run->dcr.dcrn, &run->dcr.data); |
304 | d76d1650 | aurel32 | } |
305 | d76d1650 | aurel32 | break;
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306 | d76d1650 | aurel32 | case KVM_EXIT_HLT:
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307 | d76d1650 | aurel32 | dprintf("handle halt\n");
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308 | d76d1650 | aurel32 | ret = kvmppc_handle_halt(env); |
309 | d76d1650 | aurel32 | break;
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310 | 73aaec4a | Jan Kiszka | default:
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311 | 73aaec4a | Jan Kiszka | fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
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312 | 73aaec4a | Jan Kiszka | ret = -1;
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313 | 73aaec4a | Jan Kiszka | break;
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314 | d76d1650 | aurel32 | } |
315 | d76d1650 | aurel32 | |
316 | d76d1650 | aurel32 | return ret;
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317 | d76d1650 | aurel32 | } |
318 | d76d1650 | aurel32 | |
319 | dc333cd6 | Alexander Graf | static int read_cpuinfo(const char *field, char *value, int len) |
320 | dc333cd6 | Alexander Graf | { |
321 | dc333cd6 | Alexander Graf | FILE *f; |
322 | dc333cd6 | Alexander Graf | int ret = -1; |
323 | dc333cd6 | Alexander Graf | int field_len = strlen(field);
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324 | dc333cd6 | Alexander Graf | char line[512]; |
325 | dc333cd6 | Alexander Graf | |
326 | dc333cd6 | Alexander Graf | f = fopen("/proc/cpuinfo", "r"); |
327 | dc333cd6 | Alexander Graf | if (!f) {
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328 | dc333cd6 | Alexander Graf | return -1; |
329 | dc333cd6 | Alexander Graf | } |
330 | dc333cd6 | Alexander Graf | |
331 | dc333cd6 | Alexander Graf | do {
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332 | dc333cd6 | Alexander Graf | if(!fgets(line, sizeof(line), f)) { |
333 | dc333cd6 | Alexander Graf | break;
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334 | dc333cd6 | Alexander Graf | } |
335 | dc333cd6 | Alexander Graf | if (!strncmp(line, field, field_len)) {
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336 | dc333cd6 | Alexander Graf | strncpy(value, line, len); |
337 | dc333cd6 | Alexander Graf | ret = 0;
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338 | dc333cd6 | Alexander Graf | break;
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339 | dc333cd6 | Alexander Graf | } |
340 | dc333cd6 | Alexander Graf | } while(*line);
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341 | dc333cd6 | Alexander Graf | |
342 | dc333cd6 | Alexander Graf | fclose(f); |
343 | dc333cd6 | Alexander Graf | |
344 | dc333cd6 | Alexander Graf | return ret;
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345 | dc333cd6 | Alexander Graf | } |
346 | dc333cd6 | Alexander Graf | |
347 | dc333cd6 | Alexander Graf | uint32_t kvmppc_get_tbfreq(void)
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348 | dc333cd6 | Alexander Graf | { |
349 | dc333cd6 | Alexander Graf | char line[512]; |
350 | dc333cd6 | Alexander Graf | char *ns;
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351 | dc333cd6 | Alexander Graf | uint32_t retval = get_ticks_per_sec(); |
352 | dc333cd6 | Alexander Graf | |
353 | dc333cd6 | Alexander Graf | if (read_cpuinfo("timebase", line, sizeof(line))) { |
354 | dc333cd6 | Alexander Graf | return retval;
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355 | dc333cd6 | Alexander Graf | } |
356 | dc333cd6 | Alexander Graf | |
357 | dc333cd6 | Alexander Graf | if (!(ns = strchr(line, ':'))) { |
358 | dc333cd6 | Alexander Graf | return retval;
|
359 | dc333cd6 | Alexander Graf | } |
360 | dc333cd6 | Alexander Graf | |
361 | dc333cd6 | Alexander Graf | ns++; |
362 | dc333cd6 | Alexander Graf | |
363 | dc333cd6 | Alexander Graf | retval = atoi(ns); |
364 | dc333cd6 | Alexander Graf | return retval;
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365 | dc333cd6 | Alexander Graf | } |
366 | 4513d923 | Gleb Natapov | |
367 | 45024f09 | Alexander Graf | int kvmppc_get_hypercall(CPUState *env, uint8_t *buf, int buf_len) |
368 | 45024f09 | Alexander Graf | { |
369 | 45024f09 | Alexander Graf | uint32_t *hc = (uint32_t*)buf; |
370 | 45024f09 | Alexander Graf | |
371 | 45024f09 | Alexander Graf | #ifdef KVM_CAP_PPC_GET_PVINFO
|
372 | 45024f09 | Alexander Graf | struct kvm_ppc_pvinfo pvinfo;
|
373 | 45024f09 | Alexander Graf | |
374 | 45024f09 | Alexander Graf | if (kvm_check_extension(env->kvm_state, KVM_CAP_PPC_GET_PVINFO) &&
|
375 | 45024f09 | Alexander Graf | !kvm_vm_ioctl(env->kvm_state, KVM_PPC_GET_PVINFO, &pvinfo)) { |
376 | 45024f09 | Alexander Graf | memcpy(buf, pvinfo.hcall, buf_len); |
377 | 45024f09 | Alexander Graf | |
378 | 45024f09 | Alexander Graf | return 0; |
379 | 45024f09 | Alexander Graf | } |
380 | 45024f09 | Alexander Graf | #endif
|
381 | 45024f09 | Alexander Graf | |
382 | 45024f09 | Alexander Graf | /*
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383 | 45024f09 | Alexander Graf | * Fallback to always fail hypercalls:
|
384 | 45024f09 | Alexander Graf | *
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385 | 45024f09 | Alexander Graf | * li r3, -1
|
386 | 45024f09 | Alexander Graf | * nop
|
387 | 45024f09 | Alexander Graf | * nop
|
388 | 45024f09 | Alexander Graf | * nop
|
389 | 45024f09 | Alexander Graf | */
|
390 | 45024f09 | Alexander Graf | |
391 | 45024f09 | Alexander Graf | hc[0] = 0x3860ffff; |
392 | 45024f09 | Alexander Graf | hc[1] = 0x60000000; |
393 | 45024f09 | Alexander Graf | hc[2] = 0x60000000; |
394 | 45024f09 | Alexander Graf | hc[3] = 0x60000000; |
395 | 45024f09 | Alexander Graf | |
396 | 45024f09 | Alexander Graf | return 0; |
397 | 45024f09 | Alexander Graf | } |
398 | 45024f09 | Alexander Graf | |
399 | 4513d923 | Gleb Natapov | bool kvm_arch_stop_on_emulation_error(CPUState *env)
|
400 | 4513d923 | Gleb Natapov | { |
401 | 4513d923 | Gleb Natapov | return true; |
402 | 4513d923 | Gleb Natapov | } |