Revision 73b01960
| b/darwin-user/main.c | ||
|---|---|---|
| 113 | 113 |
} |
| 114 | 114 |
|
| 115 | 115 |
/* XXX: to be fixed */ |
| 116 |
int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp)
|
|
| 116 |
int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
|
|
| 117 | 117 |
{
|
| 118 | 118 |
return -1; |
| 119 | 119 |
} |
| 120 | 120 |
|
| 121 |
int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val)
|
|
| 121 |
int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
|
|
| 122 | 122 |
{
|
| 123 | 123 |
return -1; |
| 124 | 124 |
} |
| b/hw/ppc.c | ||
|---|---|---|
| 1009 | 1009 |
int (*write_error)(int dcrn); |
| 1010 | 1010 |
}; |
| 1011 | 1011 |
|
| 1012 |
int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp)
|
|
| 1012 |
int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
|
|
| 1013 | 1013 |
{
|
| 1014 | 1014 |
ppc_dcrn_t *dcr; |
| 1015 | 1015 |
|
| ... | ... | |
| 1029 | 1029 |
return -1; |
| 1030 | 1030 |
} |
| 1031 | 1031 |
|
| 1032 |
int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val)
|
|
| 1032 |
int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
|
|
| 1033 | 1033 |
{
|
| 1034 | 1034 |
ppc_dcrn_t *dcr; |
| 1035 | 1035 |
|
| b/hw/ppc.h | ||
|---|---|---|
| 13 | 13 |
|
| 14 | 14 |
clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq); |
| 15 | 15 |
/* Embedded PowerPC DCR management */ |
| 16 |
typedef target_ulong (*dcr_read_cb)(void *opaque, int dcrn);
|
|
| 17 |
typedef void (*dcr_write_cb)(void *opaque, int dcrn, target_ulong val);
|
|
| 16 |
typedef uint32_t (*dcr_read_cb)(void *opaque, int dcrn);
|
|
| 17 |
typedef void (*dcr_write_cb)(void *opaque, int dcrn, uint32_t val);
|
|
| 18 | 18 |
int ppc_dcr_init (CPUState *env, int (*dcr_read_error)(int dcrn), |
| 19 | 19 |
int (*dcr_write_error)(int dcrn)); |
| 20 | 20 |
int ppc_dcr_register (CPUState *env, int dcrn, void *opaque, |
| b/hw/ppc405_uc.c | ||
|---|---|---|
| 107 | 107 |
uint32_t besr; |
| 108 | 108 |
}; |
| 109 | 109 |
|
| 110 |
static target_ulong dcr_read_plb (void *opaque, int dcrn)
|
|
| 110 |
static uint32_t dcr_read_plb (void *opaque, int dcrn)
|
|
| 111 | 111 |
{
|
| 112 | 112 |
ppc4xx_plb_t *plb; |
| 113 |
target_ulong ret;
|
|
| 113 |
uint32_t ret;
|
|
| 114 | 114 |
|
| 115 | 115 |
plb = opaque; |
| 116 | 116 |
switch (dcrn) {
|
| ... | ... | |
| 132 | 132 |
return ret; |
| 133 | 133 |
} |
| 134 | 134 |
|
| 135 |
static void dcr_write_plb (void *opaque, int dcrn, target_ulong val)
|
|
| 135 |
static void dcr_write_plb (void *opaque, int dcrn, uint32_t val)
|
|
| 136 | 136 |
{
|
| 137 | 137 |
ppc4xx_plb_t *plb; |
| 138 | 138 |
|
| ... | ... | |
| 189 | 189 |
uint32_t besr[2]; |
| 190 | 190 |
}; |
| 191 | 191 |
|
| 192 |
static target_ulong dcr_read_pob (void *opaque, int dcrn)
|
|
| 192 |
static uint32_t dcr_read_pob (void *opaque, int dcrn)
|
|
| 193 | 193 |
{
|
| 194 | 194 |
ppc4xx_pob_t *pob; |
| 195 |
target_ulong ret;
|
|
| 195 |
uint32_t ret;
|
|
| 196 | 196 |
|
| 197 | 197 |
pob = opaque; |
| 198 | 198 |
switch (dcrn) {
|
| ... | ... | |
| 212 | 212 |
return ret; |
| 213 | 213 |
} |
| 214 | 214 |
|
| 215 |
static void dcr_write_pob (void *opaque, int dcrn, target_ulong val)
|
|
| 215 |
static void dcr_write_pob (void *opaque, int dcrn, uint32_t val)
|
|
| 216 | 216 |
{
|
| 217 | 217 |
ppc4xx_pob_t *pob; |
| 218 | 218 |
|
| ... | ... | |
| 410 | 410 |
EBC0_CFGDATA = 0x013, |
| 411 | 411 |
}; |
| 412 | 412 |
|
| 413 |
static target_ulong dcr_read_ebc (void *opaque, int dcrn)
|
|
| 413 |
static uint32_t dcr_read_ebc (void *opaque, int dcrn)
|
|
| 414 | 414 |
{
|
| 415 | 415 |
ppc4xx_ebc_t *ebc; |
| 416 |
target_ulong ret;
|
|
| 416 |
uint32_t ret;
|
|
| 417 | 417 |
|
| 418 | 418 |
ebc = opaque; |
| 419 | 419 |
switch (dcrn) {
|
| ... | ... | |
| 494 | 494 |
return ret; |
| 495 | 495 |
} |
| 496 | 496 |
|
| 497 |
static void dcr_write_ebc (void *opaque, int dcrn, target_ulong val)
|
|
| 497 |
static void dcr_write_ebc (void *opaque, int dcrn, uint32_t val)
|
|
| 498 | 498 |
{
|
| 499 | 499 |
ppc4xx_ebc_t *ebc; |
| 500 | 500 |
|
| ... | ... | |
| 627 | 627 |
uint32_t pol; |
| 628 | 628 |
}; |
| 629 | 629 |
|
| 630 |
static target_ulong dcr_read_dma (void *opaque, int dcrn)
|
|
| 630 |
static uint32_t dcr_read_dma (void *opaque, int dcrn)
|
|
| 631 | 631 |
{
|
| 632 | 632 |
ppc405_dma_t *dma; |
| 633 | 633 |
|
| ... | ... | |
| 636 | 636 |
return 0; |
| 637 | 637 |
} |
| 638 | 638 |
|
| 639 |
static void dcr_write_dma (void *opaque, int dcrn, target_ulong val)
|
|
| 639 |
static void dcr_write_dma (void *opaque, int dcrn, uint32_t val)
|
|
| 640 | 640 |
{
|
| 641 | 641 |
ppc405_dma_t *dma; |
| 642 | 642 |
|
| ... | ... | |
| 914 | 914 |
} |
| 915 | 915 |
} |
| 916 | 916 |
|
| 917 |
static target_ulong dcr_read_ocm (void *opaque, int dcrn)
|
|
| 917 |
static uint32_t dcr_read_ocm (void *opaque, int dcrn)
|
|
| 918 | 918 |
{
|
| 919 | 919 |
ppc405_ocm_t *ocm; |
| 920 |
target_ulong ret;
|
|
| 920 |
uint32_t ret;
|
|
| 921 | 921 |
|
| 922 | 922 |
ocm = opaque; |
| 923 | 923 |
switch (dcrn) {
|
| ... | ... | |
| 941 | 941 |
return ret; |
| 942 | 942 |
} |
| 943 | 943 |
|
| 944 |
static void dcr_write_ocm (void *opaque, int dcrn, target_ulong val)
|
|
| 944 |
static void dcr_write_ocm (void *opaque, int dcrn, uint32_t val)
|
|
| 945 | 945 |
{
|
| 946 | 946 |
ppc405_ocm_t *ocm; |
| 947 | 947 |
uint32_t isarc, dsarc, isacntl, dsacntl; |
| ... | ... | |
| 1578 | 1578 |
|
| 1579 | 1579 |
static void ppc40x_mal_reset (void *opaque); |
| 1580 | 1580 |
|
| 1581 |
static target_ulong dcr_read_mal (void *opaque, int dcrn)
|
|
| 1581 |
static uint32_t dcr_read_mal (void *opaque, int dcrn)
|
|
| 1582 | 1582 |
{
|
| 1583 | 1583 |
ppc40x_mal_t *mal; |
| 1584 |
target_ulong ret;
|
|
| 1584 |
uint32_t ret;
|
|
| 1585 | 1585 |
|
| 1586 | 1586 |
mal = opaque; |
| 1587 | 1587 |
switch (dcrn) {
|
| ... | ... | |
| 1650 | 1650 |
return ret; |
| 1651 | 1651 |
} |
| 1652 | 1652 |
|
| 1653 |
static void dcr_write_mal (void *opaque, int dcrn, target_ulong val)
|
|
| 1653 |
static void dcr_write_mal (void *opaque, int dcrn, uint32_t val)
|
|
| 1654 | 1654 |
{
|
| 1655 | 1655 |
ppc40x_mal_t *mal; |
| 1656 | 1656 |
int idx; |
| ... | ... | |
| 1951 | 1951 |
clk_setup(&cpc->clk_setup[PPC405CR_UART_CLK], UART_clk); |
| 1952 | 1952 |
} |
| 1953 | 1953 |
|
| 1954 |
static target_ulong dcr_read_crcpc (void *opaque, int dcrn)
|
|
| 1954 |
static uint32_t dcr_read_crcpc (void *opaque, int dcrn)
|
|
| 1955 | 1955 |
{
|
| 1956 | 1956 |
ppc405cr_cpc_t *cpc; |
| 1957 |
target_ulong ret;
|
|
| 1957 |
uint32_t ret;
|
|
| 1958 | 1958 |
|
| 1959 | 1959 |
cpc = opaque; |
| 1960 | 1960 |
switch (dcrn) {
|
| ... | ... | |
| 1991 | 1991 |
return ret; |
| 1992 | 1992 |
} |
| 1993 | 1993 |
|
| 1994 |
static void dcr_write_crcpc (void *opaque, int dcrn, target_ulong val)
|
|
| 1994 |
static void dcr_write_crcpc (void *opaque, int dcrn, uint32_t val)
|
|
| 1995 | 1995 |
{
|
| 1996 | 1996 |
ppc405cr_cpc_t *cpc; |
| 1997 | 1997 |
|
| ... | ... | |
| 2353 | 2353 |
clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk); |
| 2354 | 2354 |
} |
| 2355 | 2355 |
|
| 2356 |
static target_ulong dcr_read_epcpc (void *opaque, int dcrn)
|
|
| 2356 |
static uint32_t dcr_read_epcpc (void *opaque, int dcrn)
|
|
| 2357 | 2357 |
{
|
| 2358 | 2358 |
ppc405ep_cpc_t *cpc; |
| 2359 |
target_ulong ret;
|
|
| 2359 |
uint32_t ret;
|
|
| 2360 | 2360 |
|
| 2361 | 2361 |
cpc = opaque; |
| 2362 | 2362 |
switch (dcrn) {
|
| ... | ... | |
| 2393 | 2393 |
return ret; |
| 2394 | 2394 |
} |
| 2395 | 2395 |
|
| 2396 |
static void dcr_write_epcpc (void *opaque, int dcrn, target_ulong val)
|
|
| 2396 |
static void dcr_write_epcpc (void *opaque, int dcrn, uint32_t val)
|
|
| 2397 | 2397 |
{
|
| 2398 | 2398 |
ppc405ep_cpc_t *cpc; |
| 2399 | 2399 |
|
| b/hw/ppc4xx_devs.c | ||
|---|---|---|
| 183 | 183 |
ppcuic_trigger_irq(uic); |
| 184 | 184 |
} |
| 185 | 185 |
|
| 186 |
static target_ulong dcr_read_uic (void *opaque, int dcrn)
|
|
| 186 |
static uint32_t dcr_read_uic (void *opaque, int dcrn)
|
|
| 187 | 187 |
{
|
| 188 | 188 |
ppcuic_t *uic; |
| 189 |
target_ulong ret;
|
|
| 189 |
uint32_t ret;
|
|
| 190 | 190 |
|
| 191 | 191 |
uic = opaque; |
| 192 | 192 |
dcrn -= uic->dcr_base; |
| ... | ... | |
| 229 | 229 |
return ret; |
| 230 | 230 |
} |
| 231 | 231 |
|
| 232 |
static void dcr_write_uic (void *opaque, int dcrn, target_ulong val)
|
|
| 232 |
static void dcr_write_uic (void *opaque, int dcrn, uint32_t val)
|
|
| 233 | 233 |
{
|
| 234 | 234 |
ppcuic_t *uic; |
| 235 | 235 |
|
| 236 | 236 |
uic = opaque; |
| 237 | 237 |
dcrn -= uic->dcr_base; |
| 238 |
LOG_UIC("%s: dcr %d val " TARGET_FMT_lx "\n", __func__, dcrn, val);
|
|
| 238 |
LOG_UIC("%s: dcr %d val 0x%x\n", __func__, dcrn, val);
|
|
| 239 | 239 |
switch (dcrn) {
|
| 240 | 240 |
case DCR_UICSR: |
| 241 | 241 |
uic->uicsr &= ~val; |
| ... | ... | |
| 448 | 448 |
} |
| 449 | 449 |
} |
| 450 | 450 |
|
| 451 |
static target_ulong dcr_read_sdram (void *opaque, int dcrn)
|
|
| 451 |
static uint32_t dcr_read_sdram (void *opaque, int dcrn)
|
|
| 452 | 452 |
{
|
| 453 | 453 |
ppc4xx_sdram_t *sdram; |
| 454 |
target_ulong ret;
|
|
| 454 |
uint32_t ret;
|
|
| 455 | 455 |
|
| 456 | 456 |
sdram = opaque; |
| 457 | 457 |
switch (dcrn) {
|
| ... | ... | |
| 516 | 516 |
return ret; |
| 517 | 517 |
} |
| 518 | 518 |
|
| 519 |
static void dcr_write_sdram (void *opaque, int dcrn, target_ulong val)
|
|
| 519 |
static void dcr_write_sdram (void *opaque, int dcrn, uint32_t val)
|
|
| 520 | 520 |
{
|
| 521 | 521 |
ppc4xx_sdram_t *sdram; |
| 522 | 522 |
|
| b/linux-user/main.c | ||
|---|---|---|
| 1097 | 1097 |
} |
| 1098 | 1098 |
|
| 1099 | 1099 |
/* XXX: to be fixed */ |
| 1100 |
int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp)
|
|
| 1100 |
int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
|
|
| 1101 | 1101 |
{
|
| 1102 | 1102 |
return -1; |
| 1103 | 1103 |
} |
| 1104 | 1104 |
|
| 1105 |
int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val)
|
|
| 1105 |
int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
|
|
| 1106 | 1106 |
{
|
| 1107 | 1107 |
return -1; |
| 1108 | 1108 |
} |
| b/target-ppc/cpu.h | ||
|---|---|---|
| 795 | 795 |
} |
| 796 | 796 |
|
| 797 | 797 |
/* Device control registers */ |
| 798 |
int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp);
|
|
| 799 |
int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);
|
|
| 798 |
int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
|
|
| 799 |
int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
|
|
| 800 | 800 |
|
| 801 | 801 |
#define cpu_init cpu_ppc_init |
| 802 | 802 |
#define cpu_exec cpu_ppc_exec |
| b/target-ppc/helper.h | ||
|---|---|---|
| 359 | 359 |
DEF_HELPER_2(divs, tl, tl, tl) |
| 360 | 360 |
DEF_HELPER_2(divso, tl, tl, tl) |
| 361 | 361 |
|
| 362 |
DEF_HELPER_1(load_dcr, tl, tl);
|
|
| 363 |
DEF_HELPER_2(store_dcr, void, tl, tl)
|
|
| 362 |
DEF_HELPER_1(load_dcr, i32, i32);
|
|
| 363 |
DEF_HELPER_2(store_dcr, void, i32, i32)
|
|
| 364 | 364 |
|
| 365 | 365 |
DEF_HELPER_1(load_dump_spr, void, i32) |
| 366 | 366 |
DEF_HELPER_1(store_dump_spr, void, i32) |
| b/target-ppc/op_helper.c | ||
|---|---|---|
| 1828 | 1828 |
/* Embedded PowerPC specific helpers */ |
| 1829 | 1829 |
|
| 1830 | 1830 |
/* XXX: to be improved to check access rights when in user-mode */ |
| 1831 |
target_ulong helper_load_dcr (target_ulong dcrn)
|
|
| 1831 |
uint32_t helper_load_dcr (uint32_t dcrn)
|
|
| 1832 | 1832 |
{
|
| 1833 |
target_ulong val = 0;
|
|
| 1833 |
uint32_t val = 0;
|
|
| 1834 | 1834 |
|
| 1835 | 1835 |
if (unlikely(env->dcr_env == NULL)) {
|
| 1836 | 1836 |
qemu_log("No DCR environment\n");
|
| 1837 | 1837 |
helper_raise_exception_err(POWERPC_EXCP_PROGRAM, |
| 1838 | 1838 |
POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL); |
| 1839 | 1839 |
} else if (unlikely(ppc_dcr_read(env->dcr_env, dcrn, &val) != 0)) {
|
| 1840 |
qemu_log("DCR read error %d %03x\n", (int)dcrn, (int)dcrn);
|
|
| 1840 |
qemu_log("DCR read error %d %03x\n", dcrn, dcrn);
|
|
| 1841 | 1841 |
helper_raise_exception_err(POWERPC_EXCP_PROGRAM, |
| 1842 | 1842 |
POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG); |
| 1843 | 1843 |
} |
| 1844 | 1844 |
return val; |
| 1845 | 1845 |
} |
| 1846 | 1846 |
|
| 1847 |
void helper_store_dcr (target_ulong dcrn, target_ulong val)
|
|
| 1847 |
void helper_store_dcr (uint32_t dcrn, uint32_t val)
|
|
| 1848 | 1848 |
{
|
| 1849 | 1849 |
if (unlikely(env->dcr_env == NULL)) {
|
| 1850 | 1850 |
qemu_log("No DCR environment\n");
|
| 1851 | 1851 |
helper_raise_exception_err(POWERPC_EXCP_PROGRAM, |
| 1852 | 1852 |
POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL); |
| 1853 | 1853 |
} else if (unlikely(ppc_dcr_write(env->dcr_env, dcrn, val) != 0)) {
|
| 1854 |
qemu_log("DCR write error %d %03x\n", (int)dcrn, (int)dcrn);
|
|
| 1854 |
qemu_log("DCR write error %d %03x\n", dcrn, dcrn);
|
|
| 1855 | 1855 |
helper_raise_exception_err(POWERPC_EXCP_PROGRAM, |
| 1856 | 1856 |
POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG); |
| 1857 | 1857 |
} |
Also available in: Unified diff