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/*
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 * QEMU System Emulator header
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 *
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 * Copyright (c) 2003 Fabrice Bellard
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#ifndef VL_H
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#define VL_H
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/* we put basic includes here to avoid repeating them in device drivers */
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#include <stdlib.h>
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#include <stdio.h>
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#include <stdarg.h>
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#include <string.h>
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#include <inttypes.h>
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#include <limits.h>
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#include <time.h>
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#include <ctype.h>
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#include <errno.h>
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#include <unistd.h>
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#include <fcntl.h>
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#include <sys/stat.h>
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#ifndef O_LARGEFILE
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#define O_LARGEFILE 0
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#endif
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#ifndef O_BINARY
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#define O_BINARY 0
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#endif
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#ifndef ENOMEDIUM
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#define ENOMEDIUM ENODEV
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#endif
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#ifdef _WIN32
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#include <windows.h>
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#define fsync _commit
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#define lseek _lseeki64
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#define ENOTSUP 4096
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extern int qemu_ftruncate64(int, int64_t);
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#define ftruncate qemu_ftruncate64
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static inline char *realpath(const char *path, char *resolved_path)
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{
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    _fullpath(resolved_path, path, _MAX_PATH);
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    return resolved_path;
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}
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#define PRId64 "I64d"
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#define PRIx64 "I64x"
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#define PRIu64 "I64u"
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#define PRIo64 "I64o"
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#endif
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#ifdef QEMU_TOOL
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/* we use QEMU_TOOL in the command line tools which do not depend on
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   the target CPU type */
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#include "config-host.h"
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#include <setjmp.h>
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#include "osdep.h"
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#include "bswap.h"
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#else
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#include "audio/audio.h"
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#include "cpu.h"
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#endif /* !defined(QEMU_TOOL) */
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#ifndef glue
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#define xglue(x, y) x ## y
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#define glue(x, y) xglue(x, y)
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#define stringify(s)        tostring(s)
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#define tostring(s)        #s
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#endif
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#ifndef likely
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#if __GNUC__ < 3
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#define __builtin_expect(x, n) (x)
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#endif
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#define likely(x)   __builtin_expect(!!(x), 1)
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#define unlikely(x)   __builtin_expect(!!(x), 0)
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#endif
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#ifndef MIN
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#define MIN(a, b) (((a) < (b)) ? (a) : (b))
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#endif
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#ifndef MAX
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#define MAX(a, b) (((a) > (b)) ? (a) : (b))
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#endif
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#ifndef always_inline
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#if (__GNUC__ < 3) || defined(__APPLE__)
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#define always_inline inline
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#else
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#define always_inline __attribute__ (( always_inline )) inline
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#endif
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#endif
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/* cutils.c */
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void pstrcpy(char *buf, int buf_size, const char *str);
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char *pstrcat(char *buf, int buf_size, const char *s);
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int strstart(const char *str, const char *val, const char **ptr);
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int stristart(const char *str, const char *val, const char **ptr);
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/* vl.c */
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uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c);
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void hw_error(const char *fmt, ...);
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extern const char *bios_dir;
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extern const char *bios_name;
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extern int vm_running;
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extern const char *qemu_name;
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typedef struct vm_change_state_entry VMChangeStateEntry;
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typedef void VMChangeStateHandler(void *opaque, int running);
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typedef void VMStopHandler(void *opaque, int reason);
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VMChangeStateEntry *qemu_add_vm_change_state_handler(VMChangeStateHandler *cb,
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                                                     void *opaque);
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void qemu_del_vm_change_state_handler(VMChangeStateEntry *e);
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int qemu_add_vm_stop_handler(VMStopHandler *cb, void *opaque);
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void qemu_del_vm_stop_handler(VMStopHandler *cb, void *opaque);
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void vm_start(void);
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void vm_stop(int reason);
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typedef void QEMUResetHandler(void *opaque);
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void qemu_register_reset(QEMUResetHandler *func, void *opaque);
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void qemu_system_reset_request(void);
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void qemu_system_shutdown_request(void);
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void qemu_system_powerdown_request(void);
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#if !defined(TARGET_SPARC)
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// Please implement a power failure function to signal the OS
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#define qemu_system_powerdown() do{}while(0)
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#else
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void qemu_system_powerdown(void);
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#endif
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void main_loop_wait(int timeout);
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extern int ram_size;
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extern int bios_size;
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extern int rtc_utc;
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extern int cirrus_vga_enabled;
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extern int vmsvga_enabled;
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extern int graphic_width;
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extern int graphic_height;
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extern int graphic_depth;
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extern const char *keyboard_layout;
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extern int kqemu_allowed;
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extern int win2k_install_hack;
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extern int alt_grab;
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extern int usb_enabled;
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extern int smp_cpus;
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extern int cursor_hide;
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extern int graphic_rotate;
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extern int no_quit;
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extern int semihosting_enabled;
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extern int autostart;
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extern int old_param;
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extern const char *bootp_filename;
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#define MAX_OPTION_ROMS 16
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extern const char *option_rom[MAX_OPTION_ROMS];
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extern int nb_option_roms;
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#ifdef TARGET_SPARC
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#define MAX_PROM_ENVS 128
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extern const char *prom_envs[MAX_PROM_ENVS];
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extern unsigned int nb_prom_envs;
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#endif
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/* XXX: make it dynamic */
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#define MAX_BIOS_SIZE (4 * 1024 * 1024)
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#if defined (TARGET_PPC)
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#define BIOS_SIZE (1024 * 1024)
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#elif defined (TARGET_SPARC64)
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#define BIOS_SIZE ((512 + 32) * 1024)
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#elif defined(TARGET_MIPS)
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#define BIOS_SIZE (4 * 1024 * 1024)
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#endif
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/* keyboard/mouse support */
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#define MOUSE_EVENT_LBUTTON 0x01
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#define MOUSE_EVENT_RBUTTON 0x02
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#define MOUSE_EVENT_MBUTTON 0x04
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typedef void QEMUPutKBDEvent(void *opaque, int keycode);
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typedef void QEMUPutMouseEvent(void *opaque, int dx, int dy, int dz, int buttons_state);
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typedef struct QEMUPutMouseEntry {
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    QEMUPutMouseEvent *qemu_put_mouse_event;
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    void *qemu_put_mouse_event_opaque;
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    int qemu_put_mouse_event_absolute;
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    char *qemu_put_mouse_event_name;
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    /* used internally by qemu for handling mice */
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    struct QEMUPutMouseEntry *next;
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} QEMUPutMouseEntry;
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void qemu_add_kbd_event_handler(QEMUPutKBDEvent *func, void *opaque);
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QEMUPutMouseEntry *qemu_add_mouse_event_handler(QEMUPutMouseEvent *func,
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                                                void *opaque, int absolute,
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                                                const char *name);
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void qemu_remove_mouse_event_handler(QEMUPutMouseEntry *entry);
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void kbd_put_keycode(int keycode);
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void kbd_mouse_event(int dx, int dy, int dz, int buttons_state);
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int kbd_mouse_is_absolute(void);
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void do_info_mice(void);
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void do_mouse_set(int index);
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/* keysym is a unicode code except for special keys (see QEMU_KEY_xxx
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   constants) */
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#define QEMU_KEY_ESC1(c) ((c) | 0xe100)
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#define QEMU_KEY_BACKSPACE  0x007f
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#define QEMU_KEY_UP         QEMU_KEY_ESC1('A')
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#define QEMU_KEY_DOWN       QEMU_KEY_ESC1('B')
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#define QEMU_KEY_RIGHT      QEMU_KEY_ESC1('C')
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#define QEMU_KEY_LEFT       QEMU_KEY_ESC1('D')
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#define QEMU_KEY_HOME       QEMU_KEY_ESC1(1)
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#define QEMU_KEY_END        QEMU_KEY_ESC1(4)
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#define QEMU_KEY_PAGEUP     QEMU_KEY_ESC1(5)
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#define QEMU_KEY_PAGEDOWN   QEMU_KEY_ESC1(6)
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#define QEMU_KEY_DELETE     QEMU_KEY_ESC1(3)
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#define QEMU_KEY_CTRL_UP         0xe400
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#define QEMU_KEY_CTRL_DOWN       0xe401
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#define QEMU_KEY_CTRL_LEFT       0xe402
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#define QEMU_KEY_CTRL_RIGHT      0xe403
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#define QEMU_KEY_CTRL_HOME       0xe404
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#define QEMU_KEY_CTRL_END        0xe405
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#define QEMU_KEY_CTRL_PAGEUP     0xe406
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#define QEMU_KEY_CTRL_PAGEDOWN   0xe407
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void kbd_put_keysym(int keysym);
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/* async I/O support */
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typedef void IOReadHandler(void *opaque, const uint8_t *buf, int size);
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typedef int IOCanRWHandler(void *opaque);
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typedef void IOHandler(void *opaque);
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int qemu_set_fd_handler2(int fd,
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                         IOCanRWHandler *fd_read_poll,
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                         IOHandler *fd_read,
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                         IOHandler *fd_write,
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                         void *opaque);
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int qemu_set_fd_handler(int fd,
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                        IOHandler *fd_read,
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                        IOHandler *fd_write,
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                        void *opaque);
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/* Polling handling */
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/* return TRUE if no sleep should be done afterwards */
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typedef int PollingFunc(void *opaque);
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int qemu_add_polling_cb(PollingFunc *func, void *opaque);
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void qemu_del_polling_cb(PollingFunc *func, void *opaque);
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#ifdef _WIN32
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/* Wait objects handling */
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typedef void WaitObjectFunc(void *opaque);
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int qemu_add_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
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void qemu_del_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
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#endif
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typedef struct QEMUBH QEMUBH;
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/* character device */
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#define CHR_EVENT_BREAK 0 /* serial break char */
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#define CHR_EVENT_FOCUS 1 /* focus to this terminal (modal input needed) */
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#define CHR_EVENT_RESET 2 /* new connection established */
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#define CHR_IOCTL_SERIAL_SET_PARAMS   1
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typedef struct {
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    int speed;
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    int parity;
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    int data_bits;
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    int stop_bits;
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} QEMUSerialSetParams;
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#define CHR_IOCTL_SERIAL_SET_BREAK    2
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#define CHR_IOCTL_PP_READ_DATA        3
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#define CHR_IOCTL_PP_WRITE_DATA       4
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#define CHR_IOCTL_PP_READ_CONTROL     5
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#define CHR_IOCTL_PP_WRITE_CONTROL    6
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#define CHR_IOCTL_PP_READ_STATUS      7
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#define CHR_IOCTL_PP_EPP_READ_ADDR    8
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#define CHR_IOCTL_PP_EPP_READ         9
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#define CHR_IOCTL_PP_EPP_WRITE_ADDR  10
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#define CHR_IOCTL_PP_EPP_WRITE       11
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typedef void IOEventHandler(void *opaque, int event);
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typedef struct CharDriverState {
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    int (*chr_write)(struct CharDriverState *s, const uint8_t *buf, int len);
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    void (*chr_update_read_handler)(struct CharDriverState *s);
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    int (*chr_ioctl)(struct CharDriverState *s, int cmd, void *arg);
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    IOEventHandler *chr_event;
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    IOCanRWHandler *chr_can_read;
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    IOReadHandler *chr_read;
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    void *handler_opaque;
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    void (*chr_send_event)(struct CharDriverState *chr, int event);
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    void (*chr_close)(struct CharDriverState *chr);
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    void *opaque;
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    int focus;
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    QEMUBH *bh;
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} CharDriverState;
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CharDriverState *qemu_chr_open(const char *filename);
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void qemu_chr_printf(CharDriverState *s, const char *fmt, ...);
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int qemu_chr_write(CharDriverState *s, const uint8_t *buf, int len);
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void qemu_chr_send_event(CharDriverState *s, int event);
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void qemu_chr_add_handlers(CharDriverState *s,
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                           IOCanRWHandler *fd_can_read,
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                           IOReadHandler *fd_read,
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                           IOEventHandler *fd_event,
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                           void *opaque);
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int qemu_chr_ioctl(CharDriverState *s, int cmd, void *arg);
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void qemu_chr_reset(CharDriverState *s);
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int qemu_chr_can_read(CharDriverState *s);
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void qemu_chr_read(CharDriverState *s, uint8_t *buf, int len);
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/* consoles */
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typedef struct DisplayState DisplayState;
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typedef struct TextConsole TextConsole;
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typedef void (*vga_hw_update_ptr)(void *);
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typedef void (*vga_hw_invalidate_ptr)(void *);
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typedef void (*vga_hw_screen_dump_ptr)(void *, const char *);
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TextConsole *graphic_console_init(DisplayState *ds, vga_hw_update_ptr update,
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                                  vga_hw_invalidate_ptr invalidate,
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                                  vga_hw_screen_dump_ptr screen_dump,
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                                  void *opaque);
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void vga_hw_update(void);
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void vga_hw_invalidate(void);
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void vga_hw_screen_dump(const char *filename);
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int is_graphic_console(void);
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CharDriverState *text_console_init(DisplayState *ds, const char *p);
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void console_select(unsigned int index);
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void console_color_init(DisplayState *ds);
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/* serial ports */
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#define MAX_SERIAL_PORTS 4
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extern CharDriverState *serial_hds[MAX_SERIAL_PORTS];
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/* parallel ports */
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#define MAX_PARALLEL_PORTS 3
388 6508fe59 bellard
389 6508fe59 bellard
extern CharDriverState *parallel_hds[MAX_PARALLEL_PORTS];
390 6508fe59 bellard
391 5867c88a ths
struct ParallelIOArg {
392 5867c88a ths
    void *buffer;
393 5867c88a ths
    int count;
394 5867c88a ths
};
395 5867c88a ths
396 7c9d8e07 bellard
/* VLANs support */
397 7c9d8e07 bellard
398 7c9d8e07 bellard
typedef struct VLANClientState VLANClientState;
399 7c9d8e07 bellard
400 7c9d8e07 bellard
struct VLANClientState {
401 7c9d8e07 bellard
    IOReadHandler *fd_read;
402 d861b05e pbrook
    /* Packets may still be sent if this returns zero.  It's used to
403 d861b05e pbrook
       rate-limit the slirp code.  */
404 d861b05e pbrook
    IOCanRWHandler *fd_can_read;
405 7c9d8e07 bellard
    void *opaque;
406 7c9d8e07 bellard
    struct VLANClientState *next;
407 7c9d8e07 bellard
    struct VLANState *vlan;
408 7c9d8e07 bellard
    char info_str[256];
409 7c9d8e07 bellard
};
410 7c9d8e07 bellard
411 7c9d8e07 bellard
typedef struct VLANState {
412 7c9d8e07 bellard
    int id;
413 7c9d8e07 bellard
    VLANClientState *first_client;
414 7c9d8e07 bellard
    struct VLANState *next;
415 833c7174 blueswir1
    unsigned int nb_guest_devs, nb_host_devs;
416 7c9d8e07 bellard
} VLANState;
417 7c9d8e07 bellard
418 7c9d8e07 bellard
VLANState *qemu_find_vlan(int id);
419 7c9d8e07 bellard
VLANClientState *qemu_new_vlan_client(VLANState *vlan,
420 d861b05e pbrook
                                      IOReadHandler *fd_read,
421 d861b05e pbrook
                                      IOCanRWHandler *fd_can_read,
422 d861b05e pbrook
                                      void *opaque);
423 d861b05e pbrook
int qemu_can_send_packet(VLANClientState *vc);
424 7c9d8e07 bellard
void qemu_send_packet(VLANClientState *vc, const uint8_t *buf, int size);
425 d861b05e pbrook
void qemu_handler_true(void *opaque);
426 7c9d8e07 bellard
427 7c9d8e07 bellard
void do_info_network(void);
428 7c9d8e07 bellard
429 7fb843f8 bellard
/* TAP win32 */
430 7fb843f8 bellard
int tap_win32_init(VLANState *vlan, const char *ifname);
431 7fb843f8 bellard
432 7c9d8e07 bellard
/* NIC info */
433 c4b1fcc0 bellard
434 c4b1fcc0 bellard
#define MAX_NICS 8
435 c4b1fcc0 bellard
436 7c9d8e07 bellard
typedef struct NICInfo {
437 c4b1fcc0 bellard
    uint8_t macaddr[6];
438 a41b2ff2 pbrook
    const char *model;
439 7c9d8e07 bellard
    VLANState *vlan;
440 7c9d8e07 bellard
} NICInfo;
441 c4b1fcc0 bellard
442 c4b1fcc0 bellard
extern int nb_nics;
443 7c9d8e07 bellard
extern NICInfo nd_table[MAX_NICS];
444 8a7ddc38 bellard
445 31a60e22 blueswir1
/* SLIRP */
446 31a60e22 blueswir1
void do_info_slirp(void);
447 31a60e22 blueswir1
448 8a7ddc38 bellard
/* timers */
449 8a7ddc38 bellard
450 8a7ddc38 bellard
typedef struct QEMUClock QEMUClock;
451 8a7ddc38 bellard
typedef struct QEMUTimer QEMUTimer;
452 8a7ddc38 bellard
typedef void QEMUTimerCB(void *opaque);
453 8a7ddc38 bellard
454 8a7ddc38 bellard
/* The real time clock should be used only for stuff which does not
455 8a7ddc38 bellard
   change the virtual machine state, as it is run even if the virtual
456 69b91039 bellard
   machine is stopped. The real time clock has a frequency of 1000
457 8a7ddc38 bellard
   Hz. */
458 8a7ddc38 bellard
extern QEMUClock *rt_clock;
459 8a7ddc38 bellard
460 e80cfcfc bellard
/* The virtual clock is only run during the emulation. It is stopped
461 8a7ddc38 bellard
   when the virtual machine is stopped. Virtual timers use a high
462 8a7ddc38 bellard
   precision clock, usually cpu cycles (use ticks_per_sec). */
463 8a7ddc38 bellard
extern QEMUClock *vm_clock;
464 8a7ddc38 bellard
465 8a7ddc38 bellard
int64_t qemu_get_clock(QEMUClock *clock);
466 8a7ddc38 bellard
467 8a7ddc38 bellard
QEMUTimer *qemu_new_timer(QEMUClock *clock, QEMUTimerCB *cb, void *opaque);
468 8a7ddc38 bellard
void qemu_free_timer(QEMUTimer *ts);
469 8a7ddc38 bellard
void qemu_del_timer(QEMUTimer *ts);
470 8a7ddc38 bellard
void qemu_mod_timer(QEMUTimer *ts, int64_t expire_time);
471 8a7ddc38 bellard
int qemu_timer_pending(QEMUTimer *ts);
472 8a7ddc38 bellard
473 8a7ddc38 bellard
extern int64_t ticks_per_sec;
474 8a7ddc38 bellard
475 1dce7c3c bellard
int64_t cpu_get_ticks(void);
476 8a7ddc38 bellard
void cpu_enable_ticks(void);
477 8a7ddc38 bellard
void cpu_disable_ticks(void);
478 8a7ddc38 bellard
479 8a7ddc38 bellard
/* VM Load/Save */
480 8a7ddc38 bellard
481 faea38e7 bellard
typedef struct QEMUFile QEMUFile;
482 8a7ddc38 bellard
483 faea38e7 bellard
QEMUFile *qemu_fopen(const char *filename, const char *mode);
484 faea38e7 bellard
void qemu_fflush(QEMUFile *f);
485 faea38e7 bellard
void qemu_fclose(QEMUFile *f);
486 8a7ddc38 bellard
void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, int size);
487 8a7ddc38 bellard
void qemu_put_byte(QEMUFile *f, int v);
488 8a7ddc38 bellard
void qemu_put_be16(QEMUFile *f, unsigned int v);
489 8a7ddc38 bellard
void qemu_put_be32(QEMUFile *f, unsigned int v);
490 8a7ddc38 bellard
void qemu_put_be64(QEMUFile *f, uint64_t v);
491 8a7ddc38 bellard
int qemu_get_buffer(QEMUFile *f, uint8_t *buf, int size);
492 8a7ddc38 bellard
int qemu_get_byte(QEMUFile *f);
493 8a7ddc38 bellard
unsigned int qemu_get_be16(QEMUFile *f);
494 8a7ddc38 bellard
unsigned int qemu_get_be32(QEMUFile *f);
495 8a7ddc38 bellard
uint64_t qemu_get_be64(QEMUFile *f);
496 8a7ddc38 bellard
497 8a7ddc38 bellard
static inline void qemu_put_be64s(QEMUFile *f, const uint64_t *pv)
498 8a7ddc38 bellard
{
499 8a7ddc38 bellard
    qemu_put_be64(f, *pv);
500 8a7ddc38 bellard
}
501 8a7ddc38 bellard
502 8a7ddc38 bellard
static inline void qemu_put_be32s(QEMUFile *f, const uint32_t *pv)
503 8a7ddc38 bellard
{
504 8a7ddc38 bellard
    qemu_put_be32(f, *pv);
505 8a7ddc38 bellard
}
506 8a7ddc38 bellard
507 8a7ddc38 bellard
static inline void qemu_put_be16s(QEMUFile *f, const uint16_t *pv)
508 8a7ddc38 bellard
{
509 8a7ddc38 bellard
    qemu_put_be16(f, *pv);
510 8a7ddc38 bellard
}
511 8a7ddc38 bellard
512 8a7ddc38 bellard
static inline void qemu_put_8s(QEMUFile *f, const uint8_t *pv)
513 8a7ddc38 bellard
{
514 8a7ddc38 bellard
    qemu_put_byte(f, *pv);
515 8a7ddc38 bellard
}
516 8a7ddc38 bellard
517 8a7ddc38 bellard
static inline void qemu_get_be64s(QEMUFile *f, uint64_t *pv)
518 8a7ddc38 bellard
{
519 8a7ddc38 bellard
    *pv = qemu_get_be64(f);
520 8a7ddc38 bellard
}
521 8a7ddc38 bellard
522 8a7ddc38 bellard
static inline void qemu_get_be32s(QEMUFile *f, uint32_t *pv)
523 8a7ddc38 bellard
{
524 8a7ddc38 bellard
    *pv = qemu_get_be32(f);
525 8a7ddc38 bellard
}
526 8a7ddc38 bellard
527 8a7ddc38 bellard
static inline void qemu_get_be16s(QEMUFile *f, uint16_t *pv)
528 8a7ddc38 bellard
{
529 8a7ddc38 bellard
    *pv = qemu_get_be16(f);
530 8a7ddc38 bellard
}
531 8a7ddc38 bellard
532 8a7ddc38 bellard
static inline void qemu_get_8s(QEMUFile *f, uint8_t *pv)
533 8a7ddc38 bellard
{
534 8a7ddc38 bellard
    *pv = qemu_get_byte(f);
535 8a7ddc38 bellard
}
536 8a7ddc38 bellard
537 c27004ec bellard
#if TARGET_LONG_BITS == 64
538 c27004ec bellard
#define qemu_put_betl qemu_put_be64
539 c27004ec bellard
#define qemu_get_betl qemu_get_be64
540 c27004ec bellard
#define qemu_put_betls qemu_put_be64s
541 c27004ec bellard
#define qemu_get_betls qemu_get_be64s
542 c27004ec bellard
#else
543 c27004ec bellard
#define qemu_put_betl qemu_put_be32
544 c27004ec bellard
#define qemu_get_betl qemu_get_be32
545 c27004ec bellard
#define qemu_put_betls qemu_put_be32s
546 c27004ec bellard
#define qemu_get_betls qemu_get_be32s
547 c27004ec bellard
#endif
548 c27004ec bellard
549 8a7ddc38 bellard
int64_t qemu_ftell(QEMUFile *f);
550 8a7ddc38 bellard
int64_t qemu_fseek(QEMUFile *f, int64_t pos, int whence);
551 8a7ddc38 bellard
552 8a7ddc38 bellard
typedef void SaveStateHandler(QEMUFile *f, void *opaque);
553 8a7ddc38 bellard
typedef int LoadStateHandler(QEMUFile *f, void *opaque, int version_id);
554 8a7ddc38 bellard
555 5fafdf24 ths
int register_savevm(const char *idstr,
556 5fafdf24 ths
                    int instance_id,
557 8a7ddc38 bellard
                    int version_id,
558 8a7ddc38 bellard
                    SaveStateHandler *save_state,
559 8a7ddc38 bellard
                    LoadStateHandler *load_state,
560 8a7ddc38 bellard
                    void *opaque);
561 8a7ddc38 bellard
void qemu_get_timer(QEMUFile *f, QEMUTimer *ts);
562 8a7ddc38 bellard
void qemu_put_timer(QEMUFile *f, QEMUTimer *ts);
563 c4b1fcc0 bellard
564 6a00d601 bellard
void cpu_save(QEMUFile *f, void *opaque);
565 6a00d601 bellard
int cpu_load(QEMUFile *f, void *opaque, int version_id);
566 6a00d601 bellard
567 faea38e7 bellard
void do_savevm(const char *name);
568 faea38e7 bellard
void do_loadvm(const char *name);
569 faea38e7 bellard
void do_delvm(const char *name);
570 faea38e7 bellard
void do_info_snapshots(void);
571 faea38e7 bellard
572 83f64091 bellard
/* bottom halves */
573 83f64091 bellard
typedef void QEMUBHFunc(void *opaque);
574 83f64091 bellard
575 83f64091 bellard
QEMUBH *qemu_bh_new(QEMUBHFunc *cb, void *opaque);
576 83f64091 bellard
void qemu_bh_schedule(QEMUBH *bh);
577 83f64091 bellard
void qemu_bh_cancel(QEMUBH *bh);
578 83f64091 bellard
void qemu_bh_delete(QEMUBH *bh);
579 6eb5733a bellard
int qemu_bh_poll(void);
580 83f64091 bellard
581 fc01f7e7 bellard
/* block.c */
582 fc01f7e7 bellard
typedef struct BlockDriverState BlockDriverState;
583 ea2384d3 bellard
typedef struct BlockDriver BlockDriver;
584 ea2384d3 bellard
585 ea2384d3 bellard
extern BlockDriver bdrv_raw;
586 19cb3738 bellard
extern BlockDriver bdrv_host_device;
587 ea2384d3 bellard
extern BlockDriver bdrv_cow;
588 ea2384d3 bellard
extern BlockDriver bdrv_qcow;
589 ea2384d3 bellard
extern BlockDriver bdrv_vmdk;
590 3c56521b bellard
extern BlockDriver bdrv_cloop;
591 585d0ed9 bellard
extern BlockDriver bdrv_dmg;
592 a8753c34 bellard
extern BlockDriver bdrv_bochs;
593 6a0f9e82 bellard
extern BlockDriver bdrv_vpc;
594 de167e41 bellard
extern BlockDriver bdrv_vvfat;
595 faea38e7 bellard
extern BlockDriver bdrv_qcow2;
596 6ada7453 ths
extern BlockDriver bdrv_parallels;
597 faea38e7 bellard
598 faea38e7 bellard
typedef struct BlockDriverInfo {
599 faea38e7 bellard
    /* in bytes, 0 if irrelevant */
600 5fafdf24 ths
    int cluster_size;
601 faea38e7 bellard
    /* offset at which the VM state can be saved (0 if not possible) */
602 5fafdf24 ths
    int64_t vm_state_offset;
603 faea38e7 bellard
} BlockDriverInfo;
604 faea38e7 bellard
605 faea38e7 bellard
typedef struct QEMUSnapshotInfo {
606 faea38e7 bellard
    char id_str[128]; /* unique snapshot id */
607 faea38e7 bellard
    /* the following fields are informative. They are not needed for
608 faea38e7 bellard
       the consistency of the snapshot */
609 faea38e7 bellard
    char name[256]; /* user choosen name */
610 faea38e7 bellard
    uint32_t vm_state_size; /* VM state info size */
611 faea38e7 bellard
    uint32_t date_sec; /* UTC date of the snapshot */
612 faea38e7 bellard
    uint32_t date_nsec;
613 faea38e7 bellard
    uint64_t vm_clock_nsec; /* VM clock relative to boot */
614 faea38e7 bellard
} QEMUSnapshotInfo;
615 ea2384d3 bellard
616 83f64091 bellard
#define BDRV_O_RDONLY      0x0000
617 83f64091 bellard
#define BDRV_O_RDWR        0x0002
618 83f64091 bellard
#define BDRV_O_ACCESS      0x0003
619 83f64091 bellard
#define BDRV_O_CREAT       0x0004 /* create an empty file */
620 83f64091 bellard
#define BDRV_O_SNAPSHOT    0x0008 /* open the file read only and save writes in a snapshot */
621 83f64091 bellard
#define BDRV_O_FILE        0x0010 /* open as a raw file (do not try to
622 83f64091 bellard
                                     use a disk image format on top of
623 83f64091 bellard
                                     it (default for
624 83f64091 bellard
                                     bdrv_file_open()) */
625 83f64091 bellard
626 ea2384d3 bellard
void bdrv_init(void);
627 ea2384d3 bellard
BlockDriver *bdrv_find_format(const char *format_name);
628 5fafdf24 ths
int bdrv_create(BlockDriver *drv,
629 ea2384d3 bellard
                const char *filename, int64_t size_in_sectors,
630 ea2384d3 bellard
                const char *backing_file, int flags);
631 c4b1fcc0 bellard
BlockDriverState *bdrv_new(const char *device_name);
632 c4b1fcc0 bellard
void bdrv_delete(BlockDriverState *bs);
633 83f64091 bellard
int bdrv_file_open(BlockDriverState **pbs, const char *filename, int flags);
634 83f64091 bellard
int bdrv_open(BlockDriverState *bs, const char *filename, int flags);
635 83f64091 bellard
int bdrv_open2(BlockDriverState *bs, const char *filename, int flags,
636 ea2384d3 bellard
               BlockDriver *drv);
637 fc01f7e7 bellard
void bdrv_close(BlockDriverState *bs);
638 5fafdf24 ths
int bdrv_read(BlockDriverState *bs, int64_t sector_num,
639 fc01f7e7 bellard
              uint8_t *buf, int nb_sectors);
640 5fafdf24 ths
int bdrv_write(BlockDriverState *bs, int64_t sector_num,
641 fc01f7e7 bellard
               const uint8_t *buf, int nb_sectors);
642 5fafdf24 ths
int bdrv_pread(BlockDriverState *bs, int64_t offset,
643 83f64091 bellard
               void *buf, int count);
644 5fafdf24 ths
int bdrv_pwrite(BlockDriverState *bs, int64_t offset,
645 83f64091 bellard
                const void *buf, int count);
646 83f64091 bellard
int bdrv_truncate(BlockDriverState *bs, int64_t offset);
647 83f64091 bellard
int64_t bdrv_getlength(BlockDriverState *bs);
648 fc01f7e7 bellard
void bdrv_get_geometry(BlockDriverState *bs, int64_t *nb_sectors_ptr);
649 33e3963e bellard
int bdrv_commit(BlockDriverState *bs);
650 77fef8c1 bellard
void bdrv_set_boot_sector(BlockDriverState *bs, const uint8_t *data, int size);
651 83f64091 bellard
/* async block I/O */
652 83f64091 bellard
typedef struct BlockDriverAIOCB BlockDriverAIOCB;
653 83f64091 bellard
typedef void BlockDriverCompletionFunc(void *opaque, int ret);
654 83f64091 bellard
655 ce1a14dc pbrook
BlockDriverAIOCB *bdrv_aio_read(BlockDriverState *bs, int64_t sector_num,
656 ce1a14dc pbrook
                                uint8_t *buf, int nb_sectors,
657 ce1a14dc pbrook
                                BlockDriverCompletionFunc *cb, void *opaque);
658 ce1a14dc pbrook
BlockDriverAIOCB *bdrv_aio_write(BlockDriverState *bs, int64_t sector_num,
659 ce1a14dc pbrook
                                 const uint8_t *buf, int nb_sectors,
660 ce1a14dc pbrook
                                 BlockDriverCompletionFunc *cb, void *opaque);
661 83f64091 bellard
void bdrv_aio_cancel(BlockDriverAIOCB *acb);
662 83f64091 bellard
663 83f64091 bellard
void qemu_aio_init(void);
664 83f64091 bellard
void qemu_aio_poll(void);
665 6192bc37 pbrook
void qemu_aio_flush(void);
666 83f64091 bellard
void qemu_aio_wait_start(void);
667 83f64091 bellard
void qemu_aio_wait(void);
668 83f64091 bellard
void qemu_aio_wait_end(void);
669 83f64091 bellard
670 2bac6019 balrog
int qemu_key_check(BlockDriverState *bs, const char *name);
671 2bac6019 balrog
672 7a6cba61 pbrook
/* Ensure contents are flushed to disk.  */
673 7a6cba61 pbrook
void bdrv_flush(BlockDriverState *bs);
674 33e3963e bellard
675 c4b1fcc0 bellard
#define BDRV_TYPE_HD     0
676 c4b1fcc0 bellard
#define BDRV_TYPE_CDROM  1
677 c4b1fcc0 bellard
#define BDRV_TYPE_FLOPPY 2
678 4dbb0f50 ths
#define BIOS_ATA_TRANSLATION_AUTO   0
679 4dbb0f50 ths
#define BIOS_ATA_TRANSLATION_NONE   1
680 4dbb0f50 ths
#define BIOS_ATA_TRANSLATION_LBA    2
681 4dbb0f50 ths
#define BIOS_ATA_TRANSLATION_LARGE  3
682 4dbb0f50 ths
#define BIOS_ATA_TRANSLATION_RECHS  4
683 c4b1fcc0 bellard
684 5fafdf24 ths
void bdrv_set_geometry_hint(BlockDriverState *bs,
685 c4b1fcc0 bellard
                            int cyls, int heads, int secs);
686 c4b1fcc0 bellard
void bdrv_set_type_hint(BlockDriverState *bs, int type);
687 46d4767d bellard
void bdrv_set_translation_hint(BlockDriverState *bs, int translation);
688 5fafdf24 ths
void bdrv_get_geometry_hint(BlockDriverState *bs,
689 c4b1fcc0 bellard
                            int *pcyls, int *pheads, int *psecs);
690 c4b1fcc0 bellard
int bdrv_get_type_hint(BlockDriverState *bs);
691 46d4767d bellard
int bdrv_get_translation_hint(BlockDriverState *bs);
692 c4b1fcc0 bellard
int bdrv_is_removable(BlockDriverState *bs);
693 c4b1fcc0 bellard
int bdrv_is_read_only(BlockDriverState *bs);
694 c4b1fcc0 bellard
int bdrv_is_inserted(BlockDriverState *bs);
695 19cb3738 bellard
int bdrv_media_changed(BlockDriverState *bs);
696 c4b1fcc0 bellard
int bdrv_is_locked(BlockDriverState *bs);
697 c4b1fcc0 bellard
void bdrv_set_locked(BlockDriverState *bs, int locked);
698 19cb3738 bellard
void bdrv_eject(BlockDriverState *bs, int eject_flag);
699 5fafdf24 ths
void bdrv_set_change_cb(BlockDriverState *bs,
700 c4b1fcc0 bellard
                        void (*change_cb)(void *opaque), void *opaque);
701 ea2384d3 bellard
void bdrv_get_format(BlockDriverState *bs, char *buf, int buf_size);
702 c4b1fcc0 bellard
void bdrv_info(void);
703 c4b1fcc0 bellard
BlockDriverState *bdrv_find(const char *name);
704 82c643ff bellard
void bdrv_iterate(void (*it)(void *opaque, const char *name), void *opaque);
705 ea2384d3 bellard
int bdrv_is_encrypted(BlockDriverState *bs);
706 ea2384d3 bellard
int bdrv_set_key(BlockDriverState *bs, const char *key);
707 5fafdf24 ths
void bdrv_iterate_format(void (*it)(void *opaque, const char *name),
708 ea2384d3 bellard
                         void *opaque);
709 ea2384d3 bellard
const char *bdrv_get_device_name(BlockDriverState *bs);
710 5fafdf24 ths
int bdrv_write_compressed(BlockDriverState *bs, int64_t sector_num,
711 faea38e7 bellard
                          const uint8_t *buf, int nb_sectors);
712 faea38e7 bellard
int bdrv_get_info(BlockDriverState *bs, BlockDriverInfo *bdi);
713 c4b1fcc0 bellard
714 5fafdf24 ths
void bdrv_get_backing_filename(BlockDriverState *bs,
715 83f64091 bellard
                               char *filename, int filename_size);
716 5fafdf24 ths
int bdrv_snapshot_create(BlockDriverState *bs,
717 faea38e7 bellard
                         QEMUSnapshotInfo *sn_info);
718 5fafdf24 ths
int bdrv_snapshot_goto(BlockDriverState *bs,
719 faea38e7 bellard
                       const char *snapshot_id);
720 faea38e7 bellard
int bdrv_snapshot_delete(BlockDriverState *bs, const char *snapshot_id);
721 5fafdf24 ths
int bdrv_snapshot_list(BlockDriverState *bs,
722 faea38e7 bellard
                       QEMUSnapshotInfo **psn_info);
723 faea38e7 bellard
char *bdrv_snapshot_dump(char *buf, int buf_size, QEMUSnapshotInfo *sn);
724 faea38e7 bellard
725 faea38e7 bellard
char *get_human_readable_size(char *buf, int buf_size, int64_t size);
726 83f64091 bellard
int path_is_absolute(const char *path);
727 83f64091 bellard
void path_combine(char *dest, int dest_size,
728 83f64091 bellard
                  const char *base_path,
729 83f64091 bellard
                  const char *filename);
730 ea2384d3 bellard
731 ea2384d3 bellard
#ifndef QEMU_TOOL
732 54fa5af5 bellard
733 5fafdf24 ths
typedef void QEMUMachineInitFunc(int ram_size, int vga_ram_size,
734 6ac0e82d balrog
                                 const char *boot_device,
735 54fa5af5 bellard
             DisplayState *ds, const char **fd_filename, int snapshot,
736 54fa5af5 bellard
             const char *kernel_filename, const char *kernel_cmdline,
737 94fc95cd j_mayer
             const char *initrd_filename, const char *cpu_model);
738 54fa5af5 bellard
739 54fa5af5 bellard
typedef struct QEMUMachine {
740 54fa5af5 bellard
    const char *name;
741 54fa5af5 bellard
    const char *desc;
742 54fa5af5 bellard
    QEMUMachineInitFunc *init;
743 54fa5af5 bellard
    struct QEMUMachine *next;
744 54fa5af5 bellard
} QEMUMachine;
745 54fa5af5 bellard
746 54fa5af5 bellard
int qemu_register_machine(QEMUMachine *m);
747 54fa5af5 bellard
748 54fa5af5 bellard
typedef void SetIRQFunc(void *opaque, int irq_num, int level);
749 54fa5af5 bellard
750 d537cf6c pbrook
#include "hw/irq.h"
751 d537cf6c pbrook
752 26aa7d72 bellard
/* ISA bus */
753 26aa7d72 bellard
754 26aa7d72 bellard
extern target_phys_addr_t isa_mem_base;
755 26aa7d72 bellard
756 26aa7d72 bellard
typedef void (IOPortWriteFunc)(void *opaque, uint32_t address, uint32_t data);
757 26aa7d72 bellard
typedef uint32_t (IOPortReadFunc)(void *opaque, uint32_t address);
758 26aa7d72 bellard
759 5fafdf24 ths
int register_ioport_read(int start, int length, int size,
760 26aa7d72 bellard
                         IOPortReadFunc *func, void *opaque);
761 5fafdf24 ths
int register_ioport_write(int start, int length, int size,
762 26aa7d72 bellard
                          IOPortWriteFunc *func, void *opaque);
763 69b91039 bellard
void isa_unassign_ioport(int start, int length);
764 69b91039 bellard
765 aef445bd pbrook
void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
766 aef445bd pbrook
767 69b91039 bellard
/* PCI bus */
768 69b91039 bellard
769 69b91039 bellard
extern target_phys_addr_t pci_mem_base;
770 69b91039 bellard
771 46e50e9d bellard
typedef struct PCIBus PCIBus;
772 69b91039 bellard
typedef struct PCIDevice PCIDevice;
773 69b91039 bellard
774 5fafdf24 ths
typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
775 69b91039 bellard
                                uint32_t address, uint32_t data, int len);
776 5fafdf24 ths
typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
777 69b91039 bellard
                                   uint32_t address, int len);
778 5fafdf24 ths
typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
779 69b91039 bellard
                                uint32_t addr, uint32_t size, int type);
780 69b91039 bellard
781 69b91039 bellard
#define PCI_ADDRESS_SPACE_MEM                0x00
782 69b91039 bellard
#define PCI_ADDRESS_SPACE_IO                0x01
783 69b91039 bellard
#define PCI_ADDRESS_SPACE_MEM_PREFETCH        0x08
784 69b91039 bellard
785 69b91039 bellard
typedef struct PCIIORegion {
786 5768f5ac bellard
    uint32_t addr; /* current PCI mapping address. -1 means not mapped */
787 69b91039 bellard
    uint32_t size;
788 69b91039 bellard
    uint8_t type;
789 69b91039 bellard
    PCIMapIORegionFunc *map_func;
790 69b91039 bellard
} PCIIORegion;
791 69b91039 bellard
792 8a8696a3 bellard
#define PCI_ROM_SLOT 6
793 8a8696a3 bellard
#define PCI_NUM_REGIONS 7
794 502a5395 pbrook
795 502a5395 pbrook
#define PCI_DEVICES_MAX 64
796 502a5395 pbrook
797 502a5395 pbrook
#define PCI_VENDOR_ID                0x00        /* 16 bits */
798 502a5395 pbrook
#define PCI_DEVICE_ID                0x02        /* 16 bits */
799 502a5395 pbrook
#define PCI_COMMAND                0x04        /* 16 bits */
800 502a5395 pbrook
#define  PCI_COMMAND_IO                0x1        /* Enable response in I/O space */
801 502a5395 pbrook
#define  PCI_COMMAND_MEMORY        0x2        /* Enable response in Memory space */
802 502a5395 pbrook
#define PCI_CLASS_DEVICE        0x0a    /* Device class */
803 502a5395 pbrook
#define PCI_INTERRUPT_LINE        0x3c        /* 8 bits */
804 502a5395 pbrook
#define PCI_INTERRUPT_PIN        0x3d        /* 8 bits */
805 502a5395 pbrook
#define PCI_MIN_GNT                0x3e        /* 8 bits */
806 502a5395 pbrook
#define PCI_MAX_LAT                0x3f        /* 8 bits */
807 502a5395 pbrook
808 69b91039 bellard
struct PCIDevice {
809 69b91039 bellard
    /* PCI config space */
810 69b91039 bellard
    uint8_t config[256];
811 69b91039 bellard
812 69b91039 bellard
    /* the following fields are read only */
813 46e50e9d bellard
    PCIBus *bus;
814 69b91039 bellard
    int devfn;
815 69b91039 bellard
    char name[64];
816 8a8696a3 bellard
    PCIIORegion io_regions[PCI_NUM_REGIONS];
817 3b46e624 ths
818 69b91039 bellard
    /* do not access the following fields */
819 69b91039 bellard
    PCIConfigReadFunc *config_read;
820 69b91039 bellard
    PCIConfigWriteFunc *config_write;
821 502a5395 pbrook
    /* ??? This is a PC-specific hack, and should be removed.  */
822 5768f5ac bellard
    int irq_index;
823 d2b59317 pbrook
824 d537cf6c pbrook
    /* IRQ objects for the INTA-INTD pins.  */
825 d537cf6c pbrook
    qemu_irq *irq;
826 d537cf6c pbrook
827 d2b59317 pbrook
    /* Current IRQ levels.  Used internally by the generic PCI code.  */
828 d2b59317 pbrook
    int irq_state[4];
829 69b91039 bellard
};
830 69b91039 bellard
831 46e50e9d bellard
PCIDevice *pci_register_device(PCIBus *bus, const char *name,
832 46e50e9d bellard
                               int instance_size, int devfn,
833 5fafdf24 ths
                               PCIConfigReadFunc *config_read,
834 69b91039 bellard
                               PCIConfigWriteFunc *config_write);
835 69b91039 bellard
836 5fafdf24 ths
void pci_register_io_region(PCIDevice *pci_dev, int region_num,
837 5fafdf24 ths
                            uint32_t size, int type,
838 69b91039 bellard
                            PCIMapIORegionFunc *map_func);
839 69b91039 bellard
840 5fafdf24 ths
uint32_t pci_default_read_config(PCIDevice *d,
841 5768f5ac bellard
                                 uint32_t address, int len);
842 5fafdf24 ths
void pci_default_write_config(PCIDevice *d,
843 5768f5ac bellard
                              uint32_t address, uint32_t val, int len);
844 89b6b508 bellard
void pci_device_save(PCIDevice *s, QEMUFile *f);
845 89b6b508 bellard
int pci_device_load(PCIDevice *s, QEMUFile *f);
846 5768f5ac bellard
847 d537cf6c pbrook
typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level);
848 d2b59317 pbrook
typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
849 d2b59317 pbrook
PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
850 d537cf6c pbrook
                         qemu_irq *pic, int devfn_min, int nirq);
851 502a5395 pbrook
852 abcebc7e ths
void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn);
853 502a5395 pbrook
void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
854 502a5395 pbrook
uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
855 502a5395 pbrook
int pci_bus_num(PCIBus *s);
856 80b3ada7 pbrook
void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d));
857 9995c51f bellard
858 5768f5ac bellard
void pci_info(void);
859 80b3ada7 pbrook
PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
860 80b3ada7 pbrook
                        pci_map_irq_fn map_irq, const char *name);
861 26aa7d72 bellard
862 502a5395 pbrook
/* prep_pci.c */
863 d537cf6c pbrook
PCIBus *pci_prep_init(qemu_irq *pic);
864 77d4bc34 bellard
865 502a5395 pbrook
/* apb_pci.c */
866 5b9693dc blueswir1
PCIBus *pci_apb_init(target_phys_addr_t special_base, target_phys_addr_t mem_base,
867 d537cf6c pbrook
                     qemu_irq *pic);
868 502a5395 pbrook
869 d537cf6c pbrook
PCIBus *pci_vpb_init(qemu_irq *pic, int irq, int realview);
870 502a5395 pbrook
871 502a5395 pbrook
/* piix_pci.c */
872 d537cf6c pbrook
PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic);
873 f00fc47c bellard
void i440fx_set_smm(PCIDevice *d, int val);
874 8f1c91d8 ths
int piix3_init(PCIBus *bus, int devfn);
875 f00fc47c bellard
void i440fx_init_memory_mappings(PCIDevice *d);
876 a41b2ff2 pbrook
877 5856de80 ths
int piix4_init(PCIBus *bus, int devfn);
878 5856de80 ths
879 28b9b5af bellard
/* openpic.c */
880 e9df014c j_mayer
/* OpenPIC have 5 outputs per CPU connected and one IRQ out single output */
881 47103572 j_mayer
enum {
882 e9df014c j_mayer
    OPENPIC_OUTPUT_INT = 0, /* IRQ                       */
883 e9df014c j_mayer
    OPENPIC_OUTPUT_CINT,    /* critical IRQ              */
884 e9df014c j_mayer
    OPENPIC_OUTPUT_MCK,     /* Machine check event       */
885 e9df014c j_mayer
    OPENPIC_OUTPUT_DEBUG,   /* Inconditional debug event */
886 e9df014c j_mayer
    OPENPIC_OUTPUT_RESET,   /* Core reset event          */
887 e9df014c j_mayer
    OPENPIC_OUTPUT_NB,
888 47103572 j_mayer
};
889 e9df014c j_mayer
qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
890 e9df014c j_mayer
                        qemu_irq **irqs, qemu_irq irq_out);
891 28b9b5af bellard
892 fde7d5bd ths
/* gt64xxx.c */
893 d537cf6c pbrook
PCIBus *pci_gt64120_init(qemu_irq *pic);
894 fde7d5bd ths
895 6a36d84e bellard
#ifdef HAS_AUDIO
896 6a36d84e bellard
struct soundhw {
897 6a36d84e bellard
    const char *name;
898 6a36d84e bellard
    const char *descr;
899 6a36d84e bellard
    int enabled;
900 6a36d84e bellard
    int isa;
901 6a36d84e bellard
    union {
902 d537cf6c pbrook
        int (*init_isa) (AudioState *s, qemu_irq *pic);
903 6a36d84e bellard
        int (*init_pci) (PCIBus *bus, AudioState *s);
904 6a36d84e bellard
    } init;
905 6a36d84e bellard
};
906 6a36d84e bellard
907 6a36d84e bellard
extern struct soundhw soundhw[];
908 6a36d84e bellard
#endif
909 6a36d84e bellard
910 313aa567 bellard
/* vga.c */
911 313aa567 bellard
912 eee0b836 blueswir1
#ifndef TARGET_SPARC
913 74a14f22 bellard
#define VGA_RAM_SIZE (8192 * 1024)
914 eee0b836 blueswir1
#else
915 eee0b836 blueswir1
#define VGA_RAM_SIZE (9 * 1024 * 1024)
916 eee0b836 blueswir1
#endif
917 313aa567 bellard
918 82c643ff bellard
struct DisplayState {
919 313aa567 bellard
    uint8_t *data;
920 313aa567 bellard
    int linesize;
921 313aa567 bellard
    int depth;
922 d3079cd2 bellard
    int bgr; /* BGR color order instead of RGB. Only valid for depth == 32 */
923 82c643ff bellard
    int width;
924 82c643ff bellard
    int height;
925 24236869 bellard
    void *opaque;
926 740733bb ths
    QEMUTimer *gui_timer;
927 24236869 bellard
928 313aa567 bellard
    void (*dpy_update)(struct DisplayState *s, int x, int y, int w, int h);
929 313aa567 bellard
    void (*dpy_resize)(struct DisplayState *s, int w, int h);
930 313aa567 bellard
    void (*dpy_refresh)(struct DisplayState *s);
931 d34cab9f ths
    void (*dpy_copy)(struct DisplayState *s, int src_x, int src_y,
932 d34cab9f ths
                     int dst_x, int dst_y, int w, int h);
933 d34cab9f ths
    void (*dpy_fill)(struct DisplayState *s, int x, int y,
934 d34cab9f ths
                     int w, int h, uint32_t c);
935 d34cab9f ths
    void (*mouse_set)(int x, int y, int on);
936 d34cab9f ths
    void (*cursor_define)(int width, int height, int bpp, int hot_x, int hot_y,
937 d34cab9f ths
                          uint8_t *image, uint8_t *mask);
938 82c643ff bellard
};
939 313aa567 bellard
940 313aa567 bellard
static inline void dpy_update(DisplayState *s, int x, int y, int w, int h)
941 313aa567 bellard
{
942 313aa567 bellard
    s->dpy_update(s, x, y, w, h);
943 313aa567 bellard
}
944 313aa567 bellard
945 313aa567 bellard
static inline void dpy_resize(DisplayState *s, int w, int h)
946 313aa567 bellard
{
947 313aa567 bellard
    s->dpy_resize(s, w, h);
948 313aa567 bellard
}
949 313aa567 bellard
950 5fafdf24 ths
int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
951 89b6b508 bellard
                 unsigned long vga_ram_offset, int vga_ram_size);
952 5fafdf24 ths
int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
953 89b6b508 bellard
                 unsigned long vga_ram_offset, int vga_ram_size,
954 89b6b508 bellard
                 unsigned long vga_bios_offset, int vga_bios_size);
955 2abec30b ths
int isa_vga_mm_init(DisplayState *ds, uint8_t *vga_ram_base,
956 2abec30b ths
                    unsigned long vga_ram_offset, int vga_ram_size,
957 2abec30b ths
                    target_phys_addr_t vram_base, target_phys_addr_t ctrl_base,
958 2abec30b ths
                    int it_shift);
959 313aa567 bellard
960 d6bfa22f bellard
/* cirrus_vga.c */
961 5fafdf24 ths
void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
962 d6bfa22f bellard
                         unsigned long vga_ram_offset, int vga_ram_size);
963 5fafdf24 ths
void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
964 d6bfa22f bellard
                         unsigned long vga_ram_offset, int vga_ram_size);
965 d6bfa22f bellard
966 d34cab9f ths
/* vmware_vga.c */
967 d34cab9f ths
void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
968 d34cab9f ths
                     unsigned long vga_ram_offset, int vga_ram_size);
969 d34cab9f ths
970 313aa567 bellard
/* sdl.c */
971 43523e93 ths
void sdl_display_init(DisplayState *ds, int full_screen, int no_frame);
972 313aa567 bellard
973 da4dbf74 bellard
/* cocoa.m */
974 da4dbf74 bellard
void cocoa_display_init(DisplayState *ds, int full_screen);
975 da4dbf74 bellard
976 24236869 bellard
/* vnc.c */
977 71cab5ca ths
void vnc_display_init(DisplayState *ds);
978 71cab5ca ths
void vnc_display_close(DisplayState *ds);
979 71cab5ca ths
int vnc_display_open(DisplayState *ds, const char *display);
980 70848515 ths
int vnc_display_password(DisplayState *ds, const char *password);
981 a9ce8590 bellard
void do_info_vnc(void);
982 24236869 bellard
983 6070dd07 ths
/* x_keymap.c */
984 6070dd07 ths
extern uint8_t _translate_keycode(const int key);
985 6070dd07 ths
986 5391d806 bellard
/* ide.c */
987 5391d806 bellard
#define MAX_DISKS 4
988 5391d806 bellard
989 faea38e7 bellard
extern BlockDriverState *bs_table[MAX_DISKS + 1];
990 a1bb27b1 pbrook
extern BlockDriverState *sd_bdrv;
991 3e3d5815 balrog
extern BlockDriverState *mtd_bdrv;
992 5391d806 bellard
993 d537cf6c pbrook
void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
994 69b91039 bellard
                  BlockDriverState *hd0, BlockDriverState *hd1);
995 54fa5af5 bellard
void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
996 54fa5af5 bellard
                         int secondary_ide_enabled);
997 d537cf6c pbrook
void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
998 d537cf6c pbrook
                        qemu_irq *pic);
999 afcc3cdf ths
void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
1000 afcc3cdf ths
                        qemu_irq *pic);
1001 5391d806 bellard
1002 2e5d83bb pbrook
/* cdrom.c */
1003 2e5d83bb pbrook
int cdrom_read_toc(int nb_sectors, uint8_t *buf, int msf, int start_track);
1004 2e5d83bb pbrook
int cdrom_read_toc_raw(int nb_sectors, uint8_t *buf, int msf, int session_num);
1005 2e5d83bb pbrook
1006 9542611a ths
/* ds1225y.c */
1007 9542611a ths
typedef struct ds1225y_t ds1225y_t;
1008 71db710f blueswir1
ds1225y_t *ds1225y_init(target_phys_addr_t mem_base, const char *filename);
1009 9542611a ths
1010 1d14ffa9 bellard
/* es1370.c */
1011 c0fe3827 bellard
int es1370_init (PCIBus *bus, AudioState *s);
1012 1d14ffa9 bellard
1013 fb065187 bellard
/* sb16.c */
1014 d537cf6c pbrook
int SB16_init (AudioState *s, qemu_irq *pic);
1015 fb065187 bellard
1016 fb065187 bellard
/* adlib.c */
1017 d537cf6c pbrook
int Adlib_init (AudioState *s, qemu_irq *pic);
1018 fb065187 bellard
1019 fb065187 bellard
/* gus.c */
1020 d537cf6c pbrook
int GUS_init (AudioState *s, qemu_irq *pic);
1021 27503323 bellard
1022 27503323 bellard
/* dma.c */
1023 85571bc7 bellard
typedef int (*DMA_transfer_handler) (void *opaque, int nchan, int pos, int size);
1024 27503323 bellard
int DMA_get_channel_mode (int nchan);
1025 85571bc7 bellard
int DMA_read_memory (int nchan, void *buf, int pos, int size);
1026 85571bc7 bellard
int DMA_write_memory (int nchan, void *buf, int pos, int size);
1027 27503323 bellard
void DMA_hold_DREQ (int nchan);
1028 27503323 bellard
void DMA_release_DREQ (int nchan);
1029 16f62432 bellard
void DMA_schedule(int nchan);
1030 27503323 bellard
void DMA_run (void);
1031 28b9b5af bellard
void DMA_init (int high_page_enable);
1032 27503323 bellard
void DMA_register_channel (int nchan,
1033 85571bc7 bellard
                           DMA_transfer_handler transfer_handler,
1034 85571bc7 bellard
                           void *opaque);
1035 7138fcfb bellard
/* fdc.c */
1036 7138fcfb bellard
#define MAX_FD 2
1037 7138fcfb bellard
extern BlockDriverState *fd_table[MAX_FD];
1038 7138fcfb bellard
1039 baca51fa bellard
typedef struct fdctrl_t fdctrl_t;
1040 baca51fa bellard
1041 5fafdf24 ths
fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
1042 5dcb6b91 blueswir1
                       target_phys_addr_t io_base,
1043 baca51fa bellard
                       BlockDriverState **fds);
1044 741402f9 blueswir1
fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, target_phys_addr_t io_base,
1045 741402f9 blueswir1
                             BlockDriverState **fds);
1046 baca51fa bellard
int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num);
1047 7138fcfb bellard
1048 663e8e51 ths
/* eepro100.c */
1049 663e8e51 ths
1050 663e8e51 ths
void pci_i82551_init(PCIBus *bus, NICInfo *nd, int devfn);
1051 663e8e51 ths
void pci_i82557b_init(PCIBus *bus, NICInfo *nd, int devfn);
1052 663e8e51 ths
void pci_i82559er_init(PCIBus *bus, NICInfo *nd, int devfn);
1053 663e8e51 ths
1054 80cabfad bellard
/* ne2000.c */
1055 80cabfad bellard
1056 d537cf6c pbrook
void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd);
1057 abcebc7e ths
void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn);
1058 80cabfad bellard
1059 a41b2ff2 pbrook
/* rtl8139.c */
1060 a41b2ff2 pbrook
1061 abcebc7e ths
void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn);
1062 a41b2ff2 pbrook
1063 e3c2613f bellard
/* pcnet.c */
1064 e3c2613f bellard
1065 abcebc7e ths
void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn);
1066 70c0de96 blueswir1
void lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque,
1067 2d069bab blueswir1
                qemu_irq irq, qemu_irq *reset);
1068 67e999be bellard
1069 6bf5b4e8 ths
/* mipsnet.c */
1070 6bf5b4e8 ths
void mipsnet_init(int base, qemu_irq irq, NICInfo *nd);
1071 6bf5b4e8 ths
1072 548df2ac ths
/* vmmouse.c */
1073 548df2ac ths
void *vmmouse_init(void *m);
1074 e3c2613f bellard
1075 591a6d62 ths
/* vmport.c */
1076 591a6d62 ths
#ifdef TARGET_I386
1077 591a6d62 ths
void vmport_init(CPUState *env);
1078 591a6d62 ths
void vmport_register(unsigned char command, IOPortReadFunc *func, void *opaque);
1079 591a6d62 ths
#endif
1080 591a6d62 ths
1081 80cabfad bellard
/* pckbd.c */
1082 80cabfad bellard
1083 b92bb99b ths
void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
1084 71db710f blueswir1
void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
1085 71db710f blueswir1
                   target_phys_addr_t base, int it_shift);
1086 80cabfad bellard
1087 80cabfad bellard
/* mc146818rtc.c */
1088 80cabfad bellard
1089 8a7ddc38 bellard
typedef struct RTCState RTCState;
1090 80cabfad bellard
1091 d537cf6c pbrook
RTCState *rtc_init(int base, qemu_irq irq);
1092 18c6e2ff ths
RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq);
1093 8a7ddc38 bellard
void rtc_set_memory(RTCState *s, int addr, int val);
1094 8a7ddc38 bellard
void rtc_set_date(RTCState *s, const struct tm *tm);
1095 80cabfad bellard
1096 80cabfad bellard
/* serial.c */
1097 80cabfad bellard
1098 c4b1fcc0 bellard
typedef struct SerialState SerialState;
1099 d537cf6c pbrook
SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr);
1100 71db710f blueswir1
SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
1101 d537cf6c pbrook
                             qemu_irq irq, CharDriverState *chr,
1102 a4bc3afc ths
                             int ioregister);
1103 a4bc3afc ths
uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr);
1104 a4bc3afc ths
void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value);
1105 a4bc3afc ths
uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr);
1106 a4bc3afc ths
void serial_mm_writew (void *opaque, target_phys_addr_t addr, uint32_t value);
1107 a4bc3afc ths
uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr);
1108 a4bc3afc ths
void serial_mm_writel (void *opaque, target_phys_addr_t addr, uint32_t value);
1109 80cabfad bellard
1110 6508fe59 bellard
/* parallel.c */
1111 6508fe59 bellard
1112 6508fe59 bellard
typedef struct ParallelState ParallelState;
1113 d537cf6c pbrook
ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr);
1114 d60532ca ths
ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr);
1115 6508fe59 bellard
1116 80cabfad bellard
/* i8259.c */
1117 80cabfad bellard
1118 3de388f6 bellard
typedef struct PicState2 PicState2;
1119 3de388f6 bellard
extern PicState2 *isa_pic;
1120 80cabfad bellard
void pic_set_irq(int irq, int level);
1121 54fa5af5 bellard
void pic_set_irq_new(void *opaque, int irq, int level);
1122 d537cf6c pbrook
qemu_irq *i8259_init(qemu_irq parent_irq);
1123 d592d303 bellard
void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
1124 d592d303 bellard
                          void *alt_irq_opaque);
1125 3de388f6 bellard
int pic_read_irq(PicState2 *s);
1126 3de388f6 bellard
void pic_update_irq(PicState2 *s);
1127 3de388f6 bellard
uint32_t pic_intack_read(PicState2 *s);
1128 c20709aa bellard
void pic_info(void);
1129 4a0fb71e bellard
void irq_info(void);
1130 80cabfad bellard
1131 c27004ec bellard
/* APIC */
1132 d592d303 bellard
typedef struct IOAPICState IOAPICState;
1133 d592d303 bellard
1134 c27004ec bellard
int apic_init(CPUState *env);
1135 0e21e12b ths
int apic_accept_pic_intr(CPUState *env);
1136 c27004ec bellard
int apic_get_interrupt(CPUState *env);
1137 d592d303 bellard
IOAPICState *ioapic_init(void);
1138 d592d303 bellard
void ioapic_set_irq(void *opaque, int vector, int level);
1139 c27004ec bellard
1140 80cabfad bellard
/* i8254.c */
1141 80cabfad bellard
1142 80cabfad bellard
#define PIT_FREQ 1193182
1143 80cabfad bellard
1144 ec844b96 bellard
typedef struct PITState PITState;
1145 ec844b96 bellard
1146 d537cf6c pbrook
PITState *pit_init(int base, qemu_irq irq);
1147 ec844b96 bellard
void pit_set_gate(PITState *pit, int channel, int val);
1148 ec844b96 bellard
int pit_get_gate(PITState *pit, int channel);
1149 fd06c375 bellard
int pit_get_initial_count(PITState *pit, int channel);
1150 fd06c375 bellard
int pit_get_mode(PITState *pit, int channel);
1151 ec844b96 bellard
int pit_get_out(PITState *pit, int channel, int64_t current_time);
1152 80cabfad bellard
1153 31211df1 ths
/* jazz_led.c */
1154 31211df1 ths
extern void jazz_led_init(DisplayState *ds, target_phys_addr_t base);
1155 31211df1 ths
1156 fd06c375 bellard
/* pcspk.c */
1157 fd06c375 bellard
void pcspk_init(PITState *);
1158 d537cf6c pbrook
int pcspk_audio_init(AudioState *, qemu_irq *pic);
1159 fd06c375 bellard
1160 0ff596d0 pbrook
#include "hw/i2c.h"
1161 0ff596d0 pbrook
1162 3fffc223 ths
#include "hw/smbus.h"
1163 3fffc223 ths
1164 6515b203 bellard
/* acpi.c */
1165 6515b203 bellard
extern int acpi_enabled;
1166 7b717336 ths
i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
1167 3fffc223 ths
void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
1168 6515b203 bellard
void acpi_bios_init(void);
1169 6515b203 bellard
1170 f1ccf904 ths
/* Axis ETRAX.  */
1171 f1ccf904 ths
extern QEMUMachine bareetraxfs_machine;
1172 f1ccf904 ths
1173 80cabfad bellard
/* pc.c */
1174 54fa5af5 bellard
extern QEMUMachine pc_machine;
1175 3dbbdc25 bellard
extern QEMUMachine isapc_machine;
1176 52ca8d6a bellard
extern int fd_bootchk;
1177 80cabfad bellard
1178 6a00d601 bellard
void ioport_set_a20(int enable);
1179 6a00d601 bellard
int ioport_get_a20(void);
1180 6a00d601 bellard
1181 26aa7d72 bellard
/* ppc.c */
1182 54fa5af5 bellard
extern QEMUMachine prep_machine;
1183 54fa5af5 bellard
extern QEMUMachine core99_machine;
1184 54fa5af5 bellard
extern QEMUMachine heathrow_machine;
1185 1a6c0886 j_mayer
extern QEMUMachine ref405ep_machine;
1186 1a6c0886 j_mayer
extern QEMUMachine taihu_machine;
1187 54fa5af5 bellard
1188 6af0bf9c bellard
/* mips_r4k.c */
1189 6af0bf9c bellard
extern QEMUMachine mips_machine;
1190 6af0bf9c bellard
1191 5856de80 ths
/* mips_malta.c */
1192 5856de80 ths
extern QEMUMachine mips_malta_machine;
1193 5856de80 ths
1194 ad6fe1d2 ths
/* mips_pica61.c */
1195 ad6fe1d2 ths
extern QEMUMachine mips_pica61_machine;
1196 ad6fe1d2 ths
1197 6bf5b4e8 ths
/* mips_mipssim.c */
1198 6bf5b4e8 ths
extern QEMUMachine mips_mipssim_machine;
1199 6bf5b4e8 ths
1200 6bf5b4e8 ths
/* mips_int.c */
1201 6bf5b4e8 ths
extern void cpu_mips_irq_init_cpu(CPUState *env);
1202 6bf5b4e8 ths
1203 e16fe40c ths
/* mips_timer.c */
1204 e16fe40c ths
extern void cpu_mips_clock_init(CPUState *);
1205 e16fe40c ths
extern void cpu_mips_irqctrl_init (void);
1206 e16fe40c ths
1207 27c7ca7e bellard
/* shix.c */
1208 27c7ca7e bellard
extern QEMUMachine shix_machine;
1209 27c7ca7e bellard
1210 0d78f544 ths
/* r2d.c */
1211 0d78f544 ths
extern QEMUMachine r2d_machine;
1212 0d78f544 ths
1213 8cc43fef bellard
#ifdef TARGET_PPC
1214 47103572 j_mayer
/* PowerPC hardware exceptions management helpers */
1215 8ecc7913 j_mayer
typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);
1216 8ecc7913 j_mayer
typedef struct clk_setup_t clk_setup_t;
1217 8ecc7913 j_mayer
struct clk_setup_t {
1218 8ecc7913 j_mayer
    clk_setup_cb cb;
1219 8ecc7913 j_mayer
    void *opaque;
1220 8ecc7913 j_mayer
};
1221 8ecc7913 j_mayer
static inline void clk_setup (clk_setup_t *clk, uint32_t freq)
1222 8ecc7913 j_mayer
{
1223 8ecc7913 j_mayer
    if (clk->cb != NULL)
1224 8ecc7913 j_mayer
        (*clk->cb)(clk->opaque, freq);
1225 8ecc7913 j_mayer
}
1226 8ecc7913 j_mayer
1227 8ecc7913 j_mayer
clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq);
1228 2e719ba3 j_mayer
/* Embedded PowerPC DCR management */
1229 2e719ba3 j_mayer
typedef target_ulong (*dcr_read_cb)(void *opaque, int dcrn);
1230 2e719ba3 j_mayer
typedef void (*dcr_write_cb)(void *opaque, int dcrn, target_ulong val);
1231 2e719ba3 j_mayer
int ppc_dcr_init (CPUState *env, int (*dcr_read_error)(int dcrn),
1232 2e719ba3 j_mayer
                  int (*dcr_write_error)(int dcrn));
1233 2e719ba3 j_mayer
int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
1234 2e719ba3 j_mayer
                      dcr_read_cb drc_read, dcr_write_cb dcr_write);
1235 8ecc7913 j_mayer
clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq);
1236 4a057712 j_mayer
/* Embedded PowerPC reset */
1237 4a057712 j_mayer
void ppc40x_core_reset (CPUState *env);
1238 4a057712 j_mayer
void ppc40x_chip_reset (CPUState *env);
1239 4a057712 j_mayer
void ppc40x_system_reset (CPUState *env);
1240 64201201 bellard
void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
1241 77d4bc34 bellard
1242 77d4bc34 bellard
extern CPUWriteMemoryFunc *PPC_io_write[];
1243 77d4bc34 bellard
extern CPUReadMemoryFunc *PPC_io_read[];
1244 54fa5af5 bellard
void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
1245 3cbee15b j_mayer
#endif
1246 26aa7d72 bellard
1247 e95c8d51 bellard
/* sun4m.c */
1248 e0353fe2 blueswir1
extern QEMUMachine ss5_machine, ss10_machine;
1249 e95c8d51 bellard
1250 e95c8d51 bellard
/* iommu.c */
1251 5dcb6b91 blueswir1
void *iommu_init(target_phys_addr_t addr);
1252 67e999be bellard
void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
1253 a917d384 pbrook
                                 uint8_t *buf, int len, int is_write);
1254 67e999be bellard
static inline void sparc_iommu_memory_read(void *opaque,
1255 67e999be bellard
                                           target_phys_addr_t addr,
1256 67e999be bellard
                                           uint8_t *buf, int len)
1257 67e999be bellard
{
1258 67e999be bellard
    sparc_iommu_memory_rw(opaque, addr, buf, len, 0);
1259 67e999be bellard
}
1260 e95c8d51 bellard
1261 67e999be bellard
static inline void sparc_iommu_memory_write(void *opaque,
1262 67e999be bellard
                                            target_phys_addr_t addr,
1263 67e999be bellard
                                            uint8_t *buf, int len)
1264 67e999be bellard
{
1265 67e999be bellard
    sparc_iommu_memory_rw(opaque, addr, buf, len, 1);
1266 67e999be bellard
}
1267 e95c8d51 bellard
1268 e95c8d51 bellard
/* tcx.c */
1269 5dcb6b91 blueswir1
void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base,
1270 5dcb6b91 blueswir1
              unsigned long vram_offset, int vram_size, int width, int height,
1271 eee0b836 blueswir1
              int depth);
1272 e80cfcfc bellard
1273 e80cfcfc bellard
/* slavio_intctl.c */
1274 5dcb6b91 blueswir1
void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
1275 d537cf6c pbrook
                         const uint32_t *intbit_to_level,
1276 d7edfd27 blueswir1
                         qemu_irq **irq, qemu_irq **cpu_irq,
1277 b3a23197 blueswir1
                         qemu_irq **parent_irq, unsigned int cputimer);
1278 e80cfcfc bellard
void slavio_pic_info(void *opaque);
1279 e80cfcfc bellard
void slavio_irq_info(void *opaque);
1280 e95c8d51 bellard
1281 5fe141fd bellard
/* loader.c */
1282 5fe141fd bellard
int get_image_size(const char *filename);
1283 5fe141fd bellard
int load_image(const char *filename, uint8_t *addr);
1284 74287114 ths
int load_elf(const char *filename, int64_t virt_to_phys_addend,
1285 74287114 ths
             uint64_t *pentry, uint64_t *lowaddr, uint64_t *highaddr);
1286 e80cfcfc bellard
int load_aout(const char *filename, uint8_t *addr);
1287 1c7b3754 pbrook
int load_uboot(const char *filename, target_ulong *ep, int *is_linux);
1288 e80cfcfc bellard
1289 e80cfcfc bellard
/* slavio_timer.c */
1290 81732d19 blueswir1
void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq,
1291 81732d19 blueswir1
                           qemu_irq *cpu_irqs);
1292 8d5f07fa bellard
1293 e80cfcfc bellard
/* slavio_serial.c */
1294 5dcb6b91 blueswir1
SerialState *slavio_serial_init(target_phys_addr_t base, qemu_irq irq,
1295 5dcb6b91 blueswir1
                                CharDriverState *chr1, CharDriverState *chr2);
1296 5dcb6b91 blueswir1
void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq);
1297 e95c8d51 bellard
1298 3475187d bellard
/* slavio_misc.c */
1299 5dcb6b91 blueswir1
void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
1300 5dcb6b91 blueswir1
                       qemu_irq irq);
1301 3475187d bellard
void slavio_set_power_fail(void *opaque, int power_failing);
1302 3475187d bellard
1303 6f7e9aec bellard
/* esp.c */
1304 fa1fb14c ths
void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1305 5dcb6b91 blueswir1
void *esp_init(BlockDriverState **bd, target_phys_addr_t espaddr,
1306 2d069bab blueswir1
               void *dma_opaque, qemu_irq irq, qemu_irq *reset);
1307 67e999be bellard
1308 67e999be bellard
/* sparc32_dma.c */
1309 70c0de96 blueswir1
void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
1310 2d069bab blueswir1
                       void *iommu, qemu_irq **dev_irq, qemu_irq **reset);
1311 5fafdf24 ths
void ledma_memory_read(void *opaque, target_phys_addr_t addr,
1312 9b94dc32 bellard
                       uint8_t *buf, int len, int do_bswap);
1313 5fafdf24 ths
void ledma_memory_write(void *opaque, target_phys_addr_t addr,
1314 9b94dc32 bellard
                        uint8_t *buf, int len, int do_bswap);
1315 67e999be bellard
void espdma_memory_read(void *opaque, uint8_t *buf, int len);
1316 67e999be bellard
void espdma_memory_write(void *opaque, uint8_t *buf, int len);
1317 6f7e9aec bellard
1318 b8174937 bellard
/* cs4231.c */
1319 b8174937 bellard
void cs_init(target_phys_addr_t base, int irq, void *intctl);
1320 b8174937 bellard
1321 3475187d bellard
/* sun4u.c */
1322 3475187d bellard
extern QEMUMachine sun4u_machine;
1323 3475187d bellard
1324 64201201 bellard
/* NVRAM helpers */
1325 3cbee15b j_mayer
typedef uint32_t (*nvram_read_t)(void *private, uint32_t addr);
1326 3cbee15b j_mayer
typedef void (*nvram_write_t)(void *private, uint32_t addr, uint32_t val);
1327 3cbee15b j_mayer
typedef struct nvram_t {
1328 3cbee15b j_mayer
    void *opaque;
1329 3cbee15b j_mayer
    nvram_read_t read_fn;
1330 3cbee15b j_mayer
    nvram_write_t write_fn;
1331 3cbee15b j_mayer
} nvram_t;
1332 3cbee15b j_mayer
1333 64201201 bellard
#include "hw/m48t59.h"
1334 64201201 bellard
1335 3cbee15b j_mayer
void NVRAM_set_byte (nvram_t *nvram, uint32_t addr, uint8_t value);
1336 3cbee15b j_mayer
uint8_t NVRAM_get_byte (nvram_t *nvram, uint32_t addr);
1337 3cbee15b j_mayer
void NVRAM_set_word (nvram_t *nvram, uint32_t addr, uint16_t value);
1338 3cbee15b j_mayer
uint16_t NVRAM_get_word (nvram_t *nvram, uint32_t addr);
1339 3cbee15b j_mayer
void NVRAM_set_lword (nvram_t *nvram, uint32_t addr, uint32_t value);
1340 3cbee15b j_mayer
uint32_t NVRAM_get_lword (nvram_t *nvram, uint32_t addr);
1341 3cbee15b j_mayer
void NVRAM_set_string (nvram_t *nvram, uint32_t addr,
1342 64201201 bellard
                       const unsigned char *str, uint32_t max);
1343 3cbee15b j_mayer
int NVRAM_get_string (nvram_t *nvram, uint8_t *dst, uint16_t addr, int max);
1344 3cbee15b j_mayer
void NVRAM_set_crc (nvram_t *nvram, uint32_t addr,
1345 64201201 bellard
                    uint32_t start, uint32_t count);
1346 3cbee15b j_mayer
int PPC_NVRAM_set_params (nvram_t *nvram, uint16_t NVRAM_size,
1347 64201201 bellard
                          const unsigned char *arch,
1348 64201201 bellard
                          uint32_t RAM_size, int boot_device,
1349 64201201 bellard
                          uint32_t kernel_image, uint32_t kernel_size,
1350 28b9b5af bellard
                          const char *cmdline,
1351 64201201 bellard
                          uint32_t initrd_image, uint32_t initrd_size,
1352 28b9b5af bellard
                          uint32_t NVRAM_image,
1353 28b9b5af bellard
                          int width, int height, int depth);
1354 64201201 bellard
1355 63066f4f bellard
/* adb.c */
1356 63066f4f bellard
1357 63066f4f bellard
#define MAX_ADB_DEVICES 16
1358 63066f4f bellard
1359 e2733d20 bellard
#define ADB_MAX_OUT_LEN 16
1360 63066f4f bellard
1361 e2733d20 bellard
typedef struct ADBDevice ADBDevice;
1362 63066f4f bellard
1363 e2733d20 bellard
/* buf = NULL means polling */
1364 e2733d20 bellard
typedef int ADBDeviceRequest(ADBDevice *d, uint8_t *buf_out,
1365 e2733d20 bellard
                              const uint8_t *buf, int len);
1366 12c28fed bellard
typedef int ADBDeviceReset(ADBDevice *d);
1367 12c28fed bellard
1368 63066f4f bellard
struct ADBDevice {
1369 63066f4f bellard
    struct ADBBusState *bus;
1370 63066f4f bellard
    int devaddr;
1371 63066f4f bellard
    int handler;
1372 e2733d20 bellard
    ADBDeviceRequest *devreq;
1373 12c28fed bellard
    ADBDeviceReset *devreset;
1374 63066f4f bellard
    void *opaque;
1375 63066f4f bellard
};
1376 63066f4f bellard
1377 63066f4f bellard
typedef struct ADBBusState {
1378 63066f4f bellard
    ADBDevice devices[MAX_ADB_DEVICES];
1379 63066f4f bellard
    int nb_devices;
1380 e2733d20 bellard
    int poll_index;
1381 63066f4f bellard
} ADBBusState;
1382 63066f4f bellard
1383 e2733d20 bellard
int adb_request(ADBBusState *s, uint8_t *buf_out,
1384 e2733d20 bellard
                const uint8_t *buf, int len);
1385 e2733d20 bellard
int adb_poll(ADBBusState *s, uint8_t *buf_out);
1386 63066f4f bellard
1387 5fafdf24 ths
ADBDevice *adb_register_device(ADBBusState *s, int devaddr,
1388 5fafdf24 ths
                               ADBDeviceRequest *devreq,
1389 5fafdf24 ths
                               ADBDeviceReset *devreset,
1390 63066f4f bellard
                               void *opaque);
1391 63066f4f bellard
void adb_kbd_init(ADBBusState *bus);
1392 63066f4f bellard
void adb_mouse_init(ADBBusState *bus);
1393 63066f4f bellard
1394 63066f4f bellard
extern ADBBusState adb_bus;
1395 63066f4f bellard
1396 bb36d470 bellard
#include "hw/usb.h"
1397 bb36d470 bellard
1398 a594cfbf bellard
/* usb ports of the VM */
1399 a594cfbf bellard
1400 0d92ed30 pbrook
void qemu_register_usb_port(USBPort *port, void *opaque, int index,
1401 0d92ed30 pbrook
                            usb_attachfn attach);
1402 a594cfbf bellard
1403 0d92ed30 pbrook
#define VM_USB_HUB_SIZE 8
1404 a594cfbf bellard
1405 a594cfbf bellard
void do_usb_add(const char *devname);
1406 a594cfbf bellard
void do_usb_del(const char *devname);
1407 a594cfbf bellard
void usb_info(void);
1408 a594cfbf bellard
1409 2e5d83bb pbrook
/* scsi-disk.c */
1410 4d611c9a pbrook
enum scsi_reason {
1411 4d611c9a pbrook
    SCSI_REASON_DONE, /* Command complete.  */
1412 4d611c9a pbrook
    SCSI_REASON_DATA  /* Transfer complete, more data required.  */
1413 4d611c9a pbrook
};
1414 4d611c9a pbrook
1415 2e5d83bb pbrook
typedef struct SCSIDevice SCSIDevice;
1416 a917d384 pbrook
typedef void (*scsi_completionfn)(void *opaque, int reason, uint32_t tag,
1417 a917d384 pbrook
                                  uint32_t arg);
1418 2e5d83bb pbrook
1419 2e5d83bb pbrook
SCSIDevice *scsi_disk_init(BlockDriverState *bdrv,
1420 a917d384 pbrook
                           int tcq,
1421 2e5d83bb pbrook
                           scsi_completionfn completion,
1422 2e5d83bb pbrook
                           void *opaque);
1423 2e5d83bb pbrook
void scsi_disk_destroy(SCSIDevice *s);
1424 2e5d83bb pbrook
1425 0fc5c15a pbrook
int32_t scsi_send_command(SCSIDevice *s, uint32_t tag, uint8_t *buf, int lun);
1426 4d611c9a pbrook
/* SCSI data transfers are asynchrnonous.  However, unlike the block IO
1427 4d611c9a pbrook
   layer the completion routine may be called directly by
1428 4d611c9a pbrook
   scsi_{read,write}_data.  */
1429 a917d384 pbrook
void scsi_read_data(SCSIDevice *s, uint32_t tag);
1430 a917d384 pbrook
int scsi_write_data(SCSIDevice *s, uint32_t tag);
1431 a917d384 pbrook
void scsi_cancel_io(SCSIDevice *s, uint32_t tag);
1432 a917d384 pbrook
uint8_t *scsi_get_buf(SCSIDevice *s, uint32_t tag);
1433 2e5d83bb pbrook
1434 7d8406be pbrook
/* lsi53c895a.c */
1435 7d8406be pbrook
void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1436 7d8406be pbrook
void *lsi_scsi_init(PCIBus *bus, int devfn);
1437 7d8406be pbrook
1438 b5ff1b31 bellard
/* integratorcp.c */
1439 3371d272 pbrook
extern QEMUMachine integratorcp_machine;
1440 b5ff1b31 bellard
1441 cdbdb648 pbrook
/* versatilepb.c */
1442 cdbdb648 pbrook
extern QEMUMachine versatilepb_machine;
1443 16406950 pbrook
extern QEMUMachine versatileab_machine;
1444 cdbdb648 pbrook
1445 e69954b9 pbrook
/* realview.c */
1446 e69954b9 pbrook
extern QEMUMachine realview_machine;
1447 e69954b9 pbrook
1448 b00052e4 balrog
/* spitz.c */
1449 b00052e4 balrog
extern QEMUMachine akitapda_machine;
1450 b00052e4 balrog
extern QEMUMachine spitzpda_machine;
1451 b00052e4 balrog
extern QEMUMachine borzoipda_machine;
1452 b00052e4 balrog
extern QEMUMachine terrierpda_machine;
1453 b00052e4 balrog
1454 c3d2689d balrog
/* palm.c */
1455 c3d2689d balrog
extern QEMUMachine palmte_machine;
1456 c3d2689d balrog
1457 daa57963 bellard
/* ps2.c */
1458 daa57963 bellard
void *ps2_kbd_init(void (*update_irq)(void *, int), void *update_arg);
1459 daa57963 bellard
void *ps2_mouse_init(void (*update_irq)(void *, int), void *update_arg);
1460 daa57963 bellard
void ps2_write_mouse(void *, int val);
1461 daa57963 bellard
void ps2_write_keyboard(void *, int val);
1462 daa57963 bellard
uint32_t ps2_read_data(void *);
1463 daa57963 bellard
void ps2_queue(void *, int b);
1464 f94f5d71 pbrook
void ps2_keyboard_set_translation(void *opaque, int mode);
1465 548df2ac ths
void ps2_mouse_fake_event(void *opaque);
1466 daa57963 bellard
1467 80337b66 bellard
/* smc91c111.c */
1468 d537cf6c pbrook
void smc91c111_init(NICInfo *, uint32_t, qemu_irq);
1469 80337b66 bellard
1470 7e1543c2 pbrook
/* pl031.c */
1471 7e1543c2 pbrook
void pl031_init(uint32_t base, qemu_irq irq);
1472 7e1543c2 pbrook
1473 bdd5003a pbrook
/* pl110.c */
1474 d537cf6c pbrook
void *pl110_init(DisplayState *ds, uint32_t base, qemu_irq irq, int);
1475 bdd5003a pbrook
1476 cdbdb648 pbrook
/* pl011.c */
1477 d537cf6c pbrook
void pl011_init(uint32_t base, qemu_irq irq, CharDriverState *chr);
1478 cdbdb648 pbrook
1479 cdbdb648 pbrook
/* pl050.c */
1480 d537cf6c pbrook
void pl050_init(uint32_t base, qemu_irq irq, int is_mouse);
1481 cdbdb648 pbrook
1482 cdbdb648 pbrook
/* pl080.c */
1483 d537cf6c pbrook
void *pl080_init(uint32_t base, qemu_irq irq, int nchannels);
1484 cdbdb648 pbrook
1485 a1bb27b1 pbrook
/* pl181.c */
1486 a1bb27b1 pbrook
void pl181_init(uint32_t base, BlockDriverState *bd,
1487 d537cf6c pbrook
                qemu_irq irq0, qemu_irq irq1);
1488 a1bb27b1 pbrook
1489 cdbdb648 pbrook
/* pl190.c */
1490 d537cf6c pbrook
qemu_irq *pl190_init(uint32_t base, qemu_irq irq, qemu_irq fiq);
1491 cdbdb648 pbrook
1492 cdbdb648 pbrook
/* arm-timer.c */
1493 d537cf6c pbrook
void sp804_init(uint32_t base, qemu_irq irq);
1494 d537cf6c pbrook
void icp_pit_init(uint32_t base, qemu_irq *pic, int irq);
1495 cdbdb648 pbrook
1496 e69954b9 pbrook
/* arm_sysctl.c */
1497 e69954b9 pbrook
void arm_sysctl_init(uint32_t base, uint32_t sys_id);
1498 e69954b9 pbrook
1499 e69954b9 pbrook
/* arm_gic.c */
1500 d537cf6c pbrook
qemu_irq *arm_gic_init(uint32_t base, qemu_irq parent_irq);
1501 e69954b9 pbrook
1502 16406950 pbrook
/* arm_boot.c */
1503 16406950 pbrook
1504 daf90626 pbrook
void arm_load_kernel(CPUState *env, int ram_size, const char *kernel_filename,
1505 16406950 pbrook
                     const char *kernel_cmdline, const char *initrd_filename,
1506 9d551997 balrog
                     int board_id, target_phys_addr_t loader_start);
1507 16406950 pbrook
1508 27c7ca7e bellard
/* sh7750.c */
1509 27c7ca7e bellard
struct SH7750State;
1510 27c7ca7e bellard
1511 008a8818 pbrook
struct SH7750State *sh7750_init(CPUState * cpu);
1512 27c7ca7e bellard
1513 27c7ca7e bellard
typedef struct {
1514 27c7ca7e bellard
    /* The callback will be triggered if any of the designated lines change */
1515 27c7ca7e bellard
    uint16_t portamask_trigger;
1516 27c7ca7e bellard
    uint16_t portbmask_trigger;
1517 27c7ca7e bellard
    /* Return 0 if no action was taken */
1518 27c7ca7e bellard
    int (*port_change_cb) (uint16_t porta, uint16_t portb,
1519 27c7ca7e bellard
                           uint16_t * periph_pdtra,
1520 27c7ca7e bellard
                           uint16_t * periph_portdira,
1521 27c7ca7e bellard
                           uint16_t * periph_pdtrb,
1522 27c7ca7e bellard
                           uint16_t * periph_portdirb);
1523 27c7ca7e bellard
} sh7750_io_device;
1524 27c7ca7e bellard
1525 27c7ca7e bellard
int sh7750_register_io_device(struct SH7750State *s,
1526 27c7ca7e bellard
                              sh7750_io_device * device);
1527 cd1a3f68 ths
/* sh_timer.c */
1528 cd1a3f68 ths
#define TMU012_FEAT_TOCR   (1 << 0)
1529 cd1a3f68 ths
#define TMU012_FEAT_3CHAN  (1 << 1)
1530 cd1a3f68 ths
#define TMU012_FEAT_EXTCLK (1 << 2)
1531 cd1a3f68 ths
void tmu012_init(uint32_t base, int feat, uint32_t freq);
1532 cd1a3f68 ths
1533 2f062c72 ths
/* sh_serial.c */
1534 2f062c72 ths
#define SH_SERIAL_FEAT_SCIF (1 << 0)
1535 2f062c72 ths
void sh_serial_init (target_phys_addr_t base, int feat,
1536 2f062c72 ths
                     uint32_t freq, CharDriverState *chr);
1537 2f062c72 ths
1538 27c7ca7e bellard
/* tc58128.c */
1539 27c7ca7e bellard
int tc58128_init(struct SH7750State *s, char *zone1, char *zone2);
1540 27c7ca7e bellard
1541 29133e9a bellard
/* NOR flash devices */
1542 86f55663 j_mayer
#define MAX_PFLASH 4
1543 86f55663 j_mayer
extern BlockDriverState *pflash_table[MAX_PFLASH];
1544 29133e9a bellard
typedef struct pflash_t pflash_t;
1545 29133e9a bellard
1546 71db710f blueswir1
pflash_t *pflash_register (target_phys_addr_t base, ram_addr_t off,
1547 29133e9a bellard
                           BlockDriverState *bs,
1548 71db710f blueswir1
                           uint32_t sector_len, int nb_blocs, int width,
1549 5fafdf24 ths
                           uint16_t id0, uint16_t id1,
1550 29133e9a bellard
                           uint16_t id2, uint16_t id3);
1551 29133e9a bellard
1552 3e3d5815 balrog
/* nand.c */
1553 3e3d5815 balrog
struct nand_flash_s;
1554 3e3d5815 balrog
struct nand_flash_s *nand_init(int manf_id, int chip_id);
1555 3e3d5815 balrog
void nand_done(struct nand_flash_s *s);
1556 5fafdf24 ths
void nand_setpins(struct nand_flash_s *s,
1557 3e3d5815 balrog
                int cle, int ale, int ce, int wp, int gnd);
1558 3e3d5815 balrog
void nand_getpins(struct nand_flash_s *s, int *rb);
1559 3e3d5815 balrog
void nand_setio(struct nand_flash_s *s, uint8_t value);
1560 3e3d5815 balrog
uint8_t nand_getio(struct nand_flash_s *s);
1561 3e3d5815 balrog
1562 3e3d5815 balrog
#define NAND_MFR_TOSHIBA        0x98
1563 3e3d5815 balrog
#define NAND_MFR_SAMSUNG        0xec
1564 3e3d5815 balrog
#define NAND_MFR_FUJITSU        0x04
1565 3e3d5815 balrog
#define NAND_MFR_NATIONAL        0x8f
1566 3e3d5815 balrog
#define NAND_MFR_RENESAS        0x07
1567 3e3d5815 balrog
#define NAND_MFR_STMICRO        0x20
1568 3e3d5815 balrog
#define NAND_MFR_HYNIX                0xad
1569 3e3d5815 balrog
#define NAND_MFR_MICRON                0x2c
1570 3e3d5815 balrog
1571 9ff6755b balrog
/* ecc.c */
1572 9ff6755b balrog
struct ecc_state_s {
1573 9ff6755b balrog
    uint8_t cp;                /* Column parity */
1574 9ff6755b balrog
    uint16_t lp[2];        /* Line parity */
1575 9ff6755b balrog
    uint16_t count;
1576 9ff6755b balrog
};
1577 9ff6755b balrog
1578 9ff6755b balrog
uint8_t ecc_digest(struct ecc_state_s *s, uint8_t sample);
1579 9ff6755b balrog
void ecc_reset(struct ecc_state_s *s);
1580 9ff6755b balrog
void ecc_put(QEMUFile *f, struct ecc_state_s *s);
1581 9ff6755b balrog
void ecc_get(QEMUFile *f, struct ecc_state_s *s);
1582 3e3d5815 balrog
1583 2a1d1880 balrog
/* GPIO */
1584 2a1d1880 balrog
typedef void (*gpio_handler_t)(int line, int level, void *opaque);
1585 2a1d1880 balrog
1586 fd5a3b33 balrog
/* ads7846.c */
1587 fd5a3b33 balrog
struct ads7846_state_s;
1588 fd5a3b33 balrog
uint32_t ads7846_read(void *opaque);
1589 fd5a3b33 balrog
void ads7846_write(void *opaque, uint32_t value);
1590 fd5a3b33 balrog
struct ads7846_state_s *ads7846_init(qemu_irq penirq);
1591 fd5a3b33 balrog
1592 c824cacd balrog
/* max111x.c */
1593 c824cacd balrog
struct max111x_s;
1594 c824cacd balrog
uint32_t max111x_read(void *opaque);
1595 c824cacd balrog
void max111x_write(void *opaque, uint32_t value);
1596 c824cacd balrog
struct max111x_s *max1110_init(qemu_irq cb);
1597 c824cacd balrog
struct max111x_s *max1111_init(qemu_irq cb);
1598 c824cacd balrog
void max111x_set_input(struct max111x_s *s, int line, uint8_t value);
1599 c824cacd balrog
1600 201a51fc balrog
/* PCMCIA/Cardbus */
1601 201a51fc balrog
1602 201a51fc balrog
struct pcmcia_socket_s {
1603 201a51fc balrog
    qemu_irq irq;
1604 201a51fc balrog
    int attached;
1605 201a51fc balrog
    const char *slot_string;
1606 201a51fc balrog
    const char *card_string;
1607 201a51fc balrog
};
1608 201a51fc balrog
1609 201a51fc balrog
void pcmcia_socket_register(struct pcmcia_socket_s *socket);
1610 201a51fc balrog
void pcmcia_socket_unregister(struct pcmcia_socket_s *socket);
1611 201a51fc balrog
void pcmcia_info(void);
1612 201a51fc balrog
1613 201a51fc balrog
struct pcmcia_card_s {
1614 201a51fc balrog
    void *state;
1615 201a51fc balrog
    struct pcmcia_socket_s *slot;
1616 201a51fc balrog
    int (*attach)(void *state);
1617 201a51fc balrog
    int (*detach)(void *state);
1618 201a51fc balrog
    const uint8_t *cis;
1619 201a51fc balrog
    int cis_len;
1620 201a51fc balrog
1621 201a51fc balrog
    /* Only valid if attached */
1622 9e315fa9 balrog
    uint8_t (*attr_read)(void *state, uint32_t address);
1623 9e315fa9 balrog
    void (*attr_write)(void *state, uint32_t address, uint8_t value);
1624 9e315fa9 balrog
    uint16_t (*common_read)(void *state, uint32_t address);
1625 9e315fa9 balrog
    void (*common_write)(void *state, uint32_t address, uint16_t value);
1626 9e315fa9 balrog
    uint16_t (*io_read)(void *state, uint32_t address);
1627 9e315fa9 balrog
    void (*io_write)(void *state, uint32_t address, uint16_t value);
1628 201a51fc balrog
};
1629 201a51fc balrog
1630 201a51fc balrog
#define CISTPL_DEVICE                0x01        /* 5V Device Information Tuple */
1631 201a51fc balrog
#define CISTPL_NO_LINK                0x14        /* No Link Tuple */
1632 201a51fc balrog
#define CISTPL_VERS_1                0x15        /* Level 1 Version Tuple */
1633 201a51fc balrog
#define CISTPL_JEDEC_C                0x18        /* JEDEC ID Tuple */
1634 201a51fc balrog
#define CISTPL_JEDEC_A                0x19        /* JEDEC ID Tuple */
1635 201a51fc balrog
#define CISTPL_CONFIG                0x1a        /* Configuration Tuple */
1636 201a51fc balrog
#define CISTPL_CFTABLE_ENTRY        0x1b        /* 16-bit PCCard Configuration */
1637 201a51fc balrog
#define CISTPL_DEVICE_OC        0x1c        /* Additional Device Information */
1638 201a51fc balrog
#define CISTPL_DEVICE_OA        0x1d        /* Additional Device Information */
1639 201a51fc balrog
#define CISTPL_DEVICE_GEO        0x1e        /* Additional Device Information */
1640 201a51fc balrog
#define CISTPL_DEVICE_GEO_A        0x1f        /* Additional Device Information */
1641 201a51fc balrog
#define CISTPL_MANFID                0x20        /* Manufacture ID Tuple */
1642 201a51fc balrog
#define CISTPL_FUNCID                0x21        /* Function ID Tuple */
1643 201a51fc balrog
#define CISTPL_FUNCE                0x22        /* Function Extension Tuple */
1644 201a51fc balrog
#define CISTPL_END                0xff        /* Tuple End */
1645 201a51fc balrog
#define CISTPL_ENDMARK                0xff
1646 201a51fc balrog
1647 201a51fc balrog
/* dscm1xxxx.c */
1648 201a51fc balrog
struct pcmcia_card_s *dscm1xxxx_init(BlockDriverState *bdrv);
1649 201a51fc balrog
1650 6963d7af pbrook
/* ptimer.c */
1651 6963d7af pbrook
typedef struct ptimer_state ptimer_state;
1652 6963d7af pbrook
typedef void (*ptimer_cb)(void *opaque);
1653 6963d7af pbrook
1654 6963d7af pbrook
ptimer_state *ptimer_init(QEMUBH *bh);
1655 6963d7af pbrook
void ptimer_set_period(ptimer_state *s, int64_t period);
1656 6963d7af pbrook
void ptimer_set_freq(ptimer_state *s, uint32_t freq);
1657 8d05ea8a blueswir1
void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload);
1658 8d05ea8a blueswir1
uint64_t ptimer_get_count(ptimer_state *s);
1659 8d05ea8a blueswir1
void ptimer_set_count(ptimer_state *s, uint64_t count);
1660 6963d7af pbrook
void ptimer_run(ptimer_state *s, int oneshot);
1661 6963d7af pbrook
void ptimer_stop(ptimer_state *s);
1662 8d05ea8a blueswir1
void qemu_put_ptimer(QEMUFile *f, ptimer_state *s);
1663 8d05ea8a blueswir1
void qemu_get_ptimer(QEMUFile *f, ptimer_state *s);
1664 6963d7af pbrook
1665 c1713132 balrog
#include "hw/pxa.h"
1666 c1713132 balrog
1667 c3d2689d balrog
#include "hw/omap.h"
1668 c3d2689d balrog
1669 3efda49d balrog
/* tsc210x.c */
1670 3efda49d balrog
struct uwire_slave_s *tsc2102_init(qemu_irq pint);
1671 3efda49d balrog
1672 20dcee94 pbrook
/* mcf_uart.c */
1673 20dcee94 pbrook
uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr);
1674 20dcee94 pbrook
void mcf_uart_write(void *opaque, target_phys_addr_t addr, uint32_t val);
1675 20dcee94 pbrook
void *mcf_uart_init(qemu_irq irq, CharDriverState *chr);
1676 20dcee94 pbrook
void mcf_uart_mm_init(target_phys_addr_t base, qemu_irq irq,
1677 20dcee94 pbrook
                      CharDriverState *chr);
1678 20dcee94 pbrook
1679 20dcee94 pbrook
/* mcf_intc.c */
1680 20dcee94 pbrook
qemu_irq *mcf_intc_init(target_phys_addr_t base, CPUState *env);
1681 20dcee94 pbrook
1682 7e049b8a pbrook
/* mcf_fec.c */
1683 7e049b8a pbrook
void mcf_fec_init(NICInfo *nd, target_phys_addr_t base, qemu_irq *irq);
1684 7e049b8a pbrook
1685 0633879f pbrook
/* mcf5206.c */
1686 0633879f pbrook
qemu_irq *mcf5206_init(uint32_t base, CPUState *env);
1687 0633879f pbrook
1688 0633879f pbrook
/* an5206.c */
1689 0633879f pbrook
extern QEMUMachine an5206_machine;
1690 0633879f pbrook
1691 20dcee94 pbrook
/* mcf5208.c */
1692 20dcee94 pbrook
extern QEMUMachine mcf5208evb_machine;
1693 20dcee94 pbrook
1694 4046d913 pbrook
#include "gdbstub.h"
1695 4046d913 pbrook
1696 ea2384d3 bellard
#endif /* defined(QEMU_TOOL) */
1697 ea2384d3 bellard
1698 c4b1fcc0 bellard
/* monitor.c */
1699 82c643ff bellard
void monitor_init(CharDriverState *hd, int show_banner);
1700 ea2384d3 bellard
void term_puts(const char *str);
1701 ea2384d3 bellard
void term_vprintf(const char *fmt, va_list ap);
1702 40c3bac3 bellard
void term_printf(const char *fmt, ...) __attribute__ ((__format__ (__printf__, 1, 2)));
1703 fef30743 ths
void term_print_filename(const char *filename);
1704 c4b1fcc0 bellard
void term_flush(void);
1705 c4b1fcc0 bellard
void term_print_help(void);
1706 ea2384d3 bellard
void monitor_readline(const char *prompt, int is_password,
1707 ea2384d3 bellard
                      char *buf, int buf_size);
1708 ea2384d3 bellard
1709 ea2384d3 bellard
/* readline.c */
1710 ea2384d3 bellard
typedef void ReadLineFunc(void *opaque, const char *str);
1711 ea2384d3 bellard
1712 ea2384d3 bellard
extern int completion_index;
1713 ea2384d3 bellard
void add_completion(const char *str);
1714 ea2384d3 bellard
void readline_handle_byte(int ch);
1715 ea2384d3 bellard
void readline_find_completion(const char *cmdline);
1716 ea2384d3 bellard
const char *readline_get_history(unsigned int index);
1717 ea2384d3 bellard
void readline_start(const char *prompt, int is_password,
1718 ea2384d3 bellard
                    ReadLineFunc *readline_func, void *opaque);
1719 c4b1fcc0 bellard
1720 5e6ad6f9 bellard
void kqemu_record_dump(void);
1721 5e6ad6f9 bellard
1722 fc01f7e7 bellard
#endif /* VL_H */