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/*
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 * QEMU System Emulator header
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 *
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 * Copyright (c) 2003 Fabrice Bellard
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#ifndef VL_H
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#define VL_H
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/* we put basic includes here to avoid repeating them in device drivers */
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#include <stdlib.h>
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#include <stdio.h>
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#include <stdarg.h>
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#include <string.h>
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#include <inttypes.h>
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#include <limits.h>
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#include <time.h>
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#include <ctype.h>
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#include <errno.h>
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#include <unistd.h>
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#include <fcntl.h>
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#include <sys/stat.h>
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#ifndef O_LARGEFILE
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#define O_LARGEFILE 0
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#endif
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#ifndef O_BINARY
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#define O_BINARY 0
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#endif
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#ifndef ENOMEDIUM
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#define ENOMEDIUM ENODEV
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#endif
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#ifdef _WIN32
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#include <windows.h>
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#define fsync _commit
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#define lseek _lseeki64
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#define ENOTSUP 4096
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extern int qemu_ftruncate64(int, int64_t);
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#define ftruncate qemu_ftruncate64
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static inline char *realpath(const char *path, char *resolved_path)
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{
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    _fullpath(resolved_path, path, _MAX_PATH);
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    return resolved_path;
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}
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#define PRId64 "I64d"
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#define PRIx64 "I64x"
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#define PRIu64 "I64u"
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#define PRIo64 "I64o"
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#endif
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#ifdef QEMU_TOOL
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/* we use QEMU_TOOL in the command line tools which do not depend on
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   the target CPU type */
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#include "config-host.h"
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#include <setjmp.h>
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#include "osdep.h"
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#include "bswap.h"
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#else
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#include "audio/audio.h"
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#include "cpu.h"
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#endif /* !defined(QEMU_TOOL) */
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#ifndef glue
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#define xglue(x, y) x ## y
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#define glue(x, y) xglue(x, y)
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#define stringify(s)        tostring(s)
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#define tostring(s)        #s
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#endif
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#ifndef likely
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#if __GNUC__ < 3
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#define __builtin_expect(x, n) (x)
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#endif
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#define likely(x)   __builtin_expect(!!(x), 1)
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#define unlikely(x)   __builtin_expect(!!(x), 0)
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#endif
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#ifndef MIN
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#define MIN(a, b) (((a) < (b)) ? (a) : (b))
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#endif
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#ifndef MAX
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#define MAX(a, b) (((a) > (b)) ? (a) : (b))
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#endif
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#ifndef always_inline
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#if (__GNUC__ < 3) || defined(__APPLE__)
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#define always_inline inline
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#else
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#define always_inline __attribute__ (( always_inline )) inline
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#endif
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#endif
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/* cutils.c */
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void pstrcpy(char *buf, int buf_size, const char *str);
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char *pstrcat(char *buf, int buf_size, const char *s);
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int strstart(const char *str, const char *val, const char **ptr);
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int stristart(const char *str, const char *val, const char **ptr);
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/* vl.c */
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uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c);
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void hw_error(const char *fmt, ...);
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extern const char *bios_dir;
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extern const char *bios_name;
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extern int vm_running;
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extern const char *qemu_name;
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typedef struct vm_change_state_entry VMChangeStateEntry;
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typedef void VMChangeStateHandler(void *opaque, int running);
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typedef void VMStopHandler(void *opaque, int reason);
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VMChangeStateEntry *qemu_add_vm_change_state_handler(VMChangeStateHandler *cb,
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                                                     void *opaque);
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void qemu_del_vm_change_state_handler(VMChangeStateEntry *e);
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int qemu_add_vm_stop_handler(VMStopHandler *cb, void *opaque);
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void qemu_del_vm_stop_handler(VMStopHandler *cb, void *opaque);
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void vm_start(void);
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void vm_stop(int reason);
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typedef void QEMUResetHandler(void *opaque);
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void qemu_register_reset(QEMUResetHandler *func, void *opaque);
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void qemu_system_reset_request(void);
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void qemu_system_shutdown_request(void);
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void qemu_system_powerdown_request(void);
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#if !defined(TARGET_SPARC)
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// Please implement a power failure function to signal the OS
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#define qemu_system_powerdown() do{}while(0)
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#else
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void qemu_system_powerdown(void);
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#endif
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void main_loop_wait(int timeout);
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extern int ram_size;
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extern int bios_size;
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extern int rtc_utc;
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extern int cirrus_vga_enabled;
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extern int vmsvga_enabled;
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extern int graphic_width;
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extern int graphic_height;
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extern int graphic_depth;
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extern const char *keyboard_layout;
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extern int kqemu_allowed;
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extern int win2k_install_hack;
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extern int alt_grab;
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extern int usb_enabled;
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extern int smp_cpus;
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extern int cursor_hide;
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extern int graphic_rotate;
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extern int no_quit;
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extern int semihosting_enabled;
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extern int autostart;
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extern int old_param;
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extern const char *bootp_filename;
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#define MAX_OPTION_ROMS 16
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extern const char *option_rom[MAX_OPTION_ROMS];
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extern int nb_option_roms;
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#ifdef TARGET_SPARC
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#define MAX_PROM_ENVS 128
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extern const char *prom_envs[MAX_PROM_ENVS];
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extern unsigned int nb_prom_envs;
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#endif
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/* XXX: make it dynamic */
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#define MAX_BIOS_SIZE (4 * 1024 * 1024)
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#if defined (TARGET_PPC)
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#define BIOS_SIZE (1024 * 1024)
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#elif defined (TARGET_SPARC64)
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#define BIOS_SIZE ((512 + 32) * 1024)
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#elif defined(TARGET_MIPS)
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#define BIOS_SIZE (4 * 1024 * 1024)
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#endif
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/* keyboard/mouse support */
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#define MOUSE_EVENT_LBUTTON 0x01
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#define MOUSE_EVENT_RBUTTON 0x02
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#define MOUSE_EVENT_MBUTTON 0x04
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typedef void QEMUPutKBDEvent(void *opaque, int keycode);
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typedef void QEMUPutMouseEvent(void *opaque, int dx, int dy, int dz, int buttons_state);
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typedef struct QEMUPutMouseEntry {
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    QEMUPutMouseEvent *qemu_put_mouse_event;
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    void *qemu_put_mouse_event_opaque;
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    int qemu_put_mouse_event_absolute;
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    char *qemu_put_mouse_event_name;
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    /* used internally by qemu for handling mice */
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    struct QEMUPutMouseEntry *next;
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} QEMUPutMouseEntry;
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void qemu_add_kbd_event_handler(QEMUPutKBDEvent *func, void *opaque);
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QEMUPutMouseEntry *qemu_add_mouse_event_handler(QEMUPutMouseEvent *func,
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                                                void *opaque, int absolute,
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                                                const char *name);
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void qemu_remove_mouse_event_handler(QEMUPutMouseEntry *entry);
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void kbd_put_keycode(int keycode);
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void kbd_mouse_event(int dx, int dy, int dz, int buttons_state);
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int kbd_mouse_is_absolute(void);
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void do_info_mice(void);
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void do_mouse_set(int index);
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/* keysym is a unicode code except for special keys (see QEMU_KEY_xxx
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   constants) */
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#define QEMU_KEY_ESC1(c) ((c) | 0xe100)
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#define QEMU_KEY_BACKSPACE  0x007f
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#define QEMU_KEY_UP         QEMU_KEY_ESC1('A')
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#define QEMU_KEY_DOWN       QEMU_KEY_ESC1('B')
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#define QEMU_KEY_RIGHT      QEMU_KEY_ESC1('C')
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#define QEMU_KEY_LEFT       QEMU_KEY_ESC1('D')
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#define QEMU_KEY_HOME       QEMU_KEY_ESC1(1)
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#define QEMU_KEY_END        QEMU_KEY_ESC1(4)
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#define QEMU_KEY_PAGEUP     QEMU_KEY_ESC1(5)
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#define QEMU_KEY_PAGEDOWN   QEMU_KEY_ESC1(6)
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#define QEMU_KEY_DELETE     QEMU_KEY_ESC1(3)
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#define QEMU_KEY_CTRL_UP         0xe400
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#define QEMU_KEY_CTRL_DOWN       0xe401
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#define QEMU_KEY_CTRL_LEFT       0xe402
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#define QEMU_KEY_CTRL_RIGHT      0xe403
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#define QEMU_KEY_CTRL_HOME       0xe404
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#define QEMU_KEY_CTRL_END        0xe405
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#define QEMU_KEY_CTRL_PAGEUP     0xe406
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#define QEMU_KEY_CTRL_PAGEDOWN   0xe407
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void kbd_put_keysym(int keysym);
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/* async I/O support */
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typedef void IOReadHandler(void *opaque, const uint8_t *buf, int size);
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typedef int IOCanRWHandler(void *opaque);
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typedef void IOHandler(void *opaque);
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int qemu_set_fd_handler2(int fd,
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                         IOCanRWHandler *fd_read_poll,
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                         IOHandler *fd_read,
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                         IOHandler *fd_write,
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                         void *opaque);
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int qemu_set_fd_handler(int fd,
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                        IOHandler *fd_read,
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                        IOHandler *fd_write,
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                        void *opaque);
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/* Polling handling */
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/* return TRUE if no sleep should be done afterwards */
284
typedef int PollingFunc(void *opaque);
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int qemu_add_polling_cb(PollingFunc *func, void *opaque);
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void qemu_del_polling_cb(PollingFunc *func, void *opaque);
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#ifdef _WIN32
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/* Wait objects handling */
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typedef void WaitObjectFunc(void *opaque);
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int qemu_add_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
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void qemu_del_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
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#endif
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typedef struct QEMUBH QEMUBH;
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/* character device */
300

    
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#define CHR_EVENT_BREAK 0 /* serial break char */
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#define CHR_EVENT_FOCUS 1 /* focus to this terminal (modal input needed) */
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#define CHR_EVENT_RESET 2 /* new connection established */
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#define CHR_IOCTL_SERIAL_SET_PARAMS   1
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typedef struct {
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    int speed;
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    int parity;
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    int data_bits;
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    int stop_bits;
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} QEMUSerialSetParams;
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#define CHR_IOCTL_SERIAL_SET_BREAK    2
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#define CHR_IOCTL_PP_READ_DATA        3
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#define CHR_IOCTL_PP_WRITE_DATA       4
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#define CHR_IOCTL_PP_READ_CONTROL     5
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#define CHR_IOCTL_PP_WRITE_CONTROL    6
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#define CHR_IOCTL_PP_READ_STATUS      7
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#define CHR_IOCTL_PP_EPP_READ_ADDR    8
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#define CHR_IOCTL_PP_EPP_READ         9
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#define CHR_IOCTL_PP_EPP_WRITE_ADDR  10
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#define CHR_IOCTL_PP_EPP_WRITE       11
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typedef void IOEventHandler(void *opaque, int event);
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typedef struct CharDriverState {
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    int (*chr_write)(struct CharDriverState *s, const uint8_t *buf, int len);
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    void (*chr_update_read_handler)(struct CharDriverState *s);
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    int (*chr_ioctl)(struct CharDriverState *s, int cmd, void *arg);
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    IOEventHandler *chr_event;
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    IOCanRWHandler *chr_can_read;
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    IOReadHandler *chr_read;
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    void *handler_opaque;
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    void (*chr_send_event)(struct CharDriverState *chr, int event);
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    void (*chr_close)(struct CharDriverState *chr);
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    void *opaque;
339
    int focus;
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    QEMUBH *bh;
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} CharDriverState;
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CharDriverState *qemu_chr_open(const char *filename);
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void qemu_chr_printf(CharDriverState *s, const char *fmt, ...);
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int qemu_chr_write(CharDriverState *s, const uint8_t *buf, int len);
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void qemu_chr_send_event(CharDriverState *s, int event);
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void qemu_chr_add_handlers(CharDriverState *s,
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                           IOCanRWHandler *fd_can_read,
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                           IOReadHandler *fd_read,
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                           IOEventHandler *fd_event,
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                           void *opaque);
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int qemu_chr_ioctl(CharDriverState *s, int cmd, void *arg);
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void qemu_chr_reset(CharDriverState *s);
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int qemu_chr_can_read(CharDriverState *s);
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void qemu_chr_read(CharDriverState *s, uint8_t *buf, int len);
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/* consoles */
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typedef struct DisplayState DisplayState;
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typedef struct TextConsole TextConsole;
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typedef void (*vga_hw_update_ptr)(void *);
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typedef void (*vga_hw_invalidate_ptr)(void *);
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typedef void (*vga_hw_screen_dump_ptr)(void *, const char *);
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TextConsole *graphic_console_init(DisplayState *ds, vga_hw_update_ptr update,
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                                  vga_hw_invalidate_ptr invalidate,
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                                  vga_hw_screen_dump_ptr screen_dump,
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                                  void *opaque);
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void vga_hw_update(void);
371
void vga_hw_invalidate(void);
372
void vga_hw_screen_dump(const char *filename);
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int is_graphic_console(void);
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CharDriverState *text_console_init(DisplayState *ds, const char *p);
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void console_select(unsigned int index);
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void console_color_init(DisplayState *ds);
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/* serial ports */
380

    
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#define MAX_SERIAL_PORTS 4
382

    
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extern CharDriverState *serial_hds[MAX_SERIAL_PORTS];
384

    
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/* parallel ports */
386

    
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#define MAX_PARALLEL_PORTS 3
388

    
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extern CharDriverState *parallel_hds[MAX_PARALLEL_PORTS];
390

    
391
struct ParallelIOArg {
392
    void *buffer;
393
    int count;
394
};
395

    
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/* VLANs support */
397

    
398
typedef struct VLANClientState VLANClientState;
399

    
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struct VLANClientState {
401
    IOReadHandler *fd_read;
402
    /* Packets may still be sent if this returns zero.  It's used to
403
       rate-limit the slirp code.  */
404
    IOCanRWHandler *fd_can_read;
405
    void *opaque;
406
    struct VLANClientState *next;
407
    struct VLANState *vlan;
408
    char info_str[256];
409
};
410

    
411
typedef struct VLANState {
412
    int id;
413
    VLANClientState *first_client;
414
    struct VLANState *next;
415
    unsigned int nb_guest_devs, nb_host_devs;
416
} VLANState;
417

    
418
VLANState *qemu_find_vlan(int id);
419
VLANClientState *qemu_new_vlan_client(VLANState *vlan,
420
                                      IOReadHandler *fd_read,
421
                                      IOCanRWHandler *fd_can_read,
422
                                      void *opaque);
423
int qemu_can_send_packet(VLANClientState *vc);
424
void qemu_send_packet(VLANClientState *vc, const uint8_t *buf, int size);
425
void qemu_handler_true(void *opaque);
426

    
427
void do_info_network(void);
428

    
429
/* TAP win32 */
430
int tap_win32_init(VLANState *vlan, const char *ifname);
431

    
432
/* NIC info */
433

    
434
#define MAX_NICS 8
435

    
436
typedef struct NICInfo {
437
    uint8_t macaddr[6];
438
    const char *model;
439
    VLANState *vlan;
440
} NICInfo;
441

    
442
extern int nb_nics;
443
extern NICInfo nd_table[MAX_NICS];
444

    
445
/* SLIRP */
446
void do_info_slirp(void);
447

    
448
/* timers */
449

    
450
typedef struct QEMUClock QEMUClock;
451
typedef struct QEMUTimer QEMUTimer;
452
typedef void QEMUTimerCB(void *opaque);
453

    
454
/* The real time clock should be used only for stuff which does not
455
   change the virtual machine state, as it is run even if the virtual
456
   machine is stopped. The real time clock has a frequency of 1000
457
   Hz. */
458
extern QEMUClock *rt_clock;
459

    
460
/* The virtual clock is only run during the emulation. It is stopped
461
   when the virtual machine is stopped. Virtual timers use a high
462
   precision clock, usually cpu cycles (use ticks_per_sec). */
463
extern QEMUClock *vm_clock;
464

    
465
int64_t qemu_get_clock(QEMUClock *clock);
466

    
467
QEMUTimer *qemu_new_timer(QEMUClock *clock, QEMUTimerCB *cb, void *opaque);
468
void qemu_free_timer(QEMUTimer *ts);
469
void qemu_del_timer(QEMUTimer *ts);
470
void qemu_mod_timer(QEMUTimer *ts, int64_t expire_time);
471
int qemu_timer_pending(QEMUTimer *ts);
472

    
473
extern int64_t ticks_per_sec;
474

    
475
int64_t cpu_get_ticks(void);
476
void cpu_enable_ticks(void);
477
void cpu_disable_ticks(void);
478

    
479
/* VM Load/Save */
480

    
481
typedef struct QEMUFile QEMUFile;
482

    
483
QEMUFile *qemu_fopen(const char *filename, const char *mode);
484
void qemu_fflush(QEMUFile *f);
485
void qemu_fclose(QEMUFile *f);
486
void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, int size);
487
void qemu_put_byte(QEMUFile *f, int v);
488
void qemu_put_be16(QEMUFile *f, unsigned int v);
489
void qemu_put_be32(QEMUFile *f, unsigned int v);
490
void qemu_put_be64(QEMUFile *f, uint64_t v);
491
int qemu_get_buffer(QEMUFile *f, uint8_t *buf, int size);
492
int qemu_get_byte(QEMUFile *f);
493
unsigned int qemu_get_be16(QEMUFile *f);
494
unsigned int qemu_get_be32(QEMUFile *f);
495
uint64_t qemu_get_be64(QEMUFile *f);
496

    
497
static inline void qemu_put_be64s(QEMUFile *f, const uint64_t *pv)
498
{
499
    qemu_put_be64(f, *pv);
500
}
501

    
502
static inline void qemu_put_be32s(QEMUFile *f, const uint32_t *pv)
503
{
504
    qemu_put_be32(f, *pv);
505
}
506

    
507
static inline void qemu_put_be16s(QEMUFile *f, const uint16_t *pv)
508
{
509
    qemu_put_be16(f, *pv);
510
}
511

    
512
static inline void qemu_put_8s(QEMUFile *f, const uint8_t *pv)
513
{
514
    qemu_put_byte(f, *pv);
515
}
516

    
517
static inline void qemu_get_be64s(QEMUFile *f, uint64_t *pv)
518
{
519
    *pv = qemu_get_be64(f);
520
}
521

    
522
static inline void qemu_get_be32s(QEMUFile *f, uint32_t *pv)
523
{
524
    *pv = qemu_get_be32(f);
525
}
526

    
527
static inline void qemu_get_be16s(QEMUFile *f, uint16_t *pv)
528
{
529
    *pv = qemu_get_be16(f);
530
}
531

    
532
static inline void qemu_get_8s(QEMUFile *f, uint8_t *pv)
533
{
534
    *pv = qemu_get_byte(f);
535
}
536

    
537
#if TARGET_LONG_BITS == 64
538
#define qemu_put_betl qemu_put_be64
539
#define qemu_get_betl qemu_get_be64
540
#define qemu_put_betls qemu_put_be64s
541
#define qemu_get_betls qemu_get_be64s
542
#else
543
#define qemu_put_betl qemu_put_be32
544
#define qemu_get_betl qemu_get_be32
545
#define qemu_put_betls qemu_put_be32s
546
#define qemu_get_betls qemu_get_be32s
547
#endif
548

    
549
int64_t qemu_ftell(QEMUFile *f);
550
int64_t qemu_fseek(QEMUFile *f, int64_t pos, int whence);
551

    
552
typedef void SaveStateHandler(QEMUFile *f, void *opaque);
553
typedef int LoadStateHandler(QEMUFile *f, void *opaque, int version_id);
554

    
555
int register_savevm(const char *idstr,
556
                    int instance_id,
557
                    int version_id,
558
                    SaveStateHandler *save_state,
559
                    LoadStateHandler *load_state,
560
                    void *opaque);
561
void qemu_get_timer(QEMUFile *f, QEMUTimer *ts);
562
void qemu_put_timer(QEMUFile *f, QEMUTimer *ts);
563

    
564
void cpu_save(QEMUFile *f, void *opaque);
565
int cpu_load(QEMUFile *f, void *opaque, int version_id);
566

    
567
void do_savevm(const char *name);
568
void do_loadvm(const char *name);
569
void do_delvm(const char *name);
570
void do_info_snapshots(void);
571

    
572
/* bottom halves */
573
typedef void QEMUBHFunc(void *opaque);
574

    
575
QEMUBH *qemu_bh_new(QEMUBHFunc *cb, void *opaque);
576
void qemu_bh_schedule(QEMUBH *bh);
577
void qemu_bh_cancel(QEMUBH *bh);
578
void qemu_bh_delete(QEMUBH *bh);
579
int qemu_bh_poll(void);
580

    
581
/* block.c */
582
typedef struct BlockDriverState BlockDriverState;
583
typedef struct BlockDriver BlockDriver;
584

    
585
extern BlockDriver bdrv_raw;
586
extern BlockDriver bdrv_host_device;
587
extern BlockDriver bdrv_cow;
588
extern BlockDriver bdrv_qcow;
589
extern BlockDriver bdrv_vmdk;
590
extern BlockDriver bdrv_cloop;
591
extern BlockDriver bdrv_dmg;
592
extern BlockDriver bdrv_bochs;
593
extern BlockDriver bdrv_vpc;
594
extern BlockDriver bdrv_vvfat;
595
extern BlockDriver bdrv_qcow2;
596
extern BlockDriver bdrv_parallels;
597

    
598
typedef struct BlockDriverInfo {
599
    /* in bytes, 0 if irrelevant */
600
    int cluster_size;
601
    /* offset at which the VM state can be saved (0 if not possible) */
602
    int64_t vm_state_offset;
603
} BlockDriverInfo;
604

    
605
typedef struct QEMUSnapshotInfo {
606
    char id_str[128]; /* unique snapshot id */
607
    /* the following fields are informative. They are not needed for
608
       the consistency of the snapshot */
609
    char name[256]; /* user choosen name */
610
    uint32_t vm_state_size; /* VM state info size */
611
    uint32_t date_sec; /* UTC date of the snapshot */
612
    uint32_t date_nsec;
613
    uint64_t vm_clock_nsec; /* VM clock relative to boot */
614
} QEMUSnapshotInfo;
615

    
616
#define BDRV_O_RDONLY      0x0000
617
#define BDRV_O_RDWR        0x0002
618
#define BDRV_O_ACCESS      0x0003
619
#define BDRV_O_CREAT       0x0004 /* create an empty file */
620
#define BDRV_O_SNAPSHOT    0x0008 /* open the file read only and save writes in a snapshot */
621
#define BDRV_O_FILE        0x0010 /* open as a raw file (do not try to
622
                                     use a disk image format on top of
623
                                     it (default for
624
                                     bdrv_file_open()) */
625

    
626
void bdrv_init(void);
627
BlockDriver *bdrv_find_format(const char *format_name);
628
int bdrv_create(BlockDriver *drv,
629
                const char *filename, int64_t size_in_sectors,
630
                const char *backing_file, int flags);
631
BlockDriverState *bdrv_new(const char *device_name);
632
void bdrv_delete(BlockDriverState *bs);
633
int bdrv_file_open(BlockDriverState **pbs, const char *filename, int flags);
634
int bdrv_open(BlockDriverState *bs, const char *filename, int flags);
635
int bdrv_open2(BlockDriverState *bs, const char *filename, int flags,
636
               BlockDriver *drv);
637
void bdrv_close(BlockDriverState *bs);
638
int bdrv_read(BlockDriverState *bs, int64_t sector_num,
639
              uint8_t *buf, int nb_sectors);
640
int bdrv_write(BlockDriverState *bs, int64_t sector_num,
641
               const uint8_t *buf, int nb_sectors);
642
int bdrv_pread(BlockDriverState *bs, int64_t offset,
643
               void *buf, int count);
644
int bdrv_pwrite(BlockDriverState *bs, int64_t offset,
645
                const void *buf, int count);
646
int bdrv_truncate(BlockDriverState *bs, int64_t offset);
647
int64_t bdrv_getlength(BlockDriverState *bs);
648
void bdrv_get_geometry(BlockDriverState *bs, int64_t *nb_sectors_ptr);
649
int bdrv_commit(BlockDriverState *bs);
650
void bdrv_set_boot_sector(BlockDriverState *bs, const uint8_t *data, int size);
651
/* async block I/O */
652
typedef struct BlockDriverAIOCB BlockDriverAIOCB;
653
typedef void BlockDriverCompletionFunc(void *opaque, int ret);
654

    
655
BlockDriverAIOCB *bdrv_aio_read(BlockDriverState *bs, int64_t sector_num,
656
                                uint8_t *buf, int nb_sectors,
657
                                BlockDriverCompletionFunc *cb, void *opaque);
658
BlockDriverAIOCB *bdrv_aio_write(BlockDriverState *bs, int64_t sector_num,
659
                                 const uint8_t *buf, int nb_sectors,
660
                                 BlockDriverCompletionFunc *cb, void *opaque);
661
void bdrv_aio_cancel(BlockDriverAIOCB *acb);
662

    
663
void qemu_aio_init(void);
664
void qemu_aio_poll(void);
665
void qemu_aio_flush(void);
666
void qemu_aio_wait_start(void);
667
void qemu_aio_wait(void);
668
void qemu_aio_wait_end(void);
669

    
670
int qemu_key_check(BlockDriverState *bs, const char *name);
671

    
672
/* Ensure contents are flushed to disk.  */
673
void bdrv_flush(BlockDriverState *bs);
674

    
675
#define BDRV_TYPE_HD     0
676
#define BDRV_TYPE_CDROM  1
677
#define BDRV_TYPE_FLOPPY 2
678
#define BIOS_ATA_TRANSLATION_AUTO   0
679
#define BIOS_ATA_TRANSLATION_NONE   1
680
#define BIOS_ATA_TRANSLATION_LBA    2
681
#define BIOS_ATA_TRANSLATION_LARGE  3
682
#define BIOS_ATA_TRANSLATION_RECHS  4
683

    
684
void bdrv_set_geometry_hint(BlockDriverState *bs,
685
                            int cyls, int heads, int secs);
686
void bdrv_set_type_hint(BlockDriverState *bs, int type);
687
void bdrv_set_translation_hint(BlockDriverState *bs, int translation);
688
void bdrv_get_geometry_hint(BlockDriverState *bs,
689
                            int *pcyls, int *pheads, int *psecs);
690
int bdrv_get_type_hint(BlockDriverState *bs);
691
int bdrv_get_translation_hint(BlockDriverState *bs);
692
int bdrv_is_removable(BlockDriverState *bs);
693
int bdrv_is_read_only(BlockDriverState *bs);
694
int bdrv_is_inserted(BlockDriverState *bs);
695
int bdrv_media_changed(BlockDriverState *bs);
696
int bdrv_is_locked(BlockDriverState *bs);
697
void bdrv_set_locked(BlockDriverState *bs, int locked);
698
void bdrv_eject(BlockDriverState *bs, int eject_flag);
699
void bdrv_set_change_cb(BlockDriverState *bs,
700
                        void (*change_cb)(void *opaque), void *opaque);
701
void bdrv_get_format(BlockDriverState *bs, char *buf, int buf_size);
702
void bdrv_info(void);
703
BlockDriverState *bdrv_find(const char *name);
704
void bdrv_iterate(void (*it)(void *opaque, const char *name), void *opaque);
705
int bdrv_is_encrypted(BlockDriverState *bs);
706
int bdrv_set_key(BlockDriverState *bs, const char *key);
707
void bdrv_iterate_format(void (*it)(void *opaque, const char *name),
708
                         void *opaque);
709
const char *bdrv_get_device_name(BlockDriverState *bs);
710
int bdrv_write_compressed(BlockDriverState *bs, int64_t sector_num,
711
                          const uint8_t *buf, int nb_sectors);
712
int bdrv_get_info(BlockDriverState *bs, BlockDriverInfo *bdi);
713

    
714
void bdrv_get_backing_filename(BlockDriverState *bs,
715
                               char *filename, int filename_size);
716
int bdrv_snapshot_create(BlockDriverState *bs,
717
                         QEMUSnapshotInfo *sn_info);
718
int bdrv_snapshot_goto(BlockDriverState *bs,
719
                       const char *snapshot_id);
720
int bdrv_snapshot_delete(BlockDriverState *bs, const char *snapshot_id);
721
int bdrv_snapshot_list(BlockDriverState *bs,
722
                       QEMUSnapshotInfo **psn_info);
723
char *bdrv_snapshot_dump(char *buf, int buf_size, QEMUSnapshotInfo *sn);
724

    
725
char *get_human_readable_size(char *buf, int buf_size, int64_t size);
726
int path_is_absolute(const char *path);
727
void path_combine(char *dest, int dest_size,
728
                  const char *base_path,
729
                  const char *filename);
730

    
731
#ifndef QEMU_TOOL
732

    
733
typedef void QEMUMachineInitFunc(int ram_size, int vga_ram_size,
734
                                 const char *boot_device,
735
             DisplayState *ds, const char **fd_filename, int snapshot,
736
             const char *kernel_filename, const char *kernel_cmdline,
737
             const char *initrd_filename, const char *cpu_model);
738

    
739
typedef struct QEMUMachine {
740
    const char *name;
741
    const char *desc;
742
    QEMUMachineInitFunc *init;
743
    struct QEMUMachine *next;
744
} QEMUMachine;
745

    
746
int qemu_register_machine(QEMUMachine *m);
747

    
748
typedef void SetIRQFunc(void *opaque, int irq_num, int level);
749

    
750
#include "hw/irq.h"
751

    
752
/* ISA bus */
753

    
754
extern target_phys_addr_t isa_mem_base;
755

    
756
typedef void (IOPortWriteFunc)(void *opaque, uint32_t address, uint32_t data);
757
typedef uint32_t (IOPortReadFunc)(void *opaque, uint32_t address);
758

    
759
int register_ioport_read(int start, int length, int size,
760
                         IOPortReadFunc *func, void *opaque);
761
int register_ioport_write(int start, int length, int size,
762
                          IOPortWriteFunc *func, void *opaque);
763
void isa_unassign_ioport(int start, int length);
764

    
765
void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
766

    
767
/* PCI bus */
768

    
769
extern target_phys_addr_t pci_mem_base;
770

    
771
typedef struct PCIBus PCIBus;
772
typedef struct PCIDevice PCIDevice;
773

    
774
typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
775
                                uint32_t address, uint32_t data, int len);
776
typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
777
                                   uint32_t address, int len);
778
typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
779
                                uint32_t addr, uint32_t size, int type);
780

    
781
#define PCI_ADDRESS_SPACE_MEM                0x00
782
#define PCI_ADDRESS_SPACE_IO                0x01
783
#define PCI_ADDRESS_SPACE_MEM_PREFETCH        0x08
784

    
785
typedef struct PCIIORegion {
786
    uint32_t addr; /* current PCI mapping address. -1 means not mapped */
787
    uint32_t size;
788
    uint8_t type;
789
    PCIMapIORegionFunc *map_func;
790
} PCIIORegion;
791

    
792
#define PCI_ROM_SLOT 6
793
#define PCI_NUM_REGIONS 7
794

    
795
#define PCI_DEVICES_MAX 64
796

    
797
#define PCI_VENDOR_ID                0x00        /* 16 bits */
798
#define PCI_DEVICE_ID                0x02        /* 16 bits */
799
#define PCI_COMMAND                0x04        /* 16 bits */
800
#define  PCI_COMMAND_IO                0x1        /* Enable response in I/O space */
801
#define  PCI_COMMAND_MEMORY        0x2        /* Enable response in Memory space */
802
#define PCI_CLASS_DEVICE        0x0a    /* Device class */
803
#define PCI_INTERRUPT_LINE        0x3c        /* 8 bits */
804
#define PCI_INTERRUPT_PIN        0x3d        /* 8 bits */
805
#define PCI_MIN_GNT                0x3e        /* 8 bits */
806
#define PCI_MAX_LAT                0x3f        /* 8 bits */
807

    
808
struct PCIDevice {
809
    /* PCI config space */
810
    uint8_t config[256];
811

    
812
    /* the following fields are read only */
813
    PCIBus *bus;
814
    int devfn;
815
    char name[64];
816
    PCIIORegion io_regions[PCI_NUM_REGIONS];
817

    
818
    /* do not access the following fields */
819
    PCIConfigReadFunc *config_read;
820
    PCIConfigWriteFunc *config_write;
821
    /* ??? This is a PC-specific hack, and should be removed.  */
822
    int irq_index;
823

    
824
    /* IRQ objects for the INTA-INTD pins.  */
825
    qemu_irq *irq;
826

    
827
    /* Current IRQ levels.  Used internally by the generic PCI code.  */
828
    int irq_state[4];
829
};
830

    
831
PCIDevice *pci_register_device(PCIBus *bus, const char *name,
832
                               int instance_size, int devfn,
833
                               PCIConfigReadFunc *config_read,
834
                               PCIConfigWriteFunc *config_write);
835

    
836
void pci_register_io_region(PCIDevice *pci_dev, int region_num,
837
                            uint32_t size, int type,
838
                            PCIMapIORegionFunc *map_func);
839

    
840
uint32_t pci_default_read_config(PCIDevice *d,
841
                                 uint32_t address, int len);
842
void pci_default_write_config(PCIDevice *d,
843
                              uint32_t address, uint32_t val, int len);
844
void pci_device_save(PCIDevice *s, QEMUFile *f);
845
int pci_device_load(PCIDevice *s, QEMUFile *f);
846

    
847
typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level);
848
typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
849
PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
850
                         qemu_irq *pic, int devfn_min, int nirq);
851

    
852
void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn);
853
void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
854
uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
855
int pci_bus_num(PCIBus *s);
856
void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d));
857

    
858
void pci_info(void);
859
PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
860
                        pci_map_irq_fn map_irq, const char *name);
861

    
862
/* prep_pci.c */
863
PCIBus *pci_prep_init(qemu_irq *pic);
864

    
865
/* apb_pci.c */
866
PCIBus *pci_apb_init(target_phys_addr_t special_base, target_phys_addr_t mem_base,
867
                     qemu_irq *pic);
868

    
869
PCIBus *pci_vpb_init(qemu_irq *pic, int irq, int realview);
870

    
871
/* piix_pci.c */
872
PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic);
873
void i440fx_set_smm(PCIDevice *d, int val);
874
int piix3_init(PCIBus *bus, int devfn);
875
void i440fx_init_memory_mappings(PCIDevice *d);
876

    
877
int piix4_init(PCIBus *bus, int devfn);
878

    
879
/* openpic.c */
880
/* OpenPIC have 5 outputs per CPU connected and one IRQ out single output */
881
enum {
882
    OPENPIC_OUTPUT_INT = 0, /* IRQ                       */
883
    OPENPIC_OUTPUT_CINT,    /* critical IRQ              */
884
    OPENPIC_OUTPUT_MCK,     /* Machine check event       */
885
    OPENPIC_OUTPUT_DEBUG,   /* Inconditional debug event */
886
    OPENPIC_OUTPUT_RESET,   /* Core reset event          */
887
    OPENPIC_OUTPUT_NB,
888
};
889
qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
890
                        qemu_irq **irqs, qemu_irq irq_out);
891

    
892
/* gt64xxx.c */
893
PCIBus *pci_gt64120_init(qemu_irq *pic);
894

    
895
#ifdef HAS_AUDIO
896
struct soundhw {
897
    const char *name;
898
    const char *descr;
899
    int enabled;
900
    int isa;
901
    union {
902
        int (*init_isa) (AudioState *s, qemu_irq *pic);
903
        int (*init_pci) (PCIBus *bus, AudioState *s);
904
    } init;
905
};
906

    
907
extern struct soundhw soundhw[];
908
#endif
909

    
910
/* vga.c */
911

    
912
#ifndef TARGET_SPARC
913
#define VGA_RAM_SIZE (8192 * 1024)
914
#else
915
#define VGA_RAM_SIZE (9 * 1024 * 1024)
916
#endif
917

    
918
struct DisplayState {
919
    uint8_t *data;
920
    int linesize;
921
    int depth;
922
    int bgr; /* BGR color order instead of RGB. Only valid for depth == 32 */
923
    int width;
924
    int height;
925
    void *opaque;
926
    QEMUTimer *gui_timer;
927

    
928
    void (*dpy_update)(struct DisplayState *s, int x, int y, int w, int h);
929
    void (*dpy_resize)(struct DisplayState *s, int w, int h);
930
    void (*dpy_refresh)(struct DisplayState *s);
931
    void (*dpy_copy)(struct DisplayState *s, int src_x, int src_y,
932
                     int dst_x, int dst_y, int w, int h);
933
    void (*dpy_fill)(struct DisplayState *s, int x, int y,
934
                     int w, int h, uint32_t c);
935
    void (*mouse_set)(int x, int y, int on);
936
    void (*cursor_define)(int width, int height, int bpp, int hot_x, int hot_y,
937
                          uint8_t *image, uint8_t *mask);
938
};
939

    
940
static inline void dpy_update(DisplayState *s, int x, int y, int w, int h)
941
{
942
    s->dpy_update(s, x, y, w, h);
943
}
944

    
945
static inline void dpy_resize(DisplayState *s, int w, int h)
946
{
947
    s->dpy_resize(s, w, h);
948
}
949

    
950
int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
951
                 unsigned long vga_ram_offset, int vga_ram_size);
952
int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
953
                 unsigned long vga_ram_offset, int vga_ram_size,
954
                 unsigned long vga_bios_offset, int vga_bios_size);
955
int isa_vga_mm_init(DisplayState *ds, uint8_t *vga_ram_base,
956
                    unsigned long vga_ram_offset, int vga_ram_size,
957
                    target_phys_addr_t vram_base, target_phys_addr_t ctrl_base,
958
                    int it_shift);
959

    
960
/* cirrus_vga.c */
961
void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
962
                         unsigned long vga_ram_offset, int vga_ram_size);
963
void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
964
                         unsigned long vga_ram_offset, int vga_ram_size);
965

    
966
/* vmware_vga.c */
967
void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
968
                     unsigned long vga_ram_offset, int vga_ram_size);
969

    
970
/* sdl.c */
971
void sdl_display_init(DisplayState *ds, int full_screen, int no_frame);
972

    
973
/* cocoa.m */
974
void cocoa_display_init(DisplayState *ds, int full_screen);
975

    
976
/* vnc.c */
977
void vnc_display_init(DisplayState *ds);
978
void vnc_display_close(DisplayState *ds);
979
int vnc_display_open(DisplayState *ds, const char *display);
980
int vnc_display_password(DisplayState *ds, const char *password);
981
void do_info_vnc(void);
982

    
983
/* x_keymap.c */
984
extern uint8_t _translate_keycode(const int key);
985

    
986
/* ide.c */
987
#define MAX_DISKS 4
988

    
989
extern BlockDriverState *bs_table[MAX_DISKS + 1];
990
extern BlockDriverState *sd_bdrv;
991
extern BlockDriverState *mtd_bdrv;
992

    
993
void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
994
                  BlockDriverState *hd0, BlockDriverState *hd1);
995
void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
996
                         int secondary_ide_enabled);
997
void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
998
                        qemu_irq *pic);
999
void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
1000
                        qemu_irq *pic);
1001

    
1002
/* cdrom.c */
1003
int cdrom_read_toc(int nb_sectors, uint8_t *buf, int msf, int start_track);
1004
int cdrom_read_toc_raw(int nb_sectors, uint8_t *buf, int msf, int session_num);
1005

    
1006
/* ds1225y.c */
1007
typedef struct ds1225y_t ds1225y_t;
1008
ds1225y_t *ds1225y_init(target_phys_addr_t mem_base, const char *filename);
1009

    
1010
/* es1370.c */
1011
int es1370_init (PCIBus *bus, AudioState *s);
1012

    
1013
/* sb16.c */
1014
int SB16_init (AudioState *s, qemu_irq *pic);
1015

    
1016
/* adlib.c */
1017
int Adlib_init (AudioState *s, qemu_irq *pic);
1018

    
1019
/* gus.c */
1020
int GUS_init (AudioState *s, qemu_irq *pic);
1021

    
1022
/* dma.c */
1023
typedef int (*DMA_transfer_handler) (void *opaque, int nchan, int pos, int size);
1024
int DMA_get_channel_mode (int nchan);
1025
int DMA_read_memory (int nchan, void *buf, int pos, int size);
1026
int DMA_write_memory (int nchan, void *buf, int pos, int size);
1027
void DMA_hold_DREQ (int nchan);
1028
void DMA_release_DREQ (int nchan);
1029
void DMA_schedule(int nchan);
1030
void DMA_run (void);
1031
void DMA_init (int high_page_enable);
1032
void DMA_register_channel (int nchan,
1033
                           DMA_transfer_handler transfer_handler,
1034
                           void *opaque);
1035
/* fdc.c */
1036
#define MAX_FD 2
1037
extern BlockDriverState *fd_table[MAX_FD];
1038

    
1039
typedef struct fdctrl_t fdctrl_t;
1040

    
1041
fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
1042
                       target_phys_addr_t io_base,
1043
                       BlockDriverState **fds);
1044
fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, target_phys_addr_t io_base,
1045
                             BlockDriverState **fds);
1046
int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num);
1047

    
1048
/* eepro100.c */
1049

    
1050
void pci_i82551_init(PCIBus *bus, NICInfo *nd, int devfn);
1051
void pci_i82557b_init(PCIBus *bus, NICInfo *nd, int devfn);
1052
void pci_i82559er_init(PCIBus *bus, NICInfo *nd, int devfn);
1053

    
1054
/* ne2000.c */
1055

    
1056
void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd);
1057
void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn);
1058

    
1059
/* rtl8139.c */
1060

    
1061
void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn);
1062

    
1063
/* pcnet.c */
1064

    
1065
void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn);
1066
void lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque,
1067
                qemu_irq irq, qemu_irq *reset);
1068

    
1069
/* mipsnet.c */
1070
void mipsnet_init(int base, qemu_irq irq, NICInfo *nd);
1071

    
1072
/* vmmouse.c */
1073
void *vmmouse_init(void *m);
1074

    
1075
/* vmport.c */
1076
#ifdef TARGET_I386
1077
void vmport_init(CPUState *env);
1078
void vmport_register(unsigned char command, IOPortReadFunc *func, void *opaque);
1079
#endif
1080

    
1081
/* pckbd.c */
1082

    
1083
void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
1084
void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
1085
                   target_phys_addr_t base, int it_shift);
1086

    
1087
/* mc146818rtc.c */
1088

    
1089
typedef struct RTCState RTCState;
1090

    
1091
RTCState *rtc_init(int base, qemu_irq irq);
1092
RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq);
1093
void rtc_set_memory(RTCState *s, int addr, int val);
1094
void rtc_set_date(RTCState *s, const struct tm *tm);
1095

    
1096
/* serial.c */
1097

    
1098
typedef struct SerialState SerialState;
1099
SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr);
1100
SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
1101
                             qemu_irq irq, CharDriverState *chr,
1102
                             int ioregister);
1103
uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr);
1104
void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value);
1105
uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr);
1106
void serial_mm_writew (void *opaque, target_phys_addr_t addr, uint32_t value);
1107
uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr);
1108
void serial_mm_writel (void *opaque, target_phys_addr_t addr, uint32_t value);
1109

    
1110
/* parallel.c */
1111

    
1112
typedef struct ParallelState ParallelState;
1113
ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr);
1114
ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr);
1115

    
1116
/* i8259.c */
1117

    
1118
typedef struct PicState2 PicState2;
1119
extern PicState2 *isa_pic;
1120
void pic_set_irq(int irq, int level);
1121
void pic_set_irq_new(void *opaque, int irq, int level);
1122
qemu_irq *i8259_init(qemu_irq parent_irq);
1123
void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
1124
                          void *alt_irq_opaque);
1125
int pic_read_irq(PicState2 *s);
1126
void pic_update_irq(PicState2 *s);
1127
uint32_t pic_intack_read(PicState2 *s);
1128
void pic_info(void);
1129
void irq_info(void);
1130

    
1131
/* APIC */
1132
typedef struct IOAPICState IOAPICState;
1133

    
1134
int apic_init(CPUState *env);
1135
int apic_accept_pic_intr(CPUState *env);
1136
int apic_get_interrupt(CPUState *env);
1137
IOAPICState *ioapic_init(void);
1138
void ioapic_set_irq(void *opaque, int vector, int level);
1139

    
1140
/* i8254.c */
1141

    
1142
#define PIT_FREQ 1193182
1143

    
1144
typedef struct PITState PITState;
1145

    
1146
PITState *pit_init(int base, qemu_irq irq);
1147
void pit_set_gate(PITState *pit, int channel, int val);
1148
int pit_get_gate(PITState *pit, int channel);
1149
int pit_get_initial_count(PITState *pit, int channel);
1150
int pit_get_mode(PITState *pit, int channel);
1151
int pit_get_out(PITState *pit, int channel, int64_t current_time);
1152

    
1153
/* jazz_led.c */
1154
extern void jazz_led_init(DisplayState *ds, target_phys_addr_t base);
1155

    
1156
/* pcspk.c */
1157
void pcspk_init(PITState *);
1158
int pcspk_audio_init(AudioState *, qemu_irq *pic);
1159

    
1160
#include "hw/i2c.h"
1161

    
1162
#include "hw/smbus.h"
1163

    
1164
/* acpi.c */
1165
extern int acpi_enabled;
1166
i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
1167
void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
1168
void acpi_bios_init(void);
1169

    
1170
/* Axis ETRAX.  */
1171
extern QEMUMachine bareetraxfs_machine;
1172

    
1173
/* pc.c */
1174
extern QEMUMachine pc_machine;
1175
extern QEMUMachine isapc_machine;
1176
extern int fd_bootchk;
1177

    
1178
void ioport_set_a20(int enable);
1179
int ioport_get_a20(void);
1180

    
1181
/* ppc.c */
1182
extern QEMUMachine prep_machine;
1183
extern QEMUMachine core99_machine;
1184
extern QEMUMachine heathrow_machine;
1185
extern QEMUMachine ref405ep_machine;
1186
extern QEMUMachine taihu_machine;
1187

    
1188
/* mips_r4k.c */
1189
extern QEMUMachine mips_machine;
1190

    
1191
/* mips_malta.c */
1192
extern QEMUMachine mips_malta_machine;
1193

    
1194
/* mips_pica61.c */
1195
extern QEMUMachine mips_pica61_machine;
1196

    
1197
/* mips_mipssim.c */
1198
extern QEMUMachine mips_mipssim_machine;
1199

    
1200
/* mips_int.c */
1201
extern void cpu_mips_irq_init_cpu(CPUState *env);
1202

    
1203
/* mips_timer.c */
1204
extern void cpu_mips_clock_init(CPUState *);
1205
extern void cpu_mips_irqctrl_init (void);
1206

    
1207
/* shix.c */
1208
extern QEMUMachine shix_machine;
1209

    
1210
/* r2d.c */
1211
extern QEMUMachine r2d_machine;
1212

    
1213
#ifdef TARGET_PPC
1214
/* PowerPC hardware exceptions management helpers */
1215
typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);
1216
typedef struct clk_setup_t clk_setup_t;
1217
struct clk_setup_t {
1218
    clk_setup_cb cb;
1219
    void *opaque;
1220
};
1221
static inline void clk_setup (clk_setup_t *clk, uint32_t freq)
1222
{
1223
    if (clk->cb != NULL)
1224
        (*clk->cb)(clk->opaque, freq);
1225
}
1226

    
1227
clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq);
1228
/* Embedded PowerPC DCR management */
1229
typedef target_ulong (*dcr_read_cb)(void *opaque, int dcrn);
1230
typedef void (*dcr_write_cb)(void *opaque, int dcrn, target_ulong val);
1231
int ppc_dcr_init (CPUState *env, int (*dcr_read_error)(int dcrn),
1232
                  int (*dcr_write_error)(int dcrn));
1233
int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
1234
                      dcr_read_cb drc_read, dcr_write_cb dcr_write);
1235
clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq);
1236
/* Embedded PowerPC reset */
1237
void ppc40x_core_reset (CPUState *env);
1238
void ppc40x_chip_reset (CPUState *env);
1239
void ppc40x_system_reset (CPUState *env);
1240
void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
1241

    
1242
extern CPUWriteMemoryFunc *PPC_io_write[];
1243
extern CPUReadMemoryFunc *PPC_io_read[];
1244
void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
1245
#endif
1246

    
1247
/* sun4m.c */
1248
extern QEMUMachine ss5_machine, ss10_machine;
1249

    
1250
/* iommu.c */
1251
void *iommu_init(target_phys_addr_t addr);
1252
void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
1253
                                 uint8_t *buf, int len, int is_write);
1254
static inline void sparc_iommu_memory_read(void *opaque,
1255
                                           target_phys_addr_t addr,
1256
                                           uint8_t *buf, int len)
1257
{
1258
    sparc_iommu_memory_rw(opaque, addr, buf, len, 0);
1259
}
1260

    
1261
static inline void sparc_iommu_memory_write(void *opaque,
1262
                                            target_phys_addr_t addr,
1263
                                            uint8_t *buf, int len)
1264
{
1265
    sparc_iommu_memory_rw(opaque, addr, buf, len, 1);
1266
}
1267

    
1268
/* tcx.c */
1269
void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base,
1270
              unsigned long vram_offset, int vram_size, int width, int height,
1271
              int depth);
1272

    
1273
/* slavio_intctl.c */
1274
void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
1275
                         const uint32_t *intbit_to_level,
1276
                         qemu_irq **irq, qemu_irq **cpu_irq,
1277
                         qemu_irq **parent_irq, unsigned int cputimer);
1278
void slavio_pic_info(void *opaque);
1279
void slavio_irq_info(void *opaque);
1280

    
1281
/* loader.c */
1282
int get_image_size(const char *filename);
1283
int load_image(const char *filename, uint8_t *addr);
1284
int load_elf(const char *filename, int64_t virt_to_phys_addend,
1285
             uint64_t *pentry, uint64_t *lowaddr, uint64_t *highaddr);
1286
int load_aout(const char *filename, uint8_t *addr);
1287
int load_uboot(const char *filename, target_ulong *ep, int *is_linux);
1288

    
1289
/* slavio_timer.c */
1290
void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq,
1291
                           qemu_irq *cpu_irqs);
1292

    
1293
/* slavio_serial.c */
1294
SerialState *slavio_serial_init(target_phys_addr_t base, qemu_irq irq,
1295
                                CharDriverState *chr1, CharDriverState *chr2);
1296
void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq);
1297

    
1298
/* slavio_misc.c */
1299
void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
1300
                       qemu_irq irq);
1301
void slavio_set_power_fail(void *opaque, int power_failing);
1302

    
1303
/* esp.c */
1304
void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1305
void *esp_init(BlockDriverState **bd, target_phys_addr_t espaddr,
1306
               void *dma_opaque, qemu_irq irq, qemu_irq *reset);
1307

    
1308
/* sparc32_dma.c */
1309
void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
1310
                       void *iommu, qemu_irq **dev_irq, qemu_irq **reset);
1311
void ledma_memory_read(void *opaque, target_phys_addr_t addr,
1312
                       uint8_t *buf, int len, int do_bswap);
1313
void ledma_memory_write(void *opaque, target_phys_addr_t addr,
1314
                        uint8_t *buf, int len, int do_bswap);
1315
void espdma_memory_read(void *opaque, uint8_t *buf, int len);
1316
void espdma_memory_write(void *opaque, uint8_t *buf, int len);
1317

    
1318
/* cs4231.c */
1319
void cs_init(target_phys_addr_t base, int irq, void *intctl);
1320

    
1321
/* sun4u.c */
1322
extern QEMUMachine sun4u_machine;
1323

    
1324
/* NVRAM helpers */
1325
typedef uint32_t (*nvram_read_t)(void *private, uint32_t addr);
1326
typedef void (*nvram_write_t)(void *private, uint32_t addr, uint32_t val);
1327
typedef struct nvram_t {
1328
    void *opaque;
1329
    nvram_read_t read_fn;
1330
    nvram_write_t write_fn;
1331
} nvram_t;
1332

    
1333
#include "hw/m48t59.h"
1334

    
1335
void NVRAM_set_byte (nvram_t *nvram, uint32_t addr, uint8_t value);
1336
uint8_t NVRAM_get_byte (nvram_t *nvram, uint32_t addr);
1337
void NVRAM_set_word (nvram_t *nvram, uint32_t addr, uint16_t value);
1338
uint16_t NVRAM_get_word (nvram_t *nvram, uint32_t addr);
1339
void NVRAM_set_lword (nvram_t *nvram, uint32_t addr, uint32_t value);
1340
uint32_t NVRAM_get_lword (nvram_t *nvram, uint32_t addr);
1341
void NVRAM_set_string (nvram_t *nvram, uint32_t addr,
1342
                       const unsigned char *str, uint32_t max);
1343
int NVRAM_get_string (nvram_t *nvram, uint8_t *dst, uint16_t addr, int max);
1344
void NVRAM_set_crc (nvram_t *nvram, uint32_t addr,
1345
                    uint32_t start, uint32_t count);
1346
int PPC_NVRAM_set_params (nvram_t *nvram, uint16_t NVRAM_size,
1347
                          const unsigned char *arch,
1348
                          uint32_t RAM_size, int boot_device,
1349
                          uint32_t kernel_image, uint32_t kernel_size,
1350
                          const char *cmdline,
1351
                          uint32_t initrd_image, uint32_t initrd_size,
1352
                          uint32_t NVRAM_image,
1353
                          int width, int height, int depth);
1354

    
1355
/* adb.c */
1356

    
1357
#define MAX_ADB_DEVICES 16
1358

    
1359
#define ADB_MAX_OUT_LEN 16
1360

    
1361
typedef struct ADBDevice ADBDevice;
1362

    
1363
/* buf = NULL means polling */
1364
typedef int ADBDeviceRequest(ADBDevice *d, uint8_t *buf_out,
1365
                              const uint8_t *buf, int len);
1366
typedef int ADBDeviceReset(ADBDevice *d);
1367

    
1368
struct ADBDevice {
1369
    struct ADBBusState *bus;
1370
    int devaddr;
1371
    int handler;
1372
    ADBDeviceRequest *devreq;
1373
    ADBDeviceReset *devreset;
1374
    void *opaque;
1375
};
1376

    
1377
typedef struct ADBBusState {
1378
    ADBDevice devices[MAX_ADB_DEVICES];
1379
    int nb_devices;
1380
    int poll_index;
1381
} ADBBusState;
1382

    
1383
int adb_request(ADBBusState *s, uint8_t *buf_out,
1384
                const uint8_t *buf, int len);
1385
int adb_poll(ADBBusState *s, uint8_t *buf_out);
1386

    
1387
ADBDevice *adb_register_device(ADBBusState *s, int devaddr,
1388
                               ADBDeviceRequest *devreq,
1389
                               ADBDeviceReset *devreset,
1390
                               void *opaque);
1391
void adb_kbd_init(ADBBusState *bus);
1392
void adb_mouse_init(ADBBusState *bus);
1393

    
1394
extern ADBBusState adb_bus;
1395

    
1396
#include "hw/usb.h"
1397

    
1398
/* usb ports of the VM */
1399

    
1400
void qemu_register_usb_port(USBPort *port, void *opaque, int index,
1401
                            usb_attachfn attach);
1402

    
1403
#define VM_USB_HUB_SIZE 8
1404

    
1405
void do_usb_add(const char *devname);
1406
void do_usb_del(const char *devname);
1407
void usb_info(void);
1408

    
1409
/* scsi-disk.c */
1410
enum scsi_reason {
1411
    SCSI_REASON_DONE, /* Command complete.  */
1412
    SCSI_REASON_DATA  /* Transfer complete, more data required.  */
1413
};
1414

    
1415
typedef struct SCSIDevice SCSIDevice;
1416
typedef void (*scsi_completionfn)(void *opaque, int reason, uint32_t tag,
1417
                                  uint32_t arg);
1418

    
1419
SCSIDevice *scsi_disk_init(BlockDriverState *bdrv,
1420
                           int tcq,
1421
                           scsi_completionfn completion,
1422
                           void *opaque);
1423
void scsi_disk_destroy(SCSIDevice *s);
1424

    
1425
int32_t scsi_send_command(SCSIDevice *s, uint32_t tag, uint8_t *buf, int lun);
1426
/* SCSI data transfers are asynchrnonous.  However, unlike the block IO
1427
   layer the completion routine may be called directly by
1428
   scsi_{read,write}_data.  */
1429
void scsi_read_data(SCSIDevice *s, uint32_t tag);
1430
int scsi_write_data(SCSIDevice *s, uint32_t tag);
1431
void scsi_cancel_io(SCSIDevice *s, uint32_t tag);
1432
uint8_t *scsi_get_buf(SCSIDevice *s, uint32_t tag);
1433

    
1434
/* lsi53c895a.c */
1435
void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1436
void *lsi_scsi_init(PCIBus *bus, int devfn);
1437

    
1438
/* integratorcp.c */
1439
extern QEMUMachine integratorcp_machine;
1440

    
1441
/* versatilepb.c */
1442
extern QEMUMachine versatilepb_machine;
1443
extern QEMUMachine versatileab_machine;
1444

    
1445
/* realview.c */
1446
extern QEMUMachine realview_machine;
1447

    
1448
/* spitz.c */
1449
extern QEMUMachine akitapda_machine;
1450
extern QEMUMachine spitzpda_machine;
1451
extern QEMUMachine borzoipda_machine;
1452
extern QEMUMachine terrierpda_machine;
1453

    
1454
/* palm.c */
1455
extern QEMUMachine palmte_machine;
1456

    
1457
/* ps2.c */
1458
void *ps2_kbd_init(void (*update_irq)(void *, int), void *update_arg);
1459
void *ps2_mouse_init(void (*update_irq)(void *, int), void *update_arg);
1460
void ps2_write_mouse(void *, int val);
1461
void ps2_write_keyboard(void *, int val);
1462
uint32_t ps2_read_data(void *);
1463
void ps2_queue(void *, int b);
1464
void ps2_keyboard_set_translation(void *opaque, int mode);
1465
void ps2_mouse_fake_event(void *opaque);
1466

    
1467
/* smc91c111.c */
1468
void smc91c111_init(NICInfo *, uint32_t, qemu_irq);
1469

    
1470
/* pl031.c */
1471
void pl031_init(uint32_t base, qemu_irq irq);
1472

    
1473
/* pl110.c */
1474
void *pl110_init(DisplayState *ds, uint32_t base, qemu_irq irq, int);
1475

    
1476
/* pl011.c */
1477
void pl011_init(uint32_t base, qemu_irq irq, CharDriverState *chr);
1478

    
1479
/* pl050.c */
1480
void pl050_init(uint32_t base, qemu_irq irq, int is_mouse);
1481

    
1482
/* pl080.c */
1483
void *pl080_init(uint32_t base, qemu_irq irq, int nchannels);
1484

    
1485
/* pl181.c */
1486
void pl181_init(uint32_t base, BlockDriverState *bd,
1487
                qemu_irq irq0, qemu_irq irq1);
1488

    
1489
/* pl190.c */
1490
qemu_irq *pl190_init(uint32_t base, qemu_irq irq, qemu_irq fiq);
1491

    
1492
/* arm-timer.c */
1493
void sp804_init(uint32_t base, qemu_irq irq);
1494
void icp_pit_init(uint32_t base, qemu_irq *pic, int irq);
1495

    
1496
/* arm_sysctl.c */
1497
void arm_sysctl_init(uint32_t base, uint32_t sys_id);
1498

    
1499
/* arm_gic.c */
1500
qemu_irq *arm_gic_init(uint32_t base, qemu_irq parent_irq);
1501

    
1502
/* arm_boot.c */
1503

    
1504
void arm_load_kernel(CPUState *env, int ram_size, const char *kernel_filename,
1505
                     const char *kernel_cmdline, const char *initrd_filename,
1506
                     int board_id, target_phys_addr_t loader_start);
1507

    
1508
/* sh7750.c */
1509
struct SH7750State;
1510

    
1511
struct SH7750State *sh7750_init(CPUState * cpu);
1512

    
1513
typedef struct {
1514
    /* The callback will be triggered if any of the designated lines change */
1515
    uint16_t portamask_trigger;
1516
    uint16_t portbmask_trigger;
1517
    /* Return 0 if no action was taken */
1518
    int (*port_change_cb) (uint16_t porta, uint16_t portb,
1519
                           uint16_t * periph_pdtra,
1520
                           uint16_t * periph_portdira,
1521
                           uint16_t * periph_pdtrb,
1522
                           uint16_t * periph_portdirb);
1523
} sh7750_io_device;
1524

    
1525
int sh7750_register_io_device(struct SH7750State *s,
1526
                              sh7750_io_device * device);
1527
/* sh_timer.c */
1528
#define TMU012_FEAT_TOCR   (1 << 0)
1529
#define TMU012_FEAT_3CHAN  (1 << 1)
1530
#define TMU012_FEAT_EXTCLK (1 << 2)
1531
void tmu012_init(uint32_t base, int feat, uint32_t freq);
1532

    
1533
/* sh_serial.c */
1534
#define SH_SERIAL_FEAT_SCIF (1 << 0)
1535
void sh_serial_init (target_phys_addr_t base, int feat,
1536
                     uint32_t freq, CharDriverState *chr);
1537

    
1538
/* tc58128.c */
1539
int tc58128_init(struct SH7750State *s, char *zone1, char *zone2);
1540

    
1541
/* NOR flash devices */
1542
#define MAX_PFLASH 4
1543
extern BlockDriverState *pflash_table[MAX_PFLASH];
1544
typedef struct pflash_t pflash_t;
1545

    
1546
pflash_t *pflash_register (target_phys_addr_t base, ram_addr_t off,
1547
                           BlockDriverState *bs,
1548
                           uint32_t sector_len, int nb_blocs, int width,
1549
                           uint16_t id0, uint16_t id1,
1550
                           uint16_t id2, uint16_t id3);
1551

    
1552
/* nand.c */
1553
struct nand_flash_s;
1554
struct nand_flash_s *nand_init(int manf_id, int chip_id);
1555
void nand_done(struct nand_flash_s *s);
1556
void nand_setpins(struct nand_flash_s *s,
1557
                int cle, int ale, int ce, int wp, int gnd);
1558
void nand_getpins(struct nand_flash_s *s, int *rb);
1559
void nand_setio(struct nand_flash_s *s, uint8_t value);
1560
uint8_t nand_getio(struct nand_flash_s *s);
1561

    
1562
#define NAND_MFR_TOSHIBA        0x98
1563
#define NAND_MFR_SAMSUNG        0xec
1564
#define NAND_MFR_FUJITSU        0x04
1565
#define NAND_MFR_NATIONAL        0x8f
1566
#define NAND_MFR_RENESAS        0x07
1567
#define NAND_MFR_STMICRO        0x20
1568
#define NAND_MFR_HYNIX                0xad
1569
#define NAND_MFR_MICRON                0x2c
1570

    
1571
/* ecc.c */
1572
struct ecc_state_s {
1573
    uint8_t cp;                /* Column parity */
1574
    uint16_t lp[2];        /* Line parity */
1575
    uint16_t count;
1576
};
1577

    
1578
uint8_t ecc_digest(struct ecc_state_s *s, uint8_t sample);
1579
void ecc_reset(struct ecc_state_s *s);
1580
void ecc_put(QEMUFile *f, struct ecc_state_s *s);
1581
void ecc_get(QEMUFile *f, struct ecc_state_s *s);
1582

    
1583
/* GPIO */
1584
typedef void (*gpio_handler_t)(int line, int level, void *opaque);
1585

    
1586
/* ads7846.c */
1587
struct ads7846_state_s;
1588
uint32_t ads7846_read(void *opaque);
1589
void ads7846_write(void *opaque, uint32_t value);
1590
struct ads7846_state_s *ads7846_init(qemu_irq penirq);
1591

    
1592
/* max111x.c */
1593
struct max111x_s;
1594
uint32_t max111x_read(void *opaque);
1595
void max111x_write(void *opaque, uint32_t value);
1596
struct max111x_s *max1110_init(qemu_irq cb);
1597
struct max111x_s *max1111_init(qemu_irq cb);
1598
void max111x_set_input(struct max111x_s *s, int line, uint8_t value);
1599

    
1600
/* PCMCIA/Cardbus */
1601

    
1602
struct pcmcia_socket_s {
1603
    qemu_irq irq;
1604
    int attached;
1605
    const char *slot_string;
1606
    const char *card_string;
1607
};
1608

    
1609
void pcmcia_socket_register(struct pcmcia_socket_s *socket);
1610
void pcmcia_socket_unregister(struct pcmcia_socket_s *socket);
1611
void pcmcia_info(void);
1612

    
1613
struct pcmcia_card_s {
1614
    void *state;
1615
    struct pcmcia_socket_s *slot;
1616
    int (*attach)(void *state);
1617
    int (*detach)(void *state);
1618
    const uint8_t *cis;
1619
    int cis_len;
1620

    
1621
    /* Only valid if attached */
1622
    uint8_t (*attr_read)(void *state, uint32_t address);
1623
    void (*attr_write)(void *state, uint32_t address, uint8_t value);
1624
    uint16_t (*common_read)(void *state, uint32_t address);
1625
    void (*common_write)(void *state, uint32_t address, uint16_t value);
1626
    uint16_t (*io_read)(void *state, uint32_t address);
1627
    void (*io_write)(void *state, uint32_t address, uint16_t value);
1628
};
1629

    
1630
#define CISTPL_DEVICE                0x01        /* 5V Device Information Tuple */
1631
#define CISTPL_NO_LINK                0x14        /* No Link Tuple */
1632
#define CISTPL_VERS_1                0x15        /* Level 1 Version Tuple */
1633
#define CISTPL_JEDEC_C                0x18        /* JEDEC ID Tuple */
1634
#define CISTPL_JEDEC_A                0x19        /* JEDEC ID Tuple */
1635
#define CISTPL_CONFIG                0x1a        /* Configuration Tuple */
1636
#define CISTPL_CFTABLE_ENTRY        0x1b        /* 16-bit PCCard Configuration */
1637
#define CISTPL_DEVICE_OC        0x1c        /* Additional Device Information */
1638
#define CISTPL_DEVICE_OA        0x1d        /* Additional Device Information */
1639
#define CISTPL_DEVICE_GEO        0x1e        /* Additional Device Information */
1640
#define CISTPL_DEVICE_GEO_A        0x1f        /* Additional Device Information */
1641
#define CISTPL_MANFID                0x20        /* Manufacture ID Tuple */
1642
#define CISTPL_FUNCID                0x21        /* Function ID Tuple */
1643
#define CISTPL_FUNCE                0x22        /* Function Extension Tuple */
1644
#define CISTPL_END                0xff        /* Tuple End */
1645
#define CISTPL_ENDMARK                0xff
1646

    
1647
/* dscm1xxxx.c */
1648
struct pcmcia_card_s *dscm1xxxx_init(BlockDriverState *bdrv);
1649

    
1650
/* ptimer.c */
1651
typedef struct ptimer_state ptimer_state;
1652
typedef void (*ptimer_cb)(void *opaque);
1653

    
1654
ptimer_state *ptimer_init(QEMUBH *bh);
1655
void ptimer_set_period(ptimer_state *s, int64_t period);
1656
void ptimer_set_freq(ptimer_state *s, uint32_t freq);
1657
void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload);
1658
uint64_t ptimer_get_count(ptimer_state *s);
1659
void ptimer_set_count(ptimer_state *s, uint64_t count);
1660
void ptimer_run(ptimer_state *s, int oneshot);
1661
void ptimer_stop(ptimer_state *s);
1662
void qemu_put_ptimer(QEMUFile *f, ptimer_state *s);
1663
void qemu_get_ptimer(QEMUFile *f, ptimer_state *s);
1664

    
1665
#include "hw/pxa.h"
1666

    
1667
#include "hw/omap.h"
1668

    
1669
/* tsc210x.c */
1670
struct uwire_slave_s *tsc2102_init(qemu_irq pint);
1671

    
1672
/* mcf_uart.c */
1673
uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr);
1674
void mcf_uart_write(void *opaque, target_phys_addr_t addr, uint32_t val);
1675
void *mcf_uart_init(qemu_irq irq, CharDriverState *chr);
1676
void mcf_uart_mm_init(target_phys_addr_t base, qemu_irq irq,
1677
                      CharDriverState *chr);
1678

    
1679
/* mcf_intc.c */
1680
qemu_irq *mcf_intc_init(target_phys_addr_t base, CPUState *env);
1681

    
1682
/* mcf_fec.c */
1683
void mcf_fec_init(NICInfo *nd, target_phys_addr_t base, qemu_irq *irq);
1684

    
1685
/* mcf5206.c */
1686
qemu_irq *mcf5206_init(uint32_t base, CPUState *env);
1687

    
1688
/* an5206.c */
1689
extern QEMUMachine an5206_machine;
1690

    
1691
/* mcf5208.c */
1692
extern QEMUMachine mcf5208evb_machine;
1693

    
1694
#include "gdbstub.h"
1695

    
1696
#endif /* defined(QEMU_TOOL) */
1697

    
1698
/* monitor.c */
1699
void monitor_init(CharDriverState *hd, int show_banner);
1700
void term_puts(const char *str);
1701
void term_vprintf(const char *fmt, va_list ap);
1702
void term_printf(const char *fmt, ...) __attribute__ ((__format__ (__printf__, 1, 2)));
1703
void term_print_filename(const char *filename);
1704
void term_flush(void);
1705
void term_print_help(void);
1706
void monitor_readline(const char *prompt, int is_password,
1707
                      char *buf, int buf_size);
1708

    
1709
/* readline.c */
1710
typedef void ReadLineFunc(void *opaque, const char *str);
1711

    
1712
extern int completion_index;
1713
void add_completion(const char *str);
1714
void readline_handle_byte(int ch);
1715
void readline_find_completion(const char *cmdline);
1716
const char *readline_get_history(unsigned int index);
1717
void readline_start(const char *prompt, int is_password,
1718
                    ReadLineFunc *readline_func, void *opaque);
1719

    
1720
void kqemu_record_dump(void);
1721

    
1722
#endif /* VL_H */