Revision 74475455 hw/acpi_piix4.c
| b/hw/acpi_piix4.c | ||
|---|---|---|
| 85 | 85 |
static uint32_t get_pmtmr(PIIX4PMState *s) |
| 86 | 86 |
{
|
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uint32_t d; |
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d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY, get_ticks_per_sec()); |
|
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d = muldiv64(qemu_get_clock_ns(vm_clock), PM_TIMER_FREQUENCY, get_ticks_per_sec());
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return d & 0xffffff; |
| 90 | 90 |
} |
| 91 | 91 |
|
| ... | ... | |
| 93 | 93 |
{
|
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int64_t d; |
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|
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d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY, |
|
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d = muldiv64(qemu_get_clock_ns(vm_clock), PM_TIMER_FREQUENCY,
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|
| 97 | 97 |
get_ticks_per_sec()); |
| 98 | 98 |
if (d >= s->tmr_overflow_time) |
| 99 | 99 |
s->pmsts |= ACPI_BITMASK_TIMER_STATUS; |
| ... | ... | |
| 149 | 149 |
pmsts = get_pmsts(s); |
| 150 | 150 |
if (pmsts & val & ACPI_BITMASK_TIMER_STATUS) {
|
| 151 | 151 |
/* if TMRSTS is reset, then compute the new overflow time */ |
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d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY, |
|
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d = muldiv64(qemu_get_clock_ns(vm_clock), PM_TIMER_FREQUENCY,
|
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| 153 | 153 |
get_ticks_per_sec()); |
| 154 | 154 |
s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL; |
| 155 | 155 |
} |
| ... | ... | |
| 413 | 413 |
register_ioport_write(s->smb_io_base, 64, 1, smb_ioport_writeb, &s->smb); |
| 414 | 414 |
register_ioport_read(s->smb_io_base, 64, 1, smb_ioport_readb, &s->smb); |
| 415 | 415 |
|
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s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s); |
|
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s->tmr_timer = qemu_new_timer_ns(vm_clock, pm_tmr_timer, s);
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| 417 | 417 |
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| 418 | 418 |
qemu_system_powerdown = *qemu_allocate_irqs(piix4_powerdown, s, 1); |
| 419 | 419 |
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