Revision 74475455 hw/cuda.c
| b/hw/cuda.c | ||
|---|---|---|
| 170 | 170 |
int64_t d; |
| 171 | 171 |
unsigned int counter; |
| 172 | 172 |
|
| 173 |
d = muldiv64(qemu_get_clock(vm_clock) - s->load_time, |
|
| 173 |
d = muldiv64(qemu_get_clock_ns(vm_clock) - s->load_time,
|
|
| 174 | 174 |
CUDA_TIMER_FREQ, get_ticks_per_sec()); |
| 175 | 175 |
if (s->index == 0) {
|
| 176 | 176 |
/* the timer goes down from latch to -1 (period of latch + 2) */ |
| ... | ... | |
| 189 | 189 |
static void set_counter(CUDAState *s, CUDATimer *ti, unsigned int val) |
| 190 | 190 |
{
|
| 191 | 191 |
CUDA_DPRINTF("T%d.counter=%d\n", 1 + (ti->timer == NULL), val);
|
| 192 |
ti->load_time = qemu_get_clock(vm_clock); |
|
| 192 |
ti->load_time = qemu_get_clock_ns(vm_clock);
|
|
| 193 | 193 |
ti->counter_value = val; |
| 194 | 194 |
cuda_timer_update(s, ti, ti->load_time); |
| 195 | 195 |
} |
| ... | ... | |
| 346 | 346 |
break; |
| 347 | 347 |
case 4: |
| 348 | 348 |
s->timers[0].latch = (s->timers[0].latch & 0xff00) | val; |
| 349 |
cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock)); |
|
| 349 |
cuda_timer_update(s, &s->timers[0], qemu_get_clock_ns(vm_clock));
|
|
| 350 | 350 |
break; |
| 351 | 351 |
case 5: |
| 352 | 352 |
s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8); |
| ... | ... | |
| 355 | 355 |
break; |
| 356 | 356 |
case 6: |
| 357 | 357 |
s->timers[0].latch = (s->timers[0].latch & 0xff00) | val; |
| 358 |
cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock)); |
|
| 358 |
cuda_timer_update(s, &s->timers[0], qemu_get_clock_ns(vm_clock));
|
|
| 359 | 359 |
break; |
| 360 | 360 |
case 7: |
| 361 | 361 |
s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8); |
| 362 | 362 |
s->ifr &= ~T1_INT; |
| 363 |
cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock)); |
|
| 363 |
cuda_timer_update(s, &s->timers[0], qemu_get_clock_ns(vm_clock));
|
|
| 364 | 364 |
break; |
| 365 | 365 |
case 8: |
| 366 | 366 |
s->timers[1].latch = val; |
| ... | ... | |
| 374 | 374 |
break; |
| 375 | 375 |
case 11: |
| 376 | 376 |
s->acr = val; |
| 377 |
cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock)); |
|
| 377 |
cuda_timer_update(s, &s->timers[0], qemu_get_clock_ns(vm_clock));
|
|
| 378 | 378 |
cuda_update(s); |
| 379 | 379 |
break; |
| 380 | 380 |
case 12: |
| ... | ... | |
| 506 | 506 |
cuda_send_packet_to_host(s, obuf, olen + 2); |
| 507 | 507 |
} |
| 508 | 508 |
qemu_mod_timer(s->adb_poll_timer, |
| 509 |
qemu_get_clock(vm_clock) + |
|
| 509 |
qemu_get_clock_ns(vm_clock) +
|
|
| 510 | 510 |
(get_ticks_per_sec() / CUDA_ADB_POLL_FREQ)); |
| 511 | 511 |
} |
| 512 | 512 |
|
| ... | ... | |
| 524 | 524 |
s->autopoll = autopoll; |
| 525 | 525 |
if (autopoll) {
|
| 526 | 526 |
qemu_mod_timer(s->adb_poll_timer, |
| 527 |
qemu_get_clock(vm_clock) + |
|
| 527 |
qemu_get_clock_ns(vm_clock) +
|
|
| 528 | 528 |
(get_ticks_per_sec() / CUDA_ADB_POLL_FREQ)); |
| 529 | 529 |
} else {
|
| 530 | 530 |
qemu_del_timer(s->adb_poll_timer); |
| ... | ... | |
| 536 | 536 |
break; |
| 537 | 537 |
case CUDA_SET_TIME: |
| 538 | 538 |
ti = (((uint32_t)data[1]) << 24) + (((uint32_t)data[2]) << 16) + (((uint32_t)data[3]) << 8) + data[4]; |
| 539 |
s->tick_offset = ti - (qemu_get_clock(vm_clock) / get_ticks_per_sec()); |
|
| 539 |
s->tick_offset = ti - (qemu_get_clock_ns(vm_clock) / get_ticks_per_sec());
|
|
| 540 | 540 |
obuf[0] = CUDA_PACKET; |
| 541 | 541 |
obuf[1] = 0; |
| 542 | 542 |
obuf[2] = 0; |
| 543 | 543 |
cuda_send_packet_to_host(s, obuf, 3); |
| 544 | 544 |
break; |
| 545 | 545 |
case CUDA_GET_TIME: |
| 546 |
ti = s->tick_offset + (qemu_get_clock(vm_clock) / get_ticks_per_sec()); |
|
| 546 |
ti = s->tick_offset + (qemu_get_clock_ns(vm_clock) / get_ticks_per_sec());
|
|
| 547 | 547 |
obuf[0] = CUDA_PACKET; |
| 548 | 548 |
obuf[1] = 0; |
| 549 | 549 |
obuf[2] = 0; |
| ... | ... | |
| 754 | 754 |
s->irq = irq; |
| 755 | 755 |
|
| 756 | 756 |
s->timers[0].index = 0; |
| 757 |
s->timers[0].timer = qemu_new_timer(vm_clock, cuda_timer1, s); |
|
| 757 |
s->timers[0].timer = qemu_new_timer_ns(vm_clock, cuda_timer1, s);
|
|
| 758 | 758 |
|
| 759 | 759 |
s->timers[1].index = 1; |
| 760 | 760 |
|
| 761 | 761 |
qemu_get_timedate(&tm, 0); |
| 762 | 762 |
s->tick_offset = (uint32_t)mktimegm(&tm) + RTC_OFFSET; |
| 763 | 763 |
|
| 764 |
s->adb_poll_timer = qemu_new_timer(vm_clock, cuda_adb_poll, s); |
|
| 764 |
s->adb_poll_timer = qemu_new_timer_ns(vm_clock, cuda_adb_poll, s);
|
|
| 765 | 765 |
*cuda_mem_index = cpu_register_io_memory(cuda_read, cuda_write, s, |
| 766 | 766 |
DEVICE_NATIVE_ENDIAN); |
| 767 | 767 |
register_savevm(NULL, "cuda", -1, 1, cuda_save, cuda_load, s); |
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