Revision 74475455 hw/i8254.c

b/hw/i8254.c
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    uint64_t d;
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    int counter;
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    d = muldiv64(qemu_get_clock(vm_clock) - s->count_load_time, PIT_FREQ,
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    d = muldiv64(qemu_get_clock_ns(vm_clock) - s->count_load_time, PIT_FREQ,
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                 get_ticks_per_sec());
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    switch(s->mode) {
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    case 0:
......
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    case 5:
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        if (s->gate < val) {
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            /* restart counting on rising edge */
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            s->count_load_time = qemu_get_clock(vm_clock);
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            s->count_load_time = qemu_get_clock_ns(vm_clock);
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            pit_irq_timer_update(s, s->count_load_time);
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        }
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        break;
......
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    case 3:
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        if (s->gate < val) {
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            /* restart counting on rising edge */
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            s->count_load_time = qemu_get_clock(vm_clock);
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            s->count_load_time = qemu_get_clock_ns(vm_clock);
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            pit_irq_timer_update(s, s->count_load_time);
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        }
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        /* XXX: disable/enable counting */
......
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{
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    if (val == 0)
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        val = 0x10000;
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    s->count_load_time = qemu_get_clock(vm_clock);
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    s->count_load_time = qemu_get_clock_ns(vm_clock);
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    s->count = val;
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    pit_irq_timer_update(s, s->count_load_time);
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}
......
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                    if (!(val & 0x10) && !s->status_latched) {
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                        /* status latch */
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                        /* XXX: add BCD and null count */
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                        s->status =  (pit_get_out1(s, qemu_get_clock(vm_clock)) << 7) |
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                        s->status =  (pit_get_out1(s, qemu_get_clock_ns(vm_clock)) << 7) |
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                            (s->rw_mode << 4) |
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                            (s->mode << 1) |
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                            s->bcd;
......
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    s = &pit->channels[0];
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    /* the timer 0 is connected to an IRQ */
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    s->irq_timer = qemu_new_timer(vm_clock, pit_irq_timer, s);
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    s->irq_timer = qemu_new_timer_ns(vm_clock, pit_irq_timer, s);
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    s->irq = isa_get_irq(pit->irq);
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    register_ioport_write(pit->iobase, 4, 1, pit_ioport_write, pit);

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