Revision 74475455 hw/mc146818rtc.c
| b/hw/mc146818rtc.c | ||
|---|---|---|
| 112 | 112 |
} else {
|
| 113 | 113 |
/* divide each RTC interval to 2 - 8 smaller intervals */ |
| 114 | 114 |
int c = MIN(s->irq_coalesced, 7) + 1; |
| 115 |
int64_t next_clock = qemu_get_clock(rtc_clock) + |
|
| 115 |
int64_t next_clock = qemu_get_clock_ns(rtc_clock) +
|
|
| 116 | 116 |
muldiv64(s->period / c, get_ticks_per_sec(), 32768); |
| 117 | 117 |
qemu_mod_timer(s->coalesced_timer, next_clock); |
| 118 | 118 |
} |
| ... | ... | |
| 234 | 234 |
/* UIP bit is read only */ |
| 235 | 235 |
s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) | |
| 236 | 236 |
(s->cmos_data[RTC_REG_A] & REG_A_UIP); |
| 237 |
rtc_timer_update(s, qemu_get_clock(rtc_clock)); |
|
| 237 |
rtc_timer_update(s, qemu_get_clock_ns(rtc_clock));
|
|
| 238 | 238 |
break; |
| 239 | 239 |
case RTC_REG_B: |
| 240 | 240 |
if (data & REG_B_SET) {
|
| ... | ... | |
| 256 | 256 |
} else {
|
| 257 | 257 |
s->cmos_data[RTC_REG_B] = data; |
| 258 | 258 |
} |
| 259 |
rtc_timer_update(s, qemu_get_clock(rtc_clock)); |
|
| 259 |
rtc_timer_update(s, qemu_get_clock_ns(rtc_clock));
|
|
| 260 | 260 |
break; |
| 261 | 261 |
case RTC_REG_C: |
| 262 | 262 |
case RTC_REG_D: |
| ... | ... | |
| 599 | 599 |
|
| 600 | 600 |
rtc_set_date_from_host(dev); |
| 601 | 601 |
|
| 602 |
s->periodic_timer = qemu_new_timer(rtc_clock, rtc_periodic_timer, s); |
|
| 602 |
s->periodic_timer = qemu_new_timer_ns(rtc_clock, rtc_periodic_timer, s);
|
|
| 603 | 603 |
#ifdef TARGET_I386 |
| 604 | 604 |
if (rtc_td_hack) |
| 605 | 605 |
s->coalesced_timer = |
| 606 |
qemu_new_timer(rtc_clock, rtc_coalesced_timer, s); |
|
| 606 |
qemu_new_timer_ns(rtc_clock, rtc_coalesced_timer, s);
|
|
| 607 | 607 |
#endif |
| 608 |
s->second_timer = qemu_new_timer(rtc_clock, rtc_update_second, s); |
|
| 609 |
s->second_timer2 = qemu_new_timer(rtc_clock, rtc_update_second2, s); |
|
| 608 |
s->second_timer = qemu_new_timer_ns(rtc_clock, rtc_update_second, s);
|
|
| 609 |
s->second_timer2 = qemu_new_timer_ns(rtc_clock, rtc_update_second2, s);
|
|
| 610 | 610 |
|
| 611 | 611 |
s->next_second_time = |
| 612 |
qemu_get_clock(rtc_clock) + (get_ticks_per_sec() * 99) / 100; |
|
| 612 |
qemu_get_clock_ns(rtc_clock) + (get_ticks_per_sec() * 99) / 100;
|
|
| 613 | 613 |
qemu_mod_timer(s->second_timer2, s->next_second_time); |
| 614 | 614 |
|
| 615 | 615 |
register_ioport_write(base, 2, 1, cmos_ioport_write, s); |
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