Revision 74475455 hw/mips_timer.c
| b/hw/mips_timer.c | ||
|---|---|---|
| 47 | 47 |
uint64_t now, next; |
| 48 | 48 |
uint32_t wait; |
| 49 | 49 |
|
| 50 |
now = qemu_get_clock(vm_clock); |
|
| 50 |
now = qemu_get_clock_ns(vm_clock);
|
|
| 51 | 51 |
wait = env->CP0_Compare - env->CP0_Count - |
| 52 | 52 |
(uint32_t)muldiv64(now, TIMER_FREQ, get_ticks_per_sec()); |
| 53 | 53 |
next = now + muldiv64(wait, get_ticks_per_sec(), TIMER_FREQ); |
| ... | ... | |
| 71 | 71 |
} else {
|
| 72 | 72 |
uint64_t now; |
| 73 | 73 |
|
| 74 |
now = qemu_get_clock(vm_clock); |
|
| 74 |
now = qemu_get_clock_ns(vm_clock);
|
|
| 75 | 75 |
if (qemu_timer_pending(env->timer) |
| 76 | 76 |
&& qemu_timer_expired(env->timer, now)) {
|
| 77 | 77 |
/* The timer has already expired. */ |
| ... | ... | |
| 90 | 90 |
else {
|
| 91 | 91 |
/* Store new count register */ |
| 92 | 92 |
env->CP0_Count = |
| 93 |
count - (uint32_t)muldiv64(qemu_get_clock(vm_clock), |
|
| 93 |
count - (uint32_t)muldiv64(qemu_get_clock_ns(vm_clock),
|
|
| 94 | 94 |
TIMER_FREQ, get_ticks_per_sec()); |
| 95 | 95 |
/* Update timer timer */ |
| 96 | 96 |
cpu_mips_timer_update(env); |
| ... | ... | |
| 115 | 115 |
void cpu_mips_stop_count(CPUState *env) |
| 116 | 116 |
{
|
| 117 | 117 |
/* Store the current value */ |
| 118 |
env->CP0_Count += (uint32_t)muldiv64(qemu_get_clock(vm_clock), |
|
| 118 |
env->CP0_Count += (uint32_t)muldiv64(qemu_get_clock_ns(vm_clock),
|
|
| 119 | 119 |
TIMER_FREQ, get_ticks_per_sec()); |
| 120 | 120 |
} |
| 121 | 121 |
|
| ... | ... | |
| 141 | 141 |
|
| 142 | 142 |
void cpu_mips_clock_init (CPUState *env) |
| 143 | 143 |
{
|
| 144 |
env->timer = qemu_new_timer(vm_clock, &mips_timer_cb, env); |
|
| 144 |
env->timer = qemu_new_timer_ns(vm_clock, &mips_timer_cb, env);
|
|
| 145 | 145 |
env->CP0_Compare = 0; |
| 146 | 146 |
cpu_mips_store_count(env, 1); |
| 147 | 147 |
} |
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