Revision 74475455 hw/omap1.c
| b/hw/omap1.c | ||
|---|---|---|
| 101 | 101 |
|
| 102 | 102 |
static inline uint32_t omap_timer_read(struct omap_mpu_timer_s *timer) |
| 103 | 103 |
{
|
| 104 |
uint64_t distance = qemu_get_clock(vm_clock) - timer->time; |
|
| 104 |
uint64_t distance = qemu_get_clock_ns(vm_clock) - timer->time;
|
|
| 105 | 105 |
|
| 106 | 106 |
if (timer->st && timer->enable && timer->rate) |
| 107 | 107 |
return timer->val - muldiv64(distance >> (timer->ptv + 1), |
| ... | ... | |
| 113 | 113 |
static inline void omap_timer_sync(struct omap_mpu_timer_s *timer) |
| 114 | 114 |
{
|
| 115 | 115 |
timer->val = omap_timer_read(timer); |
| 116 |
timer->time = qemu_get_clock(vm_clock); |
|
| 116 |
timer->time = qemu_get_clock_ns(vm_clock);
|
|
| 117 | 117 |
} |
| 118 | 118 |
|
| 119 | 119 |
static inline void omap_timer_update(struct omap_mpu_timer_s *timer) |
| ... | ... | |
| 258 | 258 |
|
| 259 | 259 |
s->irq = irq; |
| 260 | 260 |
s->clk = clk; |
| 261 |
s->timer = qemu_new_timer(vm_clock, omap_timer_tick, s); |
|
| 261 |
s->timer = qemu_new_timer_ns(vm_clock, omap_timer_tick, s);
|
|
| 262 | 262 |
s->tick = qemu_bh_new(omap_timer_fire, s); |
| 263 | 263 |
omap_mpu_timer_reset(s); |
| 264 | 264 |
omap_timer_clk_setup(s); |
| ... | ... | |
| 382 | 382 |
|
| 383 | 383 |
s->timer.irq = irq; |
| 384 | 384 |
s->timer.clk = clk; |
| 385 |
s->timer.timer = qemu_new_timer(vm_clock, omap_timer_tick, &s->timer); |
|
| 385 |
s->timer.timer = qemu_new_timer_ns(vm_clock, omap_timer_tick, &s->timer);
|
|
| 386 | 386 |
omap_wd_timer_reset(s); |
| 387 | 387 |
omap_timer_clk_setup(&s->timer); |
| 388 | 388 |
|
| ... | ... | |
| 484 | 484 |
|
| 485 | 485 |
s->timer.irq = irq; |
| 486 | 486 |
s->timer.clk = clk; |
| 487 |
s->timer.timer = qemu_new_timer(vm_clock, omap_timer_tick, &s->timer); |
|
| 487 |
s->timer.timer = qemu_new_timer_ns(vm_clock, omap_timer_tick, &s->timer);
|
|
| 488 | 488 |
omap_os_timer_reset(s); |
| 489 | 489 |
omap_timer_clk_setup(&s->timer); |
| 490 | 490 |
|
| ... | ... | |
| 580 | 580 |
case 0x10: /* GAUGING_CTRL */ |
| 581 | 581 |
/* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */ |
| 582 | 582 |
if ((s->ulpd_pm_regs[addr >> 2] ^ value) & 1) {
|
| 583 |
now = qemu_get_clock(vm_clock); |
|
| 583 |
now = qemu_get_clock_ns(vm_clock);
|
|
| 584 | 584 |
|
| 585 | 585 |
if (value & 1) |
| 586 | 586 |
s->ulpd_gauge_start = now; |
| ... | ... | |
| 2915 | 2915 |
s->rx_req = s->rx_rate << bps[(s->rcr[0] >> 5) & 7]; |
| 2916 | 2916 |
|
| 2917 | 2917 |
omap_mcbsp_rx_newdata(s); |
| 2918 |
qemu_mod_timer(s->source_timer, qemu_get_clock(vm_clock) + |
|
| 2918 |
qemu_mod_timer(s->source_timer, qemu_get_clock_ns(vm_clock) +
|
|
| 2919 | 2919 |
get_ticks_per_sec()); |
| 2920 | 2920 |
} |
| 2921 | 2921 |
|
| ... | ... | |
| 2961 | 2961 |
s->tx_req = s->tx_rate << bps[(s->xcr[0] >> 5) & 7]; |
| 2962 | 2962 |
|
| 2963 | 2963 |
omap_mcbsp_tx_newdata(s); |
| 2964 |
qemu_mod_timer(s->sink_timer, qemu_get_clock(vm_clock) + |
|
| 2964 |
qemu_mod_timer(s->sink_timer, qemu_get_clock_ns(vm_clock) +
|
|
| 2965 | 2965 |
get_ticks_per_sec()); |
| 2966 | 2966 |
} |
| 2967 | 2967 |
|
| ... | ... | |
| 3344 | 3344 |
s->rxirq = irq[1]; |
| 3345 | 3345 |
s->txdrq = dma[0]; |
| 3346 | 3346 |
s->rxdrq = dma[1]; |
| 3347 |
s->sink_timer = qemu_new_timer(vm_clock, omap_mcbsp_sink_tick, s); |
|
| 3348 |
s->source_timer = qemu_new_timer(vm_clock, omap_mcbsp_source_tick, s); |
|
| 3347 |
s->sink_timer = qemu_new_timer_ns(vm_clock, omap_mcbsp_sink_tick, s);
|
|
| 3348 |
s->source_timer = qemu_new_timer_ns(vm_clock, omap_mcbsp_source_tick, s);
|
|
| 3349 | 3349 |
omap_mcbsp_reset(s); |
| 3350 | 3350 |
|
| 3351 | 3351 |
iomemtype = cpu_register_io_memory(omap_mcbsp_readfn, |
Also available in: Unified diff