Revision 74475455 hw/pxa2xx_timer.c
| b/hw/pxa2xx_timer.c | ||
|---|---|---|
| 171 | 171 |
goto badreg; |
| 172 | 172 |
return s->tm4[tm].tm.value; |
| 173 | 173 |
case OSCR: |
| 174 |
return s->clock + muldiv64(qemu_get_clock(vm_clock) - |
|
| 174 |
return s->clock + muldiv64(qemu_get_clock_ns(vm_clock) -
|
|
| 175 | 175 |
s->lastload, s->freq, get_ticks_per_sec()); |
| 176 | 176 |
case OSCR11: tm ++; |
| 177 | 177 |
case OSCR10: tm ++; |
| ... | ... | |
| 187 | 187 |
if ((tm == 9 - 4 || tm == 11 - 4) && (s->tm4[tm].control & (1 << 9))) {
|
| 188 | 188 |
if (s->tm4[tm - 1].freq) |
| 189 | 189 |
s->snapshot = s->tm4[tm - 1].clock + muldiv64( |
| 190 |
qemu_get_clock(vm_clock) - |
|
| 190 |
qemu_get_clock_ns(vm_clock) -
|
|
| 191 | 191 |
s->tm4[tm - 1].lastload, |
| 192 | 192 |
s->tm4[tm - 1].freq, get_ticks_per_sec()); |
| 193 | 193 |
else |
| ... | ... | |
| 196 | 196 |
|
| 197 | 197 |
if (!s->tm4[tm].freq) |
| 198 | 198 |
return s->tm4[tm].clock; |
| 199 |
return s->tm4[tm].clock + muldiv64(qemu_get_clock(vm_clock) - |
|
| 199 |
return s->tm4[tm].clock + muldiv64(qemu_get_clock_ns(vm_clock) -
|
|
| 200 | 200 |
s->tm4[tm].lastload, s->tm4[tm].freq, get_ticks_per_sec()); |
| 201 | 201 |
case OIER: |
| 202 | 202 |
return s->irq_enabled; |
| ... | ... | |
| 237 | 237 |
case OSMR1: tm ++; |
| 238 | 238 |
case OSMR0: |
| 239 | 239 |
s->timer[tm].value = value; |
| 240 |
pxa2xx_timer_update(s, qemu_get_clock(vm_clock)); |
|
| 240 |
pxa2xx_timer_update(s, qemu_get_clock_ns(vm_clock));
|
|
| 241 | 241 |
break; |
| 242 | 242 |
case OSMR11: tm ++; |
| 243 | 243 |
case OSMR10: tm ++; |
| ... | ... | |
| 250 | 250 |
if (!pxa2xx_timer_has_tm4(s)) |
| 251 | 251 |
goto badreg; |
| 252 | 252 |
s->tm4[tm].tm.value = value; |
| 253 |
pxa2xx_timer_update4(s, qemu_get_clock(vm_clock), tm); |
|
| 253 |
pxa2xx_timer_update4(s, qemu_get_clock_ns(vm_clock), tm);
|
|
| 254 | 254 |
break; |
| 255 | 255 |
case OSCR: |
| 256 | 256 |
s->oldclock = s->clock; |
| 257 |
s->lastload = qemu_get_clock(vm_clock); |
|
| 257 |
s->lastload = qemu_get_clock_ns(vm_clock);
|
|
| 258 | 258 |
s->clock = value; |
| 259 | 259 |
pxa2xx_timer_update(s, s->lastload); |
| 260 | 260 |
break; |
| ... | ... | |
| 269 | 269 |
if (!pxa2xx_timer_has_tm4(s)) |
| 270 | 270 |
goto badreg; |
| 271 | 271 |
s->tm4[tm].oldclock = s->tm4[tm].clock; |
| 272 |
s->tm4[tm].lastload = qemu_get_clock(vm_clock); |
|
| 272 |
s->tm4[tm].lastload = qemu_get_clock_ns(vm_clock);
|
|
| 273 | 273 |
s->tm4[tm].clock = value; |
| 274 | 274 |
pxa2xx_timer_update4(s, s->tm4[tm].lastload, tm); |
| 275 | 275 |
break; |
| ... | ... | |
| 300 | 300 |
s->tm4[tm].freq = pxa2xx_timer4_freq[value & 7]; |
| 301 | 301 |
else {
|
| 302 | 302 |
s->tm4[tm].freq = 0; |
| 303 |
pxa2xx_timer_update4(s, qemu_get_clock(vm_clock), tm); |
|
| 303 |
pxa2xx_timer_update4(s, qemu_get_clock_ns(vm_clock), tm);
|
|
| 304 | 304 |
} |
| 305 | 305 |
break; |
| 306 | 306 |
case OMCR11: tm ++; |
| ... | ... | |
| 316 | 316 |
pxa2xx_timer4_freq[(value & (1 << 8)) ? 0 : (value & 7)]; |
| 317 | 317 |
else {
|
| 318 | 318 |
s->tm4[tm].freq = 0; |
| 319 |
pxa2xx_timer_update4(s, qemu_get_clock(vm_clock), tm); |
|
| 319 |
pxa2xx_timer_update4(s, qemu_get_clock_ns(vm_clock), tm);
|
|
| 320 | 320 |
} |
| 321 | 321 |
break; |
| 322 | 322 |
default: |
| ... | ... | |
| 363 | 363 |
if (t->control & (1 << 3)) |
| 364 | 364 |
t->clock = 0; |
| 365 | 365 |
if (t->control & (1 << 6)) |
| 366 |
pxa2xx_timer_update4(i, qemu_get_clock(vm_clock), t->tm.num - 4); |
|
| 366 |
pxa2xx_timer_update4(i, qemu_get_clock_ns(vm_clock), t->tm.num - 4);
|
|
| 367 | 367 |
if (i->events & 0xff0) |
| 368 | 368 |
qemu_irq_raise(i->irq4); |
| 369 | 369 |
} |
| ... | ... | |
| 374 | 374 |
int64_t now; |
| 375 | 375 |
int i; |
| 376 | 376 |
|
| 377 |
now = qemu_get_clock(vm_clock); |
|
| 377 |
now = qemu_get_clock_ns(vm_clock);
|
|
| 378 | 378 |
pxa2xx_timer_update(s, now); |
| 379 | 379 |
|
| 380 | 380 |
if (pxa2xx_timer_has_tm4(s)) |
| ... | ... | |
| 394 | 394 |
s->irq_enabled = 0; |
| 395 | 395 |
s->oldclock = 0; |
| 396 | 396 |
s->clock = 0; |
| 397 |
s->lastload = qemu_get_clock(vm_clock); |
|
| 397 |
s->lastload = qemu_get_clock_ns(vm_clock);
|
|
| 398 | 398 |
s->reset3 = 0; |
| 399 | 399 |
|
| 400 | 400 |
for (i = 0; i < 4; i ++) {
|
| ... | ... | |
| 402 | 402 |
sysbus_init_irq(dev, &s->timer[i].irq); |
| 403 | 403 |
s->timer[i].info = s; |
| 404 | 404 |
s->timer[i].num = i; |
| 405 |
s->timer[i].qtimer = qemu_new_timer(vm_clock, |
|
| 405 |
s->timer[i].qtimer = qemu_new_timer_ns(vm_clock,
|
|
| 406 | 406 |
pxa2xx_timer_tick, &s->timer[i]); |
| 407 | 407 |
} |
| 408 | 408 |
if (s->flags & (1 << PXA2XX_TIMER_HAVE_TM4)) {
|
| ... | ... | |
| 414 | 414 |
s->tm4[i].tm.num = i + 4; |
| 415 | 415 |
s->tm4[i].freq = 0; |
| 416 | 416 |
s->tm4[i].control = 0x0; |
| 417 |
s->tm4[i].tm.qtimer = qemu_new_timer(vm_clock, |
|
| 417 |
s->tm4[i].tm.qtimer = qemu_new_timer_ns(vm_clock,
|
|
| 418 | 418 |
pxa2xx_timer_tick4, &s->tm4[i]); |
| 419 | 419 |
} |
| 420 | 420 |
} |
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