Revision 74475455 hw/rtl8139.c
| b/hw/rtl8139.c | ||
|---|---|---|
| 2517 | 2517 |
|
| 2518 | 2518 |
s->IntrMask = val; |
| 2519 | 2519 |
|
| 2520 |
rtl8139_set_next_tctr_time(s, qemu_get_clock(vm_clock)); |
|
| 2520 |
rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
|
|
| 2521 | 2521 |
rtl8139_update_irq(s); |
| 2522 | 2522 |
|
| 2523 | 2523 |
} |
| ... | ... | |
| 2558 | 2558 |
* and probably emulated is slower is better to assume this resetting was |
| 2559 | 2559 |
* done before testing on previous rtl8139_update_irq lead to IRQ loosing |
| 2560 | 2560 |
*/ |
| 2561 |
rtl8139_set_next_tctr_time(s, qemu_get_clock(vm_clock)); |
|
| 2561 |
rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
|
|
| 2562 | 2562 |
rtl8139_update_irq(s); |
| 2563 | 2563 |
|
| 2564 | 2564 |
#endif |
| ... | ... | |
| 2566 | 2566 |
|
| 2567 | 2567 |
static uint32_t rtl8139_IntrStatus_read(RTL8139State *s) |
| 2568 | 2568 |
{
|
| 2569 |
rtl8139_set_next_tctr_time(s, qemu_get_clock(vm_clock)); |
|
| 2569 |
rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
|
|
| 2570 | 2570 |
|
| 2571 | 2571 |
uint32_t ret = s->IntrStatus; |
| 2572 | 2572 |
|
| ... | ... | |
| 2831 | 2831 |
|
| 2832 | 2832 |
case Timer: |
| 2833 | 2833 |
DEBUG_PRINT(("RTL8139: TCTR Timer reset on write\n"));
|
| 2834 |
s->TCTR_base = qemu_get_clock(vm_clock); |
|
| 2834 |
s->TCTR_base = qemu_get_clock_ns(vm_clock);
|
|
| 2835 | 2835 |
rtl8139_set_next_tctr_time(s, s->TCTR_base); |
| 2836 | 2836 |
break; |
| 2837 | 2837 |
|
| ... | ... | |
| 2839 | 2839 |
DEBUG_PRINT(("RTL8139: FlashReg TimerInt write val=0x%08x\n", val));
|
| 2840 | 2840 |
if (s->TimerInt != val) {
|
| 2841 | 2841 |
s->TimerInt = val; |
| 2842 |
rtl8139_set_next_tctr_time(s, qemu_get_clock(vm_clock)); |
|
| 2842 |
rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
|
|
| 2843 | 2843 |
} |
| 2844 | 2844 |
break; |
| 2845 | 2845 |
|
| ... | ... | |
| 3050 | 3050 |
break; |
| 3051 | 3051 |
|
| 3052 | 3052 |
case Timer: |
| 3053 |
ret = muldiv64(qemu_get_clock(vm_clock) - s->TCTR_base, |
|
| 3053 |
ret = muldiv64(qemu_get_clock_ns(vm_clock) - s->TCTR_base,
|
|
| 3054 | 3054 |
PCI_FREQUENCY, get_ticks_per_sec()); |
| 3055 | 3055 |
DEBUG_PRINT(("RTL8139: TCTR Timer read val=0x%08x\n", ret));
|
| 3056 | 3056 |
break; |
| ... | ... | |
| 3144 | 3144 |
static int rtl8139_post_load(void *opaque, int version_id) |
| 3145 | 3145 |
{
|
| 3146 | 3146 |
RTL8139State* s = opaque; |
| 3147 |
rtl8139_set_next_tctr_time(s, qemu_get_clock(vm_clock)); |
|
| 3147 |
rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
|
|
| 3148 | 3148 |
if (version_id < 4) {
|
| 3149 | 3149 |
s->cplus_enabled = s->CpCmd != 0; |
| 3150 | 3150 |
} |
| ... | ... | |
| 3170 | 3170 |
static void rtl8139_pre_save(void *opaque) |
| 3171 | 3171 |
{
|
| 3172 | 3172 |
RTL8139State* s = opaque; |
| 3173 |
int64_t current_time = qemu_get_clock(vm_clock); |
|
| 3173 |
int64_t current_time = qemu_get_clock_ns(vm_clock);
|
|
| 3174 | 3174 |
|
| 3175 | 3175 |
/* set IntrStatus correctly */ |
| 3176 | 3176 |
rtl8139_set_next_tctr_time(s, current_time); |
| ... | ... | |
| 3319 | 3319 |
|
| 3320 | 3320 |
s->IntrStatus |= PCSTimeout; |
| 3321 | 3321 |
rtl8139_update_irq(s); |
| 3322 |
rtl8139_set_next_tctr_time(s, qemu_get_clock(vm_clock)); |
|
| 3322 |
rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
|
|
| 3323 | 3323 |
} |
| 3324 | 3324 |
|
| 3325 | 3325 |
static void rtl8139_cleanup(VLANClientState *nc) |
| ... | ... | |
| 3400 | 3400 |
s->cplus_txbuffer_offset = 0; |
| 3401 | 3401 |
|
| 3402 | 3402 |
s->TimerExpire = 0; |
| 3403 |
s->timer = qemu_new_timer(vm_clock, rtl8139_timer, s); |
|
| 3404 |
rtl8139_set_next_tctr_time(s, qemu_get_clock(vm_clock)); |
|
| 3403 |
s->timer = qemu_new_timer_ns(vm_clock, rtl8139_timer, s);
|
|
| 3404 |
rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
|
|
| 3405 | 3405 |
|
| 3406 | 3406 |
add_boot_device_path(s->conf.bootindex, &dev->qdev, "/ethernet-phy@0"); |
| 3407 | 3407 |
|
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