Revision 74475455 hw/serial.c
b/hw/serial.c | ||
---|---|---|
312 | 312 |
We'll be lazy and poll only every 10ms, and only poll it at all if MSI interrupts are turned on */ |
313 | 313 |
|
314 | 314 |
if (s->poll_msl) |
315 |
qemu_mod_timer(s->modem_status_poll, qemu_get_clock(vm_clock) + get_ticks_per_sec() / 100); |
|
315 |
qemu_mod_timer(s->modem_status_poll, qemu_get_clock_ns(vm_clock) + get_ticks_per_sec() / 100);
|
|
316 | 316 |
} |
317 | 317 |
|
318 | 318 |
static void serial_xmit(void *opaque) |
319 | 319 |
{ |
320 | 320 |
SerialState *s = opaque; |
321 |
uint64_t new_xmit_ts = qemu_get_clock(vm_clock); |
|
321 |
uint64_t new_xmit_ts = qemu_get_clock_ns(vm_clock);
|
|
322 | 322 |
|
323 | 323 |
if (s->tsr_retry <= 0) { |
324 | 324 |
if (s->fcr & UART_FCR_FE) { |
... | ... | |
350 | 350 |
s->tsr_retry = 0; |
351 | 351 |
} |
352 | 352 |
|
353 |
s->last_xmit_ts = qemu_get_clock(vm_clock); |
|
353 |
s->last_xmit_ts = qemu_get_clock_ns(vm_clock);
|
|
354 | 354 |
if (!(s->lsr & UART_LSR_THRE)) |
355 | 355 |
qemu_mod_timer(s->transmit_timer, s->last_xmit_ts + s->char_transmit_time); |
356 | 356 |
|
... | ... | |
494 | 494 |
qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_SET_TIOCM, &flags); |
495 | 495 |
/* Update the modem status after a one-character-send wait-time, since there may be a response |
496 | 496 |
from the device/computer at the other end of the serial line */ |
497 |
qemu_mod_timer(s->modem_status_poll, qemu_get_clock(vm_clock) + s->char_transmit_time); |
|
497 |
qemu_mod_timer(s->modem_status_poll, qemu_get_clock_ns(vm_clock) + s->char_transmit_time);
|
|
498 | 498 |
} |
499 | 499 |
} |
500 | 500 |
break; |
... | ... | |
525 | 525 |
if (s->recv_fifo.count == 0) |
526 | 526 |
s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); |
527 | 527 |
else |
528 |
qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock (vm_clock) + s->char_transmit_time * 4); |
|
528 |
qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock_ns (vm_clock) + s->char_transmit_time * 4);
|
|
529 | 529 |
s->timeout_ipending = 0; |
530 | 530 |
} else { |
531 | 531 |
ret = s->rbr; |
... | ... | |
641 | 641 |
} |
642 | 642 |
s->lsr |= UART_LSR_DR; |
643 | 643 |
/* call the timeout receive callback in 4 char transmit time */ |
644 |
qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock (vm_clock) + s->char_transmit_time * 4); |
|
644 |
qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock_ns (vm_clock) + s->char_transmit_time * 4);
|
|
645 | 645 |
} else { |
646 | 646 |
if (s->lsr & UART_LSR_DR) |
647 | 647 |
s->lsr |= UART_LSR_OE; |
... | ... | |
720 | 720 |
fifo_clear(s,RECV_FIFO); |
721 | 721 |
fifo_clear(s,XMIT_FIFO); |
722 | 722 |
|
723 |
s->last_xmit_ts = qemu_get_clock(vm_clock); |
|
723 |
s->last_xmit_ts = qemu_get_clock_ns(vm_clock);
|
|
724 | 724 |
|
725 | 725 |
s->thr_ipending = 0; |
726 | 726 |
s->last_break_enable = 0; |
... | ... | |
734 | 734 |
exit(1); |
735 | 735 |
} |
736 | 736 |
|
737 |
s->modem_status_poll = qemu_new_timer(vm_clock, (QEMUTimerCB *) serial_update_msl, s); |
|
737 |
s->modem_status_poll = qemu_new_timer_ns(vm_clock, (QEMUTimerCB *) serial_update_msl, s);
|
|
738 | 738 |
|
739 |
s->fifo_timeout_timer = qemu_new_timer(vm_clock, (QEMUTimerCB *) fifo_timeout_int, s); |
|
740 |
s->transmit_timer = qemu_new_timer(vm_clock, (QEMUTimerCB *) serial_xmit, s); |
|
739 |
s->fifo_timeout_timer = qemu_new_timer_ns(vm_clock, (QEMUTimerCB *) fifo_timeout_int, s);
|
|
740 |
s->transmit_timer = qemu_new_timer_ns(vm_clock, (QEMUTimerCB *) serial_xmit, s);
|
|
741 | 741 |
|
742 | 742 |
qemu_register_reset(serial_reset, s); |
743 | 743 |
|
Also available in: Unified diff